Data Sheet No. PD94698 IRU3072 20-PIN SYNCHRONOUS PWM CONTROLLER/ 3 LDO CONTROLLER FEATURES DESCRIPTION Synchronous Controller plus 3-LDO controllers Current Limit using MOSFET Sensing Dual Soft-Start Function allows power sequencing Single 5V/12V Supply Operation Programmable Switching Frequency up to 400KHz Fixed Frequency Voltage Mode 1A Peak Output Drive Capability The IRU3072 controller IC is designed to provide a low cost synchronous Buck regulator for on-board DC to DC converter for multi-output applications. The outputs can be programmed as low as 0.8V for low voltage applications. The IRU3072 features dual soft-starts which allows power sequencing between outputs. Over current limit is provided by using external MOSFET's on-resistance for optimum cost and performance. This device features a programmable frequency set from 200KHz to 400KHz, under-voltage lockout for all input supplies, dual external programmable soft-start functions as well as output under-voltage detection that latches off the device when an output short is detected. APPLICATIONS Graphic Card DDR memory source sink VTT application Applications with Multiple Outputs Low cost on-board DC to DC such as 5V to 3.3V, 2.5V or 1.8V Hard Disk Drive TYPICAL APPLICATION 3.3V C2 10uF 2.15K Fb2 R2 1K Q2 1.8V C4 10uF 1.25K 1.5V R4 1K 866V L1 U1 IRU3072 Fb4 R6 1K 3.3K C5 1uF 1uH C6 0.1uF C7 2x 47uF,16V VIN=12V C8 10uF C11 15nF Comp Q4 IRF7460 HDrv OCSet C10 220pF R8 D1 Vc Drv4 R5 C9 10uF C3 1uF Fb3 Q3 VOUT4 VccLDO Drv3 R3 VOUT3 +5V C1 1uF Drv2 R1 VOUT2 2.5V Vcc VSEN33 / SDB Q1 L2 R7 VOUT1 1uH 6.81K 1.2V @ 8A Q5 IRF7460 LDrv C12 3x 330uF, 40m V 6TPB330M, Poscap R9 46.4K Rt SS1 C13 0.1uF C14 33nF SSLDO Gnd R10 499V Fb1 R11 1K PGnd Figure 1 - Typical application of IRU3072. PACKAGE ORDER INFORMATION TA (°C) 0 To 70 Rev. 1.0 3/25/04 DEVICE IRU3072CH PACKAGE 20-Pin MLPQ 4x4 (H) www.irf.com 1 IRU3072 ABSOLUTE MAXIMUM RATINGS Vcc and VccLDO Supply Voltage .............................. Vc Supply Voltage .................................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 25V 25V -65°C To 150°C 0°C To 125°C CAUTION: For all pins, voltage should not be below -0.5V. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. PACKAGE INFORMATION 20-PIN MLPQ 4x4 (H) Fb4 Fb3 Fb2 SSLDO SS1 uJA=468C/W 20 19 18 17 16 Drv4 1 15 Comp Rt VccLDO 4 12 VS E N 3 3/SDB Vcc 5 11 OCSet LDrv 6 7 8 9 10 Vc Fb1 13 HDrv 14 3 Gnd 2 PGnd Drv3 Drv2 ELECTRICAL SPECIFICATIONS Unless otherwise specified, the typical specification value applies over Vcc=5V, Vc=12V, VccLDO=5V and TA=25°C. the Min and Max limits apply to the temperature range from 0 to 70°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM Feedback Voltage Feedback Voltage VFB Fb Voltage Line Regulation LREG UVLO UVLO Threshold - Vcc UVLO VCC UVLO Hysteresis - Vcc UVLO Threshold - Vc UVLO VC UVLO Hysteresis - Vc UVLO Threshold - VccLDO UVLO VCCLDO UVLO Hysteresis - VccLDO UVLO Threshold - VSEN33 UVLO VSEN33 UVLO Hysteresis - VSEN33 UVLO Threshold - Fb1, 2, 3, 4 UVLO Fb1 UVLO Hysteresis - Fb1, 2, 3, 4 Supply Current Vcc Dynamic Supply Current Dyn I CC Vc Dynamic Supply Current Dyn I C Vcc Static Supply Current ICCQ Vc Static Supply Current ICQ 2 TEST CONDITION MIN TYP MAX UNITS 0.784 0.8 0.2 0.816 0.625 V % Supply Ramping Up 3.8 4.6 Supply Ramping Up 3.2 Supply Ramping Up 2.25 Supply Ramping Up 1.17 Fb Ramping Down 0.3 4.2 0.25 3.5 0.2 2.5 0.15 1.27 0.07 0.4 0.02 V V V V V V V V V V 5<Vcc<12 Freq=200KHz, CL=3000pF Freq=200KHz, CL=3000pF SS=0V SS=0V www.irf.com 11 11 5 3 3.8 2.75 1.37 0.5 14 14 8 5 mA mA mA mA Rev. 1.0 3/25/04 IRU3072 PARAMETER Soft-Start Section Charge Current Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance Oscillator Frequency Ramp Amplitude Output Drivers Rise Time SYM SS I B1,IB2 SS1=SS2=0V IFB1 IFB2 Freq VRAMP Tr Fall Time Tf Dead Band Time 1 TDB Dead Band Time 2 TEST CONDITION SS1=3V SS1=0V Rt=100K Rt=39K Note 1 CLOAD=3000pF (10% to 90%) Vcc=12V CLOAD=3000pF (90% to 10%), Vcc=12V Vcc=12V, CLOAD=3000pF HDrv falls,LDrv rises Vcc=12V, CLOAD=3000pF LDrv falls, HDrv rises Fb=0.7V, Freq=200KHz Fb=0.9V DMAX Max Duty Cycle DMIN Min Duty Cycle LDO Controller Section Drive Current Drv2, 3 and 4 Fb Voltage Input Bias Current Thermal Shutdown Note 1 Current Limit IOCSET OC Threshold Set Current VOC(OFFSET) OC Comp Off-Set Voltage Note 1: Guaranteed by design but not tested in production. MIN TYP MAX UNITS 15 25 35 mA 0.1 1 75 1300 mA mA mmho 200 400 1.27 230 460 KHz 50 100 ns 50 100 ns 50 115 150 ns 20 50 100 ns 85 92 0 99 % % 40 0.784 60 0.8 0.5 150 0.816 2 mA V mA 8C 23 -7 30 0 37 +7 mA mV 35 500 170 340 900 VPP PIN DESCRIPTIONS PIN# 1 2 3 4 5 6 7 8 9 Rev. 1.0 3/25/04 PIN SYMBOL PIN DESCRIPTION Drv4 Outputs of the linear regulator controllers. Drv3 Drv2 VccLDO This pin provides power for the LDO controllers. Vcc This pin provides biasing for the internal blocks of the IC as well as power for the low side driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. LDrv Output driver for the synchronous power MOSFET. Gnd This pin serves as the ground pin and must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1mF) must be connected from Vcc, Vc and VccLDO pins to this pin for noise free operation. PGnd This pin serves as the separate ground for MOSFET's driver and should be connected to system's ground plane. HDrv Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from this pin to ground for the application when the inductor current goes negative (Source/ Sink), soft-start at no load and for the fast load transient from full load to no load. www.irf.com 3 IRU3072 PIN# 10 11 12 13 14 15 16 17 18 19 20 4 PIN SYMBOL PIN DESCRIPTION Vc This pin is connected to a voltage that must be at least 4V higher than the bus voltage of the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. OCSet This pin is connected to the Drain of the synchronous MOSFET and it provides the positive sensing for the internal current sensing circuitry. An external resistor programs the current sense (CS) threshold depending on the RDS of the power MOSFET. VSEN33/SDB This pin is used to monitor the 3.3V rail. This pin can be pulled-low to shutdown the outputs. Rt This pin sets the switching frequency with a resistor to Gnd. Fb1 This pin is connected directly to the output of the switching regulator via resistor divider to provide feedback to the Error amplifier. Comp Compensation pin of the error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. SS1 This pin provides soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. SSLDO This pin provides soft-start for the LDO controllers. An internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the LDO controller, preventing it from overshooting as well as limiting the input current. Fb2 These pins provide feedback for the linear regulator controllers. Fb3 Fb4 www.irf.com Rev. 1.0 3/25/04 IRU3072 BLOCK DIAGRAM VSEN33 / SDB 12 3V Bias Generator 1.27V 0.8V 20uA 64uA Max 64uA Max 1.27V / 1.2V 64uA Max Vcc SSLDO 17 Vc 3V VccLDO 20uA POR UVLO 4.2V / 4.0V 3.5V / 3.3V 2.5V / 2.35V 64uA Max SS1 16 13 Rt 10 Vc Rt Oscillator POR Comp Ct Enbl Error Comp 15 9 HDrv 5 Vcc 6 LDrv 8 PGnd 7 Gnd 3 Drv2 2 Drv3 1 Drv4 S Q Error Amp 25K 0.8V R Reset Dom Fb1 25K 14 0.4V 20uA 3V CS Comp OCSet VccLDO 11 POR 64uA3 25K=1.6V When SS=0 FbLo Comp 4 0.8V 25K Fb2 18 Fb3 19 Fb4 20 25K 25K Figure 2 - Simplified block diagram of the IRU3072. Rev. 1.0 3/25/04 www.irf.com 5 IRU3072 TYPICAL APPLICATION 3.3V C2 10uF 2.15K Fb2 R2 1K VccLDO C3 1uF Q2 1.8V Drv3 R3 VOUT3 1.25K R4 1K 1.5V C10 C5 1uF 1uH C6 0.1uF C7 2x 47uF,16V VIN=12V C8 10uF Drv4 R5 C9 10uF L1 U1 IRU3072 Q3 VOUT4 D1 Vc Fb3 C4 10uF +5V C1 1uF Drv2 R1 VOUT2 2.5V Vcc VSEN33 / SDB Q1 866V Fb4 R6 1K 3.3K L2 R7 OCSet 220pF R8 Q4 IRF7460 HDrv 6.81K C11 15nF Comp VOUT1 1uH 1.2V @ 8A Q5 IRF7460 LDrv C12 3x 330uF, 40m V 6TPB330M, Poscap R9 46.4K Rt R10 499V SS1 C13 0.1uF C14 33nF PARTS LIST Ref Desig Description Q1,Q2,Q3 MOSFET MOSFET Q4,Q5 Controller U1 Schottky Diode D1 Inductor L1 Inductor L2 Capacitor C1,C3 C2,C4,C9 Capacitor Capacitor C5 Capacitor C6,C13 Capacitor C7 Capacitor C8 Capacitor C10 Capacitor C11 Capacitor C12 Capacitor C14 Resistor R1 R2,R4,R6 Resistor Resistor R3 Resistor R5 Resistor R7 Resistor R8 Resistor R9 Resistor R10 Resistor R11 6 SSLDO Gnd Fb1 R11 1K PGnd Figure 3 - Typical application of IRU3072. Value Qty Part# 30V, 65mV, 22A 3 IRLR2703 20V, 10mV, 12A 2 IRF7460 Synchronous PWM 1 IRU3072 0.2A, 30V 1 BAT54S 1mH, 2A 1 DS1608C-102 1mH 1 DO3316P-102HC 1mF, Y5V, 16V 2 ECJ-2VF1C105Z 10mF 3 1mF, X7R, 25V 1 ECJ-3YB1E105K 0.1mF, Y5V, 25V 2 ECJ-2VF1E104Z 47mF, 16V 2 16TPB47M 10mF 1 220pF, X7R 1 ECU-V1H221KB 15nF 1 ECJ-2VB1H153K 330mF, 6.3V, 40mV 3 6TPB330M 33nF, X7R 1 ECJ-2VB1H333K 2.15K, 1% 1 1K, 1% 3 1.25K, 1% 1 866V, 1% 1 6.81K, 1% 1 3.3K, 1% 1 46.4K, 1% 1 499V, 1% 1 1K, 1% 1 www.irf.com Manuf Web site (www.) IR irf.com IR IR IR Coilcraft coilcraft.com Coilcraft Panasonic maco.panasonic.co.jp Panasonic Panasonic Sanyo Any Panasonic Panasonic Sanyo Panasonic Any Any Any Any Any Any Any Any Any sanyo.com maco.panasonic.co.jp sanyo.com maco.panasonic.co.jp Rev. 1.0 3/25/04 IRU3072 APPLICATION INFORMATION The IRU3072 controller IC is designed to provide a low cost synchronous Buck regulator for on-board DC to DC converter as well as three linear regulator controllers. It is specially designed for multiple output applications. The outputs can be programmed as low as 0.8V. The IRU3072 provides two separate soft-starts. It not only allows different output power sequences, but also allows shutdown of LDO and PWM output regulators individually. The IRU3072 provides cycle-by-cycle current limit and output feedback under-voltage lockout. Power Sequence and Under-Voltage Lockout For correct operation, proper power sequence should be ensured. Typically, there are four or five input voltages involved. Vcc: IC biasing voltage. VSEN33: LDO Input voltage, for example 3.3V VccLDO: Input biasing voltage for IRU3072 internal LDO controller. VBUS : Input voltage for synchronous buck converter. Vc: Input biasing voltage for IRU3072 internal high side MOSFET drivers. The power sequence should be proper such that softstart capacitors (for both LDO and PWM) start to be linearly charged up right after the above five voltages enter into steady state, as shown in the following figure. The IRU3072 senses four voltages with under-voltage lockout (UVLO) block. The voltages Vcc, Vc and VccLDO are sensed through the UVLO block. The LDO input voltage can be sensed through pin VSEN33. Although synchronous bus voltage (VBUS ) is not sensed, in practical, it can be sensed indirectly. Typically, only two or three input voltages are available. Some of the five input voltages have to either share or be generated by another method such as charge pump. One example of IRU3072 application with only two input voltages, 5V and 3.3V, is shown in figure 5. In this example: VBUS = Vcc = 5V Vc = VccLDO created by charge pump VSEN33 = 3.3V The IRU3072 will sense all four voltages to ensure all these voltages enter into steady state before the softstart capacitor is charged up. The operation waveforms are shown in Figure 6. 3.3V VSEN33 / SDB U1 IRU3072 Drv2 Fb2 Vcc UVLO VccLDO L1 Vc Input Voltage VCC,VCCLDO, VBUS,Vc, etc VBUS =5V C6 UVLO Threshold Voltage Soft-Start HDrv Q4 R7 L2 VOUT1 OCSet Soft-Start Voltage for PWM VSS SS1 Soft-Start Voltage for LDO VSSLDO LDrv SSLDO Q5 C10 Figure 5 - IRU3072 application with only two power inputs: 5V and 3.3V. Figure 4 - Desired power sequence. Rev. 1.0 3/25/04 www.irf.com 7 IRU3072 Figure 6 - Power sequence. If there are three input voltage sources available, such as 3.3V, 5V and 12V, the possible connections to ensure proper operation are shown in the following table. Option 1 2 3 4 more Vcc 5V 5V 12V 12V VBUS 5V 12V 12V 5V Vc 12V CP CP 12V VccLDO LDO Input 12V 3.3V 12V 3.3V 12V 3.3V 12V 3.3V The soft-start operation can ensure the output voltage ramps up to the regulated voltage without surge of the current. The IRU3072 also has an output feedback UVLO block, which will turn off both high side and low side MOSFET driver when the voltage at pin Fb1,Fb2,Fb3 or Fb4 is below 0.4V. The feedback UVLO is used to protect the system when the output is in short circuit. However, during the power on of the buck converter, the output of buck converter starts from zero and the voltage at pin Fb1 will be below 0.4V. The feedback UVLO should be disabled when soft-start capacitor voltage ramps up and down. This is achieved by injecting a current into the Fb1 pin (also Fb2, Fb3 and Fb4) during the soft-start and the magnitude of this current is inversely proportional to the voltage at soft-start pin (SS or SSLDO). The diagram is shown in Figure 7 and operation waveforms are shown in Figure 8. The operation principle is as follows: Initially, the buck converter’s output voltage and the voltage at pin Fb1 are both zero. The voltage at soft-start pin “SS” is almost zero and about 64mA current will inject to the pin of Fb1 through a 25KV internal resistor. The voltage at the negative input of Error Amplifier and the positive input of the feedback UVLO comparator is approximately: 64mA325KV = 1.6V Table: Possible combination of input voltage source connections to ensure proper start-up operation. (CP refers to Charge Pump) 3V 20uA HDrv SS1 There are many possible combinations of input voltage source connections and the table above lists only a few of them. Most importantly for a proper power sequence, the soft-start capacitor has to be charged up after all the input voltage sources are established. 64uA Max POR Comp Soft-Start One of the useful features of IRU3072 is that it allows different start-up times for PWM output and LDO output by programming two separate soft-start capacitors. Figure 7 just shows the soft-start for PWM section. 25K Error Amp LDrv 0.8V 25K Fb1 0.4V 64uA325K=1.6V When SS=0 POR Feeback UVLO Comp Figure 7 - IRU3072 soft-start diagram. 8 www.irf.com Rev. 1.0 3/25/04 IRU3072 Output of UVLO POR From the above analysis, the output start up time is the period when soft-start capacitor voltage increases from 1V to 2V. The start up time will be dependent on the size of the external soft-start capacitor. The start up time can be estimated by: 3V ≅2V ≅1V Soft-Start Voltage Current flowing into Fb1 pin 20mA3tSTART /CSS ≅ 2V-1V 0V 64uA For a given start up time, the soft-start capacitor can be estimated as: 0uA Voltage at negative input ≅1.6V of Error Amp and Feedback UVLO comparator CSS ≅ 20mA3tSTART /1V 0.8V For 5ms start up time, a 0.1mF soft-start capacitor is required. In practice, the 20mA current will slightly decrease as the soft-start voltage goes up. Therefore, for a 0.1mF soft-start capacitor, start up time may be slightly longer, e.g. 6ms. 0.8V Voltage at Fb1 pin ---(1) 0V Figure 8 - Theoretical operation waveforms during soft-start. When the power voltage such as Vcc go into steady state and the output of voltage UVLO “POR” goes high, a 20uA current source charges the external soft-start capacitors. The soft-start voltage ramps up. In the mean time, the current flowing into pin Fb1 starts to decrease linearly and so does the voltage at the positive pin of feedback UVLO comparator and the voltage at the negative input of Error amplifier. When the soft-start capacitor voltage is around 1V, the current flowing into the Fb1 pin is approximately 32mA. The voltage at the positive input of the Error amplifier is approximately: The soft-start waveforms are shown in Figure 9. In this figure, the start up time for the buck converter VOUT1 and LDOs is different by selecting separate soft-start capacitors. For PWM: CSS = 0.1mF, tSTART ≅ 5ms For LDOs: CSSLDO = 33nF, tSTART ≅ 2ms 32mA325KV = 0.8V The Error Amplifier will start to operate and the output voltage starts to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb1 pin will keep decreasing. Because the voltage at pin of Error Amplier is regulated to reference voltage 0.8V, the voltage at the Fb1 pin is: VFB1 = 0.8V-25KV3(Injecting Current) The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 2V and the output voltage goes into steady state. Figure 8 shows that the voltage at the positive pin of feedback UVLO comparator is always higher than 0.4V, therefore, feedback UVLO is not functional during softstart. Rev. 1.0 3/25/04 Figure 9 - Soft-start of buck converter (PWM) and LDO. Shutdown The PWM output and LDO output can be turned on and off individually by pulling up and down the corresponding soft start capacitors. www.irf.com 9 IRU3072 (a). Shutdown and start up PWM output by controlling soft start SS1. LDO output such as Vout2 will not be affected. Figure 11 - Operation waveforms when PWM converter is shutdown by pulling down the soft-start capacitor. Both PWM output and LDO output can be shutdown by pulling the pin VSEN33/SDB down. One example is shown as follows. External Shutdown U1 IRU3072 3.3V 4.7K VSEN33 / SDB Drv2 Fb2 Vcc UVLO VccLDO (b). Shutdown and start up LDO output by controlling soft-start SSLDO. PWM output VOUT1 will not be affected. L1 Vc Figure 10 - Shutdown PWM or LDO by controlling soft-start. Soft-Start C6 HDrv Q4 R7 One issue related to shutdown of PWM output by pulling down the soft-start, there is a small negative voltage shown in the output during the shutdown. It is because the low side MOSFET driver is on when the soft-start capacitor voltage is pulling down. The output inductor resonates with output capacitor and load. This occurs especially often when output current is small (light load or no load condition). The operation waveforms are shown as follows. 10 VBUS =5V L2 VOUT1 OCSet LDrv SS1 www.irf.com Q5 C10 SSLDO Figure 12 - External shutdown by using pin VSEN33/SDB. Rev. 1.0 3/25/04 IRU3072 The LDO and PWM output can be shutdown by using a transistor to pull down the pin VSEN33/SDB as shown in Figure 12. Because the VSEN33/SDB pin also senses the LDO input voltage for the power UVLO block, a high impedance resistor such as 4.7K has to be inserted between VSEN33/SDB pin and the input of LDO such as 3.3V. The input voltage UVLO operation will not be affected due to the high input impedance nature of VSEN33/SDB pin. The operation waveforms is shown as follows: 3V VBUS IRU3072 20uA Q1 RSET CS Comp L VOUT OCSet Enb Oscillator Q2 S HDrv Q R LDrv Rf1 Fb1 Rf2 0.4V Err Comp Figure 14 - IRU3072 current limit diagram. The operation is illustrated in Figure 15. Feedback V REF voltage 0.4V Figure 13 - Shutdown by pulling down pin VSEN33/SDB. One feature of shutdown by pulling down VSEN33/SDB is that there is no negative voltage shown in the buck converter output because both high side and low side MOSFET drivers are off after shutdown. Over Current Protection The IRU3072 over current protection is achieved with a cycle-by-cycle current limit and an output voltage undervoltage lockout scheme. The diagram is shown in Figure 14. It includes an over current comparator and an output voltage UVLO comparator. The current is sensed through the RDS(ON) of the low side MOSFET. A resistor, RSET , is connected from OCSet pin to the drain of the low side MOSFET in order to set the over-current limit. When the low side MOSFET Q2 is ON, the inductor current flows through MOSFET Q2. The voltage at OCSet pin is given as: VOCSet =20mA3RSET -iL3RDS(ON) When voltage VOCSet is below zero, the current sensing comparator flips and disables the oscillator. The high side MOSFET is turned off and the low side MOSFET is on until the inductor currents reduces to below current setting value. The critical inductor current can be calculated by setting: VOCSet = 20mA3RSET -iL3RDS(ON) = 0 ISET = i L(critical) = 20mA3RSET /RDS(ON) Rev. 1.0 3/25/04 IOUT FS(NOM) Switching frequency High Side MOSFET turn on time (tON) IOUT DMAX FS(NOM) VOUT FS(NOM) 3VIN IOUT <I L>=IOUT Average Inductor Current IO(NOM) IO(LIM) Normal Over Current operation Limit Mode IOUT Shutdown by UVLO Figure 15 - Operation of IRU3072 current limit and UVLO. During the normal operation mode, the synchronous buck converter operates in fixed frequency FS(NOM), which is the normal operation switching frequency and it is determined by the external resistor Rt. The output voltage is regulated to the desired voltage and the feedback voltage is equal to the reference voltage VREF. The turn on time of the high side MOSFET is given as: tON(normal) ≅ D3TS(NOM) = V OUT /(FS(NOM)3VIN) ---(2) www.irf.com 11 IRU3072 As the load current goes up, the inductor current increases and the high side MOSFET’s turn on time increases a little due to the voltage drop across the high side MOSFET RDS(ON). As the output current increases to limit current, I L=IO(LIM), which is set by the resistor RSET . The buck converter will go into cycle-by-cycle current limit mode. The operation waveforms of IRU3072 during cycle-by-cycle current mode is shown in Figure 16. Inductor Current iL(VALLEY) iL(PEAK) iL(AVG) From Figure 16, first, the high side MOSFET is on for tON period and the inductor current increases during this time. Then, the high side MOSFET is off and low side MOSFET is on. Because the inductor current is higher than the critical inductor current ISET , the current sensing comparator goes high and the low side MOSFET keeps on. The inductor current is discharged by the output voltage. When the inductor current is below setting current or critical current I SET , the current sensing comparator goes low and enables the oscillator. The high side MOSFET is turned on again and next cycle starts. The operation frequency is only dependent on the current sensing comparator and the internal clock frequency is modified by current limit. ISET In conclusion, from Figures 15 and 16, two big differences exist between normal operation and current limit mode. First, during current limit mode, the valley inductor current is determined by I SET . Current Limit Comparator Output Internal Clock ISET = iL(VALLEY) MOSFET Driver HDrv Second, in Figures 15 and 16, the frequency in current limit mode, is lower than normal operation frequency. D3 TS(NOM) TS(NOM) In general, the output current is represented by: (a) Normal operation. IOUT = iL(AVG)=iL(VALLEY)+DIPK_PK /2 Where DIPK_PK is the peak to peak inductor current ripple which is given by: Internal Clock at normal operation DIPK_PK = iL(PK)-iL(VALLEY) = (VIN-VOUT )3tON/L Figure 15 shows that the operation frequency of the buck converter decreases as output current goes up during current limit mode. The on time of high side MOSFET is controlled by the output voltage loop so that the voltage at Fb pin, still equals the reference voltage, VFB=VREF. The output voltage is regulated to the desired voltage. Internal Clock at current limit Inductor iL(PEAK) iL(AVG) Current ISET=iL(VALLEY) Current Limit Comparator Output High Side MOSFET Driver HDrv tON As a result: tON = VO(NOM)/VIN/FS tOFF IOUT(Current Limit Mode) = I SET + (VIN-VO(NOM))3VO(NOM) (23L3VIN3Fs) (b). Operation at current limit mode. Figure 16 - Cycle-by-Cycle operation when IRU3072 is in over-current limit mode. 12 Where VO(NOM) is the nominal output voltage and it is determined by the feedback resistor and reference voltage as shown in Figure 14. The above equation indicates that the operation frequency is inversely proportional to the output current during the current limit mode. For practical application, the most important is setting up the over current limit threshold. From Figure 15, at the current limit threshold IO(LIM), the frequency is still equal to nominal operation frequency. www.irf.com Rev. 1.0 3/25/04 IRU3072 FS = FS(NOM) Therefore, the output current limit threshhold is set by: IOUT(LIM) = I SET + DIPK_PK(LIM) 2 Where: DIPK_PK(LIM) = (VIN-VO(NOM))3VO(NOM) (VIN3FS(NOM)3L) From equation (2), the over current limit set resistor can be calculated by: RSET = ISET 3RDS(ON) 20mA RSET = (IOUT(LIM)-DIPK_PK(LIM)/2)3RDS(ON)/20mA ---(3) (a). Normal operation. Where RDS(ON) has to choose the maximum over the temperature for the selected MOSFET. Overall, the profile of current limit operation is shown in Figure 17. Over Current Limit Mode Normal Operation FS(NOM) Shutdown by UVLO Switching Frequency ISET IO(LIM) IO(MAX) IOUT Select inductor L, frequency FS(NOM), IO(LIM) Calculate: ∆I PK_PK(LIM) = (V IN-V O(NOM))3 V O(NOM) VIN3 L 3 F S(NOM) Set: ISET = IO(LIM)-∆IPK_PK/2 (b). Current limit mode. Figure 18 - Operation waveforms during normal and current limit mode. Select: R SET = ISET3 RDS(ON)/20m A Figure 17 - Profile of operation switching frequency versus output current. Rev. 1.0 3/25/04 www.irf.com 13 IRU3072 450 400 Frequency (KHz) 350 300 250 200 Fs(measured) Fs(predicted) 150 100 50 0 0 2 4 6 8 10 Iout (A) Figure 19 - Profile of switching frequency versus output current -predicted and measured. Figure 18 (a) shows normal operation waveforms for a 12V input 1.6V output 400KHz buck regulator. During normal operation, the switching frequency is 400KHz. Figure 18 (b) shows the operation waveforms during current limit mode. The switching frequency is reduced and output ripple increases. Figure 19 shows the profile of switching frequency versus output current. When the output current goes up and hit the over current limit, the switching frequency starts to decreases. Due to the output voltage loop, the output voltage will keep the regulation except the ripple increases. As the output current keeps going up. The output voltage will start to decrease until the feedback voltage Fb is under 0.4V. The output voltage under lockout takes over and turns off both high side and low side MOSFET. The output voltage reduces to zero. Output Feedback UVLO Besides the cycle-by-cycle current limit, an output feedback UVLO is included in the IRU3072 for the output short protection. The diagram is shown in Figure 14. If the output is short or overload, once the voltage at the Fb1 pin is below 0.4V, the output feedback UVLO comparator will flip and turn off both high side and low side MOSFETs. The output of converter will decrease to zero. The operation when PWM output is in short circuit condition is shown in Figure 20. If either PWM or LDO output is in short condition, it will turn off all outputs. The operation waveforms are shown in Figures 21 and 22. Figure 23 shows a soft-start operation when the output is short. Because of current limit and output feedback UVLO, the output will be turned off and the system protected. 14 Figure 20 - Operation waveforms when output of buck converter is short to ground. The output UVLO senses the four feedback pin voltages Fb1,Fb2,Fb3,Fb4. If any of the feedback voltages are below 0.4V, all four outputs will be shutdown. Figure 21 - Operation of PWM output and LDO when PWM output is short to ground. www.irf.com Rev. 1.0 3/25/04 IRU3072 Design Example Input voltage for buck converter: VIN=12V Output voltage for buck converter: VOUT =1.2V Nominal output current from switching regulator: IOUT =8A Output current limit is 10A. Switching frequency: FS=400KHz The maximum dynamic output voltage droop at 8A step load is 150mV. LDO specification LDO input voltage: VIN(LDO)=3.3V LDO output1: VOUT2=2.5V @ 2A LDO output2: VOUT3=1.8V @ 2A LDO output3: VOUT4=1.5V @ 2A Figure 22 - Operation of PWM output and LDO when LDO VOUT2 is short. Output inductor selection The inductor is selected based on the inductor current ripple, operation frequency and efficiency consideration. In general, a large inductor results in a small output ripple and higher efficiency but large size. A small value inductor causes large current ripple and poor efficiency but small size. Generally, the inductor is selected based on the output current ripple. The optimum point is usually found between 20% and 50% ripple of output inductor current. Suppose the ripple is selected as 40% of the total output current. DIPK_PK /IOUT = 40% The current ripple is calculated as: DIPK_PK = (VIN-VOUT )3VOUT /(L3FS3VIN) Figure 23 - Soft-start with output is short to ground. Switching frequency The switching frequency of IRU3072 can be selected by the following figure. 500 450 Frequency (KHz) 400 350 Combining of above two equations, the inductance can be selected by: L > VOUT 3(VIN-VOUT )/(FS3VIN340%3IOUT ) In this example, L > 1.2V3(12 - 1.2)/(400KHz312V30.438A) L > 0.8mH Select inductor from Panasonic so that L=1mH. The ripple current is calculated as: DIPK_PK = (12 - 1.2)31.2/(1mH3400KHz312) DIPK_PK ≅ 2.7A 300 250 200 150 100 50 0 0 50 Rt (KV V) 100 150 200 Figure 24 - Switching frequency versus resistor Rt. Rev. 1.0 3/25/04 www.irf.com 15 IRU3072 Output capacitor selection The voltage rating of the output capacitor is the same as the output voltage. Typical available capacitors on the market are electrolytic, tantalum and ceramic. If electrolytic or tantalum capacitors are employed, the criteria is normally based on the value of Effective Series Resistance (ESR) of total output capacitor. In most cases, the ESR of the output capacitor is calculated based on the following relationship: ESR < DVRIPPLE(SPEC)/DIPK_PK or ESR < DVSTEPLOAD(SPEC)/DISTEPLOAD(MAX) If output inductor current ripple is neglected, the RMS current of high side switch is given by: D = VOUT /VIN = 0.1 IRMS(HI) = D3IOUT = 0.138A = 2.53A The RMS current of low side switch is given as: IRMS(HI) = Depending on which one is the requirement. Where: DVRIPPLE(SPEC) is the maximum allowed voltage ripple. DIPK_PK is the current ripple. DVSTEPLOAD(SPEC) is the maximum allowed voltage droop during the transient or step load. DISTEPLOAD(MAX) is the maximum step load current. In this example: DVSTEPLOAD(SPEC) = 150mV DISTEPLOAD(MAX) = 8A The required ESR is calculated as: ESR < 150mV/8A = 18.75mV Select three Sanyo POSCAP 6TPB330M with 6.3V 330mF and 40mV ESR will give about 13mV, which will meet the specification. Input capacitor Selection Input capacitor is dertermined by the voltage rating and input RMS current. For this application, the input RMS current is given as: IIN(RMS) = I OUT 3 D3(1-D) D = VOUT /VIN = 1.2V/12V ≅ 0.1 1-D3IOUT = 1-0.138A = 7.6A For low side MOSFET, if it is driven by 5V, a logic gate driver MOSFET is preferred. For RDS(ON) of the MOSFET, it should be as small as possible in order to get highest efficiency. A logic driver MOSFET such as IRF7460 from International Rectifier in a SOIC 8-pin package, RDS(ON)=10mV, 20V drain source voltage rating and 12A IDS is selected for high side and low side MOSFET. Power Dissipation for MOSFETs The power dissipation for MOSFETS typically includes conduction loss and switching losses. For high side switch, the conduction loss is estimated as: PCOND(HI) = D3IOUT 3IOUT 3RDS(ON)MAX The RDS(ON) has to consider the worst case. In the datasheet of IRF7460: RDS(ON)MAX = 14mV @ Vgs = 4.5V PCOND(HI) = 0.138A38A314mV ≅ 0.09W The switching loss is more difficult to calculate because of the parasitic parameters. In general, the switching loss can be estimated by the following: PSW = 0.53VDS 3IOUT 3(tr+tf)3FS tr is the rising time and tf is the falling time. From IRU3072 datasheet: tr=50ns and tf=50ns The input RMS current is estimated as: IIN(RMS) = 8A3 ment for each MOSFET is almost the same. If logiclevel or 3V driver MOSFET is used, some caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through circuit. 0.13(1-0.1) ≅ 2.4A Select two Sanyo POSCAP -16TPB47M with 16V, 47mF and 1.4A ripple current. A 1mH, 1A small input inductor is enough for the input filer. PSW(HI) = 0.5312V38A3(50ns+50ns)3400KHz PSW(HI) ≅ 1.92W The total disspation for the high side switch is: PD(HI) = PSW(HI)+PCOND(HI) ≅ 2W Power MOSFET Selection In general, the MOSFET selection criteria depends on the maximum drain-source voltage, RMS current and ON resistance (RDS(ON)). For both high side and low side MOSFETs, a drain-source voltage rating higher than maximum input voltage is necessary. In the demo-board, 20V rating should be satisfied. The gate drive require- 16 For low side switch, most of the loss are conduction loss. The low side switch power dissipation is: PD(LO) ≅ PCOND(LO) = (1-D)3IOUT 3IOUT 3RDS(ON)MAX PD(LO) ≅ PCOND(LO) = (1-0.1)38A38A314mV PD(LO) ≅ PCOND(LO) = 0.81W www.irf.com Rev. 1.0 3/25/04 IRU3072 Estimated Temperature Rise for MOSFET The estimated junction temperature of the MOSFET is given by: TJ = TA+PD3RuJA Where: TJ is the junction temperature. TA is the ambient temperature. PD is the power dissipation. RuJA is the junction-to-ambient thermal resistance with MOSFET on 1" square PCB board and is from the data sheet. For low side MOSFET IRF7460, with 4.5V gate voltage and maximum RDS(ON) of 14mV, then: RSET = 8.7A314mV/20mA = 6.09KV Select R7=RSET =6.8KV (4) Compensation Design VOUT IRU3072 Rf1 VFB For MOSFET IRF7460 with SOIC 8-pin package, RuJA=508C/W. Assume ambient temperature is TA=358C. For high side MOSFET, the junction temperature is given as: TJ = TA+PD3RuJA = 35+2350 = 1358C < 1508C Error Amp gm Rf2 1V Cc1 Rc1 Comp For low side MOSFET IRF7460, the maximum junction temperature can be calculated as: Cc2 (Optional) TJ = TA+PD3RuJA = 35+0.81350 = 768C < 1508C The maximum junction temperature of both MOSFETs is below the maximum rating of 1508C. Controller Parameter Calculation (1) Frequency Selection From Figure 23, the frequency setting resistor can be chosen to be Rt=47KV, which gives us approximately 400KHz frequency. (2) Soft-Start Capacitor Soft-start capacitor for PWM secton is selected from equation (1). Select start up time tSTART =5ms: CSS = 20mA3tSTART = 20mA35ms = 0.1mF Select C11=CSS=0.1mF (3) Over Current Limit Setting The over current limit resistor can be calculated based on Figure 17. The output current limit is set by: IO(LIM) = 10A The current ripple during nomral operation (400KHz) is given by: DIPK_PK = (12-1.2)31.2/(1mH3400KHz312) DIPK_PK ≅ 2.7A The over current setting I SET is: Figure 25 - Type II compensator. For electrolytic capacitor, the frequency caused by ESR is typically at a few KHz range. A type II compensator is a good option. The detailed description is shown in application note AN-1043 from: http://www.irf.com/technical-info/appnotes.htm Select the zero crossover frequency to be 1/10 of switching frequency that is 40KHz: FO = 40KHz The compensation resistor can be calculated as: Rc1= Where VOSC is the oscillator peak to peak voltage and gm is the transconductance of the error amplifier. From the datasheet we get VOSC=1.25V and gm =1000mmho. The calculated compensation resistor is: Rc1=2p3403131.2531.2/(133123100030.8) Rc1=2.98K Select R8=Rc1=3.3K The compensator capacitor is given as: ISET = I O(LIM)-DIPK_PK/2 = 10A-2.7A/2 ≅ 8.7A Cc1 = The over current setting resistor: (L3COUT )/0.75/Rc1 Cc1 = (1mH3450mF)/0.75/3.3K = 10nF Select C9=Cc1=15nF RSET = I SET 3RDS(ON)/20mA Rev. 1.0 3/25/04 2p3FO3L3VOSC3VOUT (ESR3VIN3gm 3VREF) www.irf.com 17 IRU3072 (Optional) an additional capacitor Cc2 can be adopted, where: Cc2 ≅ 1/(p3Rc13FS) ≅ 220pF RuSA<(TJ-TA)/PD-RuJC-RuCS In this example, the MOSFET is mounted in the copper area more than 1 square inch. The estimated junction temperaure is: (5) Feedback resistor The output of PWM is determined by: VOUT = V REF3(RT+RB)/RB or RT = (VOUT /VREF-1)3RB TJ=TA+PD3RuJA Where VREF=0.8V RT is the top feedback resistor and RB is bottom feedback resistor.For 1.2V output, RT =499V, RB=1K. LDO Regulator Component Selection and LDO Power MOSFET Selection The first step in selecting the power MOSFET for the linear regulator is to select its maximum RDS(ON) based on the input to output dropout voltage and maximum load current. For VOUT2=2.5V, VIN(LDO)=3.3V and I OUT2=2A: Where RuJA is the thermal resistance from junction to ambient with PCB mounted. For IRLR2703s, RuJA=508C/W, Assume: TA = 358C TJ = 35+1.5W3508C/W = 1108C < 1508C The thermal managment can meet the requirement. VccLDO Selection For LDO, the LDO controller supply voltage has to satisfy the following: VCC(LDO) > VLDO(OUT)MAX+VGS(TH)MIN+2VBE RDS(ON)MAX = (VIN(LDO)-VOUT2)/IOUT2 RDS(ON)MAX = (3.3V-2.5V)/2.0A = 0.4V Note that the MOSFET’s RDS(ON) increases with temperature, the calculated RDS(ON) has to be divided by the RDS(ON) temperature coefficienct (about 1.5) in order to get typical RDS(ON). IRLR2703s from Internation Rectifier with D2 package, 30V, VDS logic drive and 65mV is good enough to meet the requirement. To select the heat sink for the LDO MOSFET, the first step is to calculate the maximum power dissipation of the device: PD = (VIN(LDO)-VOUT )3IOUT PD = (3.3V-2.5V)32A = 1.4W The junction temperature of MOSFET can be estimated by the following formula: TJ = TA+PD3(RuJC+RuCS+RuSA) TJ should be < TJ(MAX) @ 1508C Where: VLDO(OUT)MAX is the maximum output voltage VGS(TH)MIN is the minimum LDO MOSFET gate threshold voltage VBE is the diode drop, approximately 0.6V For this example, VGS(TH)MIN of MOSFET IRLR2703s, is 1V. Then: VCC(LDO) > 2.5V+1V+230.6V = 4.7V Select VCCLDO=12V for proper power sequence LDO Feedback Resistor Selection The output of LDO is determined by: VOUT = V REF3(RT+RB)/RB Where: VREF=0.8V RT is the top feedback resistor and RB is bottom feedback resistor. For 2.5V output, if RB=1K then: RT = (VOUT /VREF-1)3RB = (2.5/0.8-1)31K = 2.12K Where: TJ = the estimated junction temperature. TA = the ambient temperature. PD = the power disspation. RuJC = the thermal resistance from junction to case. RuCS = the thermal resistance from case to heat sink. RuSA = the thermal resistance from heat sink to ambient. 18 The required thermal resistance of heat sink should be Select Rt=2.15K LDO Soft-Start Capacitor The soft-start capacitor can be estimated from equation (1). Select start up time as 2ms: CSS(LDO) = 20mA3tSTART = 20mA32ms = 0.04mF Select C12=CSS(LDO)=33nF www.irf.com Rev. 1.0 3/25/04 IRU3072 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. APPLICATION EXPERIMENTAL WAVEFORMS for Application Circuit in Figures 1 and 3 Figure 26 - Transient response with 8A load. Figure 27 - Transient response (zoomed). Figure 28 - Transient response (zoomed). Rev. 1.0 3/25/04 www.irf.com 19 IRU3072 TYPICAL APPLICATIONS 3.3V VSEN33 / SDB Q1 IRLR2703 VOUT2 2.5V Fb2 2.15K C2 R2 1K Vc Fb3 1.24K C4 VccLDO Drv3 R3 R4 1K L1 C5 1uF U1 IRU3072 C6 0.1uF 1uH C7 16TPB47M 47uF, 16V VIN=5V C8 10uF Drv4 Q3 VOUT4 1.5V C1 1uF R1 Q2 VOUT3 1.8V Vcc Drv2 R5 Fb4 866 C9 C10 Q4 IRF7460 HDrv R6 1K L2 1uH R7 OCSet 100pF VOUT1 1.2V @ 8A 6.8K R8 C11 10nF 6.8K Q5 IRF7460 LDrv Comp C12 3x 6TPB330M 6.3V, 330uF, 40mV R9 Rt 46.4K R10 SS1 C13 0.1uF C14 33nF Fb1 SSLDO Gnd R11 1K PGnd 1K Figure 29 - IRU3072 typical application with one bus input voltage VCC=VBUS =5V and 3.3V for LDO. 3.3V VOUT2 2.5V R1 Fb2 2.15K C2 R2 1K 1.24K C4 VccLDO Drv3 R3 12V Vc C3 1uF Fb3 R4 1K Q3 VOUT4 1.5V C1 1uF Drv2 Q2 VOUT3 1.8V Vcc VSEN33 / SDB Q1 IRLR2703 L1 U1 IRU3072 1uH C7 16TPB47M 47uF, 16V VIN=5V C8 10uF Drv4 R5 Fb4 866 C9 C10 R6 1K OCSet 100pF R8 6.8K Q4 IRF7460 HDrv 1uH 6.8K C11 10nF Comp Q5 IRF7460 LDrv R9 46.4K C14 33nF VOUT1 0.8V C12 3x 6TPB330M 6.3V, 330uF, 40m V Rt SS1 C13 0.1uF L2 R7 SSLDO Gnd Fb1 PGnd Figure 30 - IRU3072 Typical application with 5VBUS input and 12V for the driver (charge pump is saved). 20 www.irf.com Rev. 1.0 3/25/04 IRU3072 TYPICAL APPLICATIONS 3.3V VSEN33 / SDB Q1 IRLR2703 VOUT2 2.5V R1 R2 1K Q2 VOUT3 1.8V 1.24K R4 1K D2 L1 U1 IRU3072 Fb4 866 C10 D1 Vc C5 1uF VIN=12V 1uH C6 0.1uF C8 10uF C7 47uF,16V Drv4 R5 C9 C3 1uF Fb3 Q3 VOUT4 1.5V VccLDO Drv3 R3 C4 +5V C1 1uF Fb2 2.15K C2 Vcc Drv2 Q4 IRF7460 HDrv R6 1K L2 R7 OCSet 82pF R8 C11 3.3nF 10K 1.2V @ 5A C12 2x 47uF Ceramic Q5 IRF7460 LDrv Comp VOUT1 1uH 4.7K R9 47K Rt R10 62K SS1 C13 0.1uF C14 33nF R11 4.64K C15 220pF SSLDO Fb1 Gnd PGnd R12 124K Figure 31 - IRU3072 typical application with ceramic capacitor output. 3.3V VSEN33 / SDB Q1 IRLR2703 VOUT2 2.5V Fb2 2.15K C2 R2 1K 1.24K C4 R4 1K L1 U1 IRU3072 Fb4 R6 1K R8 C6 0.1uF C7 16TPB47M 47uF, 16V Q4 IRF7460 HDrv C8 10uF L2 1uH R7 VOUT1 1.2V 6.8K C11 15nF Comp Q5 IRF7460 LDrv C12 3x 6TPB330M 6.3V, 330uF, 40mV R9 47K Rt R10 SS1 C13 0.1uF VIN=12V 1uH OCSet 220pF 3.3K C5 1uF Drv4 866 C10 Vc Fb3 R5 C9 VccLDO Drv3 R3 Q3 VOUT4 1.5V 200V C1 1uF Drv2 R1 Q2 VOUT3 1.8V R12 Vcc C14 33nF SSLDO Gnd Fb1 R11 1K PGnd 1K Figure 32 - IRU3072 typical application with one bus input voltage VCC=VBUS =12V and 3.3V for LDO. Rev. 1.0 3/25/04 www.irf.com 21 IRU3072 TYPICAL APPLICATION R13 1K 3.3V VSEN33 / SDB Q1 IRLR2703 VOUT2 2.5V Drv2 Fb2 R2 1K Q2 VOUT3 1.8V Drv3 Vc 1.24K Fb3 R4 1K R5 C10 U1 IRU3072 Fb4 866 C9 L1 C5 1uF C6 0.1uF 1uH C7 16TPB47M 47uF, 16V VIN=12V C8 10uF Drv4 Q3 VOUT4 1.5V VccLDO R3 C4 200V C1 1uF R1 2.15K C2 R12 Vcc R6 1K R8 L2 R7 OCSet 220pF 3.3K Q4 IRF7460 HDrv 1uH 6.8K C11 15nF Comp Q5 IRF7460 LDrv R9 47K C14 33nF C12 3x 6TPB330M 6.3V, 330uF, 40mV Rt R10 SS1 C13 0.1uF VOUT1 3.3V SSLDO Gnd Fb1 R11 1K PGnd 3.125K Figure 33 - IRU3072 typical application with one bus input voltage VCC=VBUS =12V to generate all LDO output. 22 www.irf.com Rev. 1.0 3/25/04 IRU3072 (H) MLPQ Package 20-Pin D D/2 D2 EXPOSED PAD PIN NUMBER 1 PIN 1 MARK AREA (See Note1) E/2 E2 E R L e TOP VIEW B BOTTOM VIEW A A3 SIDE VIEW A1 SYMBOL DESIG A A1 A3 B D D2 E E2 e L R Note 1: Details of pin #1 are optional, but must be located within the zone indicated. The identifier may be molded, or marked features. 20-PIN 4x4 MIN 0.80 0.00 0.18 2.00 2.00 0.45 0.09 NOM 0.90 0.02 0.20 REF 0.23 4.00 BSC 2.15 4.00 BSC 2.15 0.50 BSC 0.55 --- MAX 1.00 0.05 0.30 2.25 2.25 0.65 --- NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. Rev. 1.0 3/25/04 www.irf.com 23 IRU3072 PACKAGE SHIPMENT METHOD PKG DESIG H PACKAGE DESCRIPTION MLPQ 4x4 PIN COUNT 20 PARTS PER TUBE TBD PARTS PER REEL TBD T&R Orientation Fig A Feed Direction Figure A This product has been designed and qualified for the industrial market. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 24 www.irf.com Rev. 1.0 3/25/04