Application Note 1768 ISL70417SEHEVAL1Z Evaluation Board User’s Guide Introduction Power Supply Connections The ISL70417SEHEVAL1Z evaluation platform is designed to evaluate the ISL70417SEH. The ISL70417SEH contains four very high precision amplifiers featuring the perfect combination of low noise vs power consumption vs radiation hardness, providing highly reliable performance in harsh radiation environments. Its excellent noise characteristics coupled with an unique array of dynamic specifications make this amplifier well-suited for a variety of satellite system applications. Manufactured in Intersil’s PR40, silicon on insulator, BiCMOS process makes this device immune to Single Event Latch-up. J3 V- C2 R44 R1 C26 1µF 0 0 1µF D2 R37 0 V+ V- AND V+ IC SUPPLY PINS D1 J1 J4 GND J2 R48 0 V- V+ C1 0.01µF C4 0.1µF Reference Documents VREF C5 0.01µF C3 0.1µF • ISL70417SEH Data Sheet; FN7962 • ISL70417SEH SMD 5962-12228 FIGURE 1. POWER SUPPLY CIRCUIT • ISL70417SEH Radiation Test Report Figure 1 demonstrates the power supply connections, decoupling and protection circuitry. External power connections are made through the V+, V-, VREF, and GND banana jack connections on the evaluation board. De-coupling capacitors C2 and C26 provide low-frequency power-supply filtering, while additional capacitors, C1, C3, C4 and C5 which are connected close to the part, filter out high frequency noise and are connected to their respective supplies through R37 and R48 resistors. These resistors are 0Ω but can be changed by the user to provide additional power supply filtering, or to reduce the supply voltage rate-of-rise time. Anti-reverse diodes D1 and D2 protect the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. The VREF pin can be connected to ground to establish a ground referenced input for split supply operation. Evaluation Board Key Features • Dual Supply Operation: ±4.5V to ±20V • Singled-Ended or Differential Input Operation with Gain (G = 10V/V) • External VREF Input • Banana Jack Connectors for Power Supply and VREF Inputs • BNC Connectors for Op Amp Input and Output Terminals • Convenient PCB Pads for Op Amp Input/Output Impedance Loading R39, R47, R49, R50 R14, R16, R18, R40 IN- 10kΩ R5, R7, R9, R35 IN+ IN+ IN-A IN-B IN-C IN-D 2 6 9 13 IN+A IN+B IN+C IN+D 3 5 10 12 10kΩ 100kΩ 4 - V+ 0Ω ISL70417SEH + 11 V- OUT_A OUT_B OUT_C OUT_D R32 100kΩ VCM OUT 1 R51- R54 7 8 14 R67- R70 OPEN VREF VREF GND R33 OPEN FIGURE 2. BASIC DIFFERENTIAL AMPLIFIER CONFIGURATION July 2, 2012 AN1768.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1768 100k DNP 10k R20 0 FROM OUT_A TO IN-A R15 10k C7 0 TO IN+A R21 R5 DNP IN+A OPEN FIGURE 3. INPUT STAGE 0 J13 OUT A R67 0 DNP R63 DNP R51 OPEN DNP R59 OPEN A voltage divider can be added to establish a power supply-tracking common mode reference using the VREF input. The inverting and non-inverting inputs have additional resistor and capacitor placements for adding input attenuation or feedback capacitors (Figure 3). C14 OUT_A R55 User-selectable Options Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the VREF input, outputs and the amplifier feedback loops. R6 R11 R2 For single-ended input with an inverting gain G = -10V/V, the IN+ input is grounded and the signal is supplied to the IN- input. VREF must be connected to a reference voltage between the V+ and Vsupply rails. For non-inverting operation with G = 11V/V, the negative input (IN-) is grounded and the signal is supplied to the positive input (IN+). The non-inverting gain is strongly dependent on any resistance from IN- to GND. For good gain accuracy, a 0Ω resistor should be installed on the empty R11 pad. IN-A C23 OPEN R39 DNP (EQ. 1) V OUT = ( V IN+ – V IN- ) • ( R F ⁄ R IN ) + V REF C6 OPEN R14 C15 A simplified schematic of the evaluation board is shown in Figure 2. The input stage with the components supplied is shown in Figure 3. The circuit implements a Hi-Z differential input with unbalanced common mode impedance. The differential amplifier gain is expressed in Equation 1: NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. DNP Amplifier Configuration FIGURE 4. OUTPUT STAGE The outputs (Figure 4) also have additional resistor and capacitor placements for filtering and loading. TABLE 1. ISL70417SEHEVAL1Z COMPONENTS PARTS LIST DEVICE # DESCRIPTION COMMENTS C1, C5 CAP, SMD, 0805, 0.01µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C2, C26 CAP, SMD, 1210, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C3, C4 CAP, SMD, 0805, 0.1µF, 25V, 10%, X7R, ROHS Power Supply Decoupling C6-C25 CAP, SMD, 0603, OPEN-PLACE HOLDER, ROHS User selectable capacitors - not populated D1, D2 40V SCHOTTKY BARRIER DIODE Reverse Power Protection J1-J4 Johnson Components Standard Type Banana Jack, 108-0740-001 Power Supply and Reference Voltage Connector J5-J16 AMPHENOL BNC Connector, 31-5329-52RFX Connections for Input and Output RESISTOR, SMD, 0603, 100kΩ, 1%, ROHS VREF Resistor Divider R5, R7, R9, R14, R16, R18, R35, R40 RESISTOR, SMD, 0603, 10kΩ, 1%, 1/16W, ROHS Gain Setting Resistor R39, R47, R49, R50 RESISTOR, SMD, 0603, 100kΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor R2, R3, R4, R11, R12, R13, R20, R21, R22, R23, R25, R26, R28, R30, R31, R33, R34, R38, R42, R43, R46, R55, R56, R57, R58, R59, R60, R61, R62, R62, R67, R68, R69, R70 RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable resistors - not populated R32 U1 ISL70417SEH, 40V RADIATION HARDENED, LOW NOISE QUAD OPERATIONAL AMPLIFIER 2 AN1768.0 July 2, 2012 Application Note 1768 ISL70417SEHEVAL1Z Top View 3 AN1768.0 July 2, 2012 Application Note 1768 ISL70417SEHEVAL1Z Top Layer 4 AN1768.0 July 2, 2012 Application Note 1768 ISL70417SEHEVAL1Z Bottom Layer Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 5 AN1768.0 July 2, 2012 DNP D C11 OPEN RINA+ 0 R19 IN+C 0 DNP 10K IN1+ RGA+ RREFA+ RINA1+ R35 J12 10K 1 C13 OPEN R45 RINA+ 2 0 R41 IN+D 0 DNP R29 R9 R43 RREFA+ R26 J10 RINA1+ R60 J15 OUT J16 OUT DNP R67 0 C25 RGA+ DNP DNP R65 0 R69 R53 R50 R54 R66 100K 0 0 R70 DNP OPEN C20 R46 OPEN R42 C12 0 DNP R36 R38 J11 DNP IN- IN-D RREFA- 10K 8 IN+C IN-C OUTC R49 100K R61 OUT 3 10 9 VM DNP OUT 2 +IN3 -IN3 IN R57 7 R40 RINA2- R31 DNP C IN1+ -IN2 RINAIN-C R34 OPEN RINA2- +IN2 6 ISL70417SEH RREFAR25 C10 0 DNP R10 R13 DNP R4 J9 11 RGA+ RINA- 10K V- R62 DNP R23 R18 IN- 5 IN+B 0 OPEN V+ OPEN C19 R17 4 DNP RINA+ C9 12 13 OPEN 0 +IN4 DNP 10K +IN1 R58 R27 3 C21 R7 2 C24 OUTD IN-D IN+D OPEN RREFA+ RINA1+ J8 DNP IN1+ IN+B IN-B OUTB 14 -IN1 OUT 4 -IN4 C18 B IN OUT 1 OPEN VP 1 OPEN R30 DNP DNP OPEN OUTA IN-A IN+A RREFAR22 C8 0 DNP R8 R12 R3 DNP J7 IN- U1 IN-B OUT DNP 0 R68 OPEN R64 0 DNP 100K R52 DNP C22 R39 DNP OPEN R47 RINA- J14 VP Application Note 1768 R16 OUT 0.01UF 100K 10K DNP DNP 0 R59 R55 C15 OPEN C14 OPEN J1 J2 0 C23 RGA+ J13 OUT C5 0.1UF R56 R21 OPEN 0 C3 VM IN+A 0 1UF CLOSE TO PART OUT 0.01UF R15 2 D1 R63 0 C17 C7 0 R51 OPEN 1 0 D2 C26 CLOSE TO PART 0.1UF C1 0 RINA+ R1 C16 10K C4 R44 V+ OPEN R24 R5 J6 IN1+ RREFA+ DNP 6 RINA1+ 1UF RREF R37 R32 A 100K DNP DNP 2 OPEN DNP DNP RINA2- R28 R33 C6 1 0 R11 R2 DNP IN- C2 RREFAR20 R6 V- IN-A R48 10K J5 REF1 RINA- R14 J3 J4 ISL70417SEHEVAL1Z Schematic Diagram AN1768.0 July 2, 2012