Application Note 1936 ISL70419SEHEV1Z Evaluation Board User Guide Introduction Power Supply Connections The ISL70419SEHEV1Z evaluation platform is designed to evaluate the ISL70419SEH. The ISL70419SEH contains four very high precision amplifiers featuring the perfect combination of low noise vs power consumption vs radiation hardness, providing highly reliable performance in harsh radiation environments. Its excellent noise characteristics coupled with a unique array of dynamic specifications make this amplifier well-suited for a variety of satellite system applications. Manufactured in Intersil’s PR40, silicon on insulator, BiCMOS process makes this device immune to Single-Event Latch-up. J3 V- C2 R44 R1 C26 1µF 0 0 1µF D2 R37 0 V+ V- AND V+ IC SUPPLY PINS D1 J1 J4 GND J2 R48 0 V- Reference Documents VREF V+ C1 0.01µF C4 0.1µF C5 0.01µF C3 0.1µF • ISL70419SEH Datasheet • ISL70419SEH SMD 5962-14226 FIGURE 1. POWER SUPPLY CIRCUIT • ISL70419SEH Radiation Test Report (available on the ISL70419SEH Product Information page) Figure 1 demonstrates the power supply connections, decoupling and protection circuitry. External power connections are made through the V+, V-, VREF, and GND banana jack connections on the evaluation board. Decoupling capacitors C2 and C26 provide low-frequency power-supply filtering, while additional capacitors, C1, C3, C4 and C5 which are connected close to the part, filter out high frequency noise and are connected to their respective supplies through R37 and R48 resistors. These resistors are 0Ω but can be changed by the user to provide additional power supply filtering, or to reduce the supply voltage rate-of-rise time. Anti-reverse diodes D1 and D2 protect the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. The VREF pin can be connected to ground to establish a ground referenced input for split supply operation. Ordering Information PART NUMBER ISL70419SEHEV1Z DESCRIPTION ISL70419SEHEV1Z Evaluation Board User Guide Evaluation Board Key Features • Dual supply operation: ±4.5V to ±20V • Singled-ended or differential input operation with gain (G = 10V/V) • External VREF input • Banana jack connectors for power supply and VREF inputs • BNC connectors for op amp input and output terminals • Convenient PCB pads for op amp input/output impedance loading R39, R47, R49, R50 IN- IN+ IN+ R14, R16, R18, R40 IN-A IN-B IN-C IN-D 2 6 9 13 10kΩ R5, R7, R9, R35 IN+A IN+B IN+C IN+D 3 5 10 12 10kΩ VREF VREF GND 4 - V+ 0Ω ISL70419SEH + 11 V- R32 100kΩ VCM 100kΩ OUT_A OUT_B OUT_C OUT_D 1 7 8 14 OUT R51- R54 R67- R70 OPEN R33 OPEN FIGURE 2. BASIC DIFFERENTIAL AMPLIFIER EVALUATION BOARD CONFIGURATION June 20, 2014 AN1936.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1936 0 10k 100k DNP OPEN R39 R20 OPEN R14 FROM OUT_A TO IN-A R15 10k 0 C7 TO IN+A DNP R5 R21 IN+A OPEN FIGURE 3. INPUT STAGE CHANNEL A J13 OUT A DNP 0 R67 0 DNP R63 OPEN DNP R59 A voltage divider can be added to establish a power supply-tracking common mode reference using the VREF input. The inverting and non-inverting inputs have additional resistor and capacitor placements for adding input attenuation or feedback capacitors (Figure 3). R51 C15 C14 OUT_A R55 User-selectable Options Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the VREF input, outputs and the amplifier feedback loops. R6 DNP R2 For single-ended input with an inverting gain G = -10V/V, the IN+ input is grounded and the signal is supplied to the IN- input. VREF must be connected to a reference voltage between the V+ and Vsupply rails. For non-inverting operation with G = 11V/V, the negative input (IN-) is grounded and the signal is supplied to the positive input (IN+). The non-inverting gain is strongly dependent on any resistance from IN- to GND. For good gain accuracy, a 0Ω resistor should be installed on the empty R11 pad. IN-A C23 R11 (EQ. 1) V OUT = V IN+ – V IN- R F R IN + V REF C6 DNP A simplified schematic of the evaluation board is shown in Figure 2. The input stage for channel A with the components supplied, is shown in Figure 3. The circuit implements a Hi-Z differential input with unbalanced common mode impedance. The differential amplifier gain is expressed in Equation 1: NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. OPEN Amplifier Configuration FIGURE 4. OUTPUT STAGE CHANNEL A The outputs (Figure 4) also have additional resistor and capacitor placements for filtering and loading. TABLE 1. ISL70419SEHEV1Z COMPONENTS PARTS LIST DEVICE # DESCRIPTION COMMENTS C1, C5 CAP, SMD, 0805, 0.01µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C2, C26 CAP, SMD, 1210, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C3, C4 CAP, SMD, 0805, 0.1µF, 25V, 10%, X7R, ROHS Power Supply Decoupling C6-C25 CAP, SMD, 0603, OPEN-PLACE HOLDER, ROHS User Selectable Capacitors - Not Populated D1, D2 40V SCHOTTKY BARRIER DIODE Reverse Power Protection J1-J4 Johnson Components Standard Type Banana Jack, 108-0740-001 Power Supply and Reference Voltage Connector J5-J16 AMPHENOL BNC Connector, 31-5329-52RFX Connections for Input and Output RESISTOR, SMD, 0603, 100kΩ, 1%, ROHS VREF Resistor Divider R5, R7, R9, R14, R16, R18, R35, R40 RESISTOR, SMD, 0603, 10kΩ, 1%, 1/16W, ROHS Gain Setting Resistor R39, R47, R49, R50 RESISTOR, SMD, 0603, 100kΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor R2, R3, R4, R11, R12, R13, R20, R21, R22, R23, R25, R26, R28, R30, R31, R33, R34, R38, R42, R43, R46, R55, R56, R57, R58, R59, R60, R61, R62, R62, R67, R68, R69, R70 RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS User Selectable Resistors - Not Populated R32 U1 Submit Document Feedback ISL70419SEHF/PROTO, 36V RADIATION HARDENED AND SET ENHANCED, LOW NOISE QUAD OPERATIONAL AMPLIFIER 2 AN1936.0 June 20, 2014 DNP DNP J15 OPEN DNP R46 DNP R70 OUTD DNP C12 0 J16 D RINA+ R19 0 OPEN IN1+ 0 IN+C DNP 10K R29 0 1 C13 R45 RINA+ R41 2 0 OPEN RGA+ RREFA+ RINA1+ R35 J12 DRAWN BY: 0 OSCAR MANSILLA RELEASED BY: IN+D DNP R9 R43 RREFA+ R26 J10 RINA1+ C11 UPDATED BY: RGA+ TIM KLEMANN DATE: ENGINEER: DATE: TITLE: OSCAR MANSILLA 12/19/2013 DATE: 02/03/2014 TESTER MASK# FILENAME: AN1936.0 June 20, 2014 7 6 5 4 3 2 DATE: ISL70419SEH EVALUATION BOAR SCHEMATIC HRDWR ID RE ISL70419SEHEV1Z \\ISL70419SEH/ISL70419SEHEV1Z 8 OUTC DNP R69 R61 DNP 0 R62 R36 RINA2- R66 0 DNP J11 R54 R58 IN- R50 100K C21 R31 DNP DNP IN-D RREFA- R42 OPEN R40 10K R38 C10 0 R57 0 C19 R65 0 OPEN R53 C20 RINA- DNP DNP R10 R13 DNP R49 100K C25 C IN1+ 8 OUT_C VM OPEN RINA- 10K RINA2- 9 -IN_C OUT_B IN+C IN-C OUTC IN RGA+ IN-C RREFA- DNP J9 R4 IN- 10 +IN_C -IN_B 7 11 OPEN ISL70419SEHF/PROTO DNP R18 +IN_B 6 12 V- C24 OUTD IN-D IN+D IN+B R23 0 OPEN -IN_D +IN_D 13 OPEN R17 -IN_A +IN_A V+ 5 0 RINA+ C9 R34 10K R27 3 14 OUT_D OPEN R7 R25 IN1+ RREFA+ RINA1+ J8 2 4 IN IN+B IN-B OUTB B OUT_A C18 VP 1 OPEN DNP DNP OPEN R22 R12 DNP 0 OUTA IN-A IN+A R30 C8 RINA2- DNP R3 IN- IN-B RREFA- OUTB SHEET 1 1 OF Application Note 1936 R8 J7 U1 RINA- R16 R67 R60 R47 J14 DNP OPEN R68 0 100K 10K DNP DNP R59 R55 C15 C14 OPEN R64 0 DNP 100K RGA+ R52 C22 DNP R39 OUTA VP 0.01UF OPEN J13 OUT DNP C23 0.1UF R56 C5 OPEN J1 C3 VM 0.01UF 0 0 R37 CLOSE TO PART OUT IN+A DNP 0 OPEN 1UF D1 CLOSE TO PART 0.1UF C1 0 C17 R15 2 0 R63 0 OPEN RINA+ C7 1 0 D2 R51 C26 C16 0 R1 V+ OPEN 10K DNP R24 R21 3 IN1+ RREFA+ R5 R33 RINA1+ R44 R48 1UF RREF C4 A J6 J2 J3 J4 R32 DNP DNP R20 DNP RINA2- R28 2 OPEN C2 100K C6 1 0 R11 R2 IN- V- IN-A RREFA- 10K R6 J5 REF1 RINA- R14 DNP Submit Document Feedback ISL70419SEHEV1Z Schematic Diagram Application Note 1936 ISL70419SEHEV1Z Board Layout FIGURE 5. SILKSCREEN TOP Submit Document Feedback 4 AN1936.0 June 20, 2014 Application Note 1936 ISL70419SEHEV1Z Board Layout (Continued) FIGURE 6. TOP LAYER Submit Document Feedback 5 AN1936.0 June 20, 2014 Application Note 1936 ISL70419SEHEV1Z Board Layout (Continued) FIGURE 7. BOTTOM LAYER Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 6 AN1936.0 June 20, 2014 Application Note 1936 Typical Performance Curves 70 GAIN (dB) 30 20 -1 AV = 10 -3 RL = 1k -4 VS = ±20V RL = 499 CL = 4pF -6 AV = +1 AV = 1 -10 10 RL = 4.99k -2 -5 Rg = 10k, Rf = 100k 10 0 0 VS = ±20V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 RL = 10k 1 Rg = 1k, Rf = 100k 50 40 2 Rg = 100, Rf = 100k AV = 1000 GAIN (dB) 60 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. 10k 1k 100 100k 1M -8 10 10M 100 FREQUENCY (Hz) FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 8 2 VS = ±2.5V RL = 10k CL = 0.01µF CL = 47pF 0 -2 -4 CL = 4pF CL = 470pF CL = 1000pF 10k 1k 100 100k 1M VS = ±15V -2 -3 VS = ±20V -4 -5 CL = 4pF RL = 10k -6 AV = +1 -7 V OUT = 50mVP-P CL = 100pF CL = 270pF -8 10 -8 10M 10 100 FREQUENCY (Hz) 10k 1k 100k FREQUENCY (Hz) 1M 10M FIGURE 11. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 100 60 50 INPUT NOISE VOLTAGE (nV/√Hz) SMALL SIGNAL TRANSIENT RESPONSE (mV) FIGURE 10. GAIN vs FREQUENCY vs CL 40 VS =±5, ±15V 30 RL = 10k CL = 4pF AV = +1 VOUT = 50mVP-P 20 10 0 -10 10M -1 4 -6 1M VS = ±5V 0 AV = +1 VOUT = 50mVP-P 2 10k 100k FREQUENCY (Hz) VS = ±2.25V 1 GAIN (dB) GAIN (dB) 6 1k FIGURE 9. GAIN vs FREQUENCY vs RL 12 10 RL = 100 -7 VOUT = 50mVP-P Rg = OPEN, Rf = 0 VS = ±18.2V AV = 1 10 1 0 5 10 15 20 25 TIME (µs) 30 35 40 FIGURE 12. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V Submit Document Feedback 7 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 13. INPUT NOISE VOLTAGE SPECTRAL DENSITY AN1936.0 June 20, 2014