[ /Title (CD74 HC390 , CD74 HCT39 0) /Subject (High Speed CMOS Data sheet acquired from Harris Semiconductor SCHS185 CD74HC390, CD74HCT390 September 1997 High Speed CMOS Logic Dual Decade Ripple Counter Features Description • Two BCD Decade or Bi-Quinary Counters The Harris CD74HC390 and CD574HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). • One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100 • Two Master Reset Inputs to Clear Each Decade Counter Individually • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low. • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER Pinout CD74HC390, CD74HCT390 TOP VIEW 1CP0 1 16 VCC 1MR 2 15 2CP0 1Q0 3 14 2MR 1CP1 4 13 2Q0 1Q1 5 12 2CP1 1Q2 6 11 2Q1 1Q3 7 10 2Q2 GND 8 9 2Q3 TEMP. RANGE (oC) CD74HC390E -55 to 125 16 Ld PDIP E16.3 CD74HCT390E -55 to 125 16 Ld PDIP E16.3 CD74HC390M -55 to 125 16 Ld SOIC M16.15 CD74HCT390M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 PKG. NO. PACKAGE 1 File Number 1838.2 CD74HC390, CD74HCT390 Functional Diagram 1 (15) 3 (13) nCP0 2 (14) nMR nQ0 ÷2 COUNTER 5 (11) 4 (12) nCP1 ÷5 6 (10) COUNTER 7 (9) nQ1 nQ2 nQ3 GND = 8 VCC = 16 TRUTH TABLE INPUTS CP MR ACTION ↑ L No Change ↓ L Count X H All Qs Low NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low. B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390 BCD COUNT SEQUENCE FOR 1/2 THE 390 OUTPUTS OUTPUTS COUNT Q0 Q1 Q2 Q3 COUNT Q0 Q1 Q2 Q3 0 L L L L 0 L L L L 1 H L L L 1 L H L L 2 L H L L 2 L L H L 3 H H L L 3 L H H L 4 L L H L 4 L L L H 5 H L H L 5 H L L L 6 L H H L 6 H H H L 7 H H H L 7 H L H L 8 L L L H 8 H H H L 9 H L L H 9 H L L H NOTE: Output nQ3 connected to nCP0 with counter input on nCP1. NOTE: Output nQ0 connected to nCP1 with counter input on nCP0. 2 CD74HC390, CD74HCT390 Logic Diagram 4(12) nCP1 Q 1(15) nCP0 2(14) nMR Q Φ Q Φ R Q Φ R Φ R R VCC = 16 GND = 8 3(13) nQ0 5(11) nQ1 3 6(10) nQ2 7(9) nQ3 CD74HC390, CD74HCT390 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC390, CD74HCT390 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nCP0 0.45 nCP1, MR 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC CHARACTERISTIC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS fMAX 2 6 - - 5 - 4 - MHz 4.5 30 - - 24 - 20 - MHz 6 35 - - 28 - 24 - MHz 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns HC TYPES Maximum Clock Frequency Clock Pulse Width, nCP0, nCP1 Reset Removal Time tW tREM 5 CD74HC390, CD74HCT390 Prerequisite for Switching Specifications (Continued) 25oC CHARACTERISTIC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns fMAX 4.5 27 - - 22 - 18 - MHz tW 4.5 19 - - 24 - 29 - ns tREM 4.5 15 - - 19 - 22 - ns tW 4.5 13 - - 16 - 20 - ns Reset Pulse Width HCT TYPES Maximum Clock Frequency Clock Pulse Width, nCP0, nCP1 Reset Removal Time Reset Pulse Width Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay (Figure 1) nCP0 to nQ0 nCP1 to nQ1 nCP1 to nQ2 nCP1 to nQ3 nCP0 to nQ3 (nQ0 connected to nCP1) MR to Qn Output Transition Time (Figure 1) TEST SYMBOL CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns tPLH, tPHL CL = 50pF 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns 6 - - 31 - 39 - 48 ns tPLH, tPHL CL = 50pF 2 - - 245 - 305 - 370 ns 4.5 - - 49 - 61 - 74 ns 6 - - 42 - 52 - 63 ns 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 5 - 15 - - - - - ns 6 - - 31 - 38 - 46 ns tPLH, tPHL tPLH, tPHL tPLH, tPHL CL = 50pF CL = 50pF 2 - - 365 - 455 - 550 ns 4.5 - - 73 - 91 - 110 ns 6 - - 62 - 77 - 94 ns 2 - - 190 - 240 - 285 ns 4.5 - - 38 - 48 - 57 ns CL =15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 32 - 41 - 48 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns tPLH, tPHL CL = 50pF CL = 50pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 28 - - - - - pF 6 CD74HC390, CD74HCT390 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS PARAMETER HCT TYPES Propagation Delay (Figure 1) 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 17 - - - - - ns nCP1 to nQ1 tPLH, tPHL CL = 50pF 4.5 - - 43 - 51 - 65 ns nCP1 to nQ2 tPLH, tPHL CL = 50pF 4.5 - - 55 - 69 - 83 ns nCP1 to nQ3 tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns nCP0 to nQ0 nCP0 to nQ2 (nQ0 connected to nCP1) tPLH, tPHL CL = 50pF 4.5 - - 84 - 105 - 126 ns MR to Qn tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns 4.5 - - 15 - 19 - 22 ns tTLH, tTHL CL = 50pF Output Transition Input Capacitance CIN CL =15pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 32 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per multiplexer. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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