LTC7860 - High Efficiency Switching Surge Stopper

LTC7860
High Efficiency Switching
Surge Stopper
Features
Description
High Efficiency VOUT Clamp Stops High Voltage
Input Surges
nn SWITCH-ON Mode 100% Duty Cycle for Normal Operation
nn PROTECTIVE PWM Mode for Transients and Faults
nn V Pin to SGND Range: 3.5V to 60V
IN
nn External Input Voltage is Extendable to 200V+
nn Adjustable Output Voltage Clamp
nn Adjustable Output Overcurrent Protection
nn Power Inductor Improves Input EMI in Normal Operation
nn Programmable Fault Timer
nn Adjustable Soft-Start for Input Inrush Current Limiting
nn 4.5% Retry Duty Cycle During Faults
nn Adjustable Switching Frequency: 50kHz to 850kHz
nn Optional Reverse Input Voltage Protection
nn Available in Thermally Enhanced 12-lead MSOP Package
The LTC®7860 high efficiency surge stopper protects loads
from high voltage transients. High efficiency permits
higher currents and smaller solution sizes. During an
input overvoltage event, such as a load dump in vehicles,
the LTC7860 controls the gate of an external MOSFET to
act as a switching DC/DC regulator (PROTECTIVE PWM
mode). This operation regulates the output voltage to a
safe level, allowing the loads to operate through the input
over-voltage event. During normal operation (SWITCHON mode), the LTC7860 turns on the external MOSFET
continuously, passing the input voltage through to the
output. An internal comparator limits the voltage across
the current sense resistor and regulates the maximum
output current to protect against overcurrent faults.
nn
Applications
Industrial and Automotive Power
Telecom Power
nn Vehicle Power Including ISO7637
nn Military Power Including MIL1275
nn
nn
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5731694.
An adjustable timer limits the time that the LTC7860 can
spend in overvoltage or overcurrent regulation. When the
timer expires, the external MOSFET is turned off until the
LTC7860 restarts after a cool down period. By strictly
limiting the time in PROTECTIVE PWM Mode when the
power loss is high, the components and thermal design
can be optimized for normal operation and safely operate through high voltage input surges and/or overcurrent
faults. An additional PMOS can be added for reverse
battery protection.
Typical Application
VIN
60V MAX
12V NOM
3.5V MIN
VOUT
18V MAX
12V NOM
3.5V MIN
5A
6.8µH
12mΩ
10µF
PROTECTIVE PWM: VOUT Clamped
to 18V During a VIN Surge
GATE
VFBN
SENSE
VIN
60V INPUT SURGE
CAP
10µF
LTC7860
TMR
22µF
0.1µF
10k
680pF
VIN
10V/DIV
VFB
FREQ
0.47µF
1M
RUN
SGND PGND
VOUT
10V/DIV
18V ADJUSTABLE CLAMP
VTMR
1V/DIV
48.7k
SS
ITH
CTMR = 22µF
0.1µF
100ms/DIV
7860 TA01b
7860 TA01a
7860f
For more information www.linear.com/LTC7860
1
LTC7860
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
Input Supply Voltage (VIN).......................... –0.3V to 65V
VIN-VSENSE Voltage....................................... –0.3V to 6V
VIN-VCAP Voltage......................................... –0.3V to 10V
RUN Voltage............................................... –0.3V to 65V
VFBN, TMR Voltages...................................... –0.3V to 6V
SS, ITH, FREQ, VFB Voltages......................... –0.3V to 5V
Operating Junction Temperature Range
(Notes 3, 4)......................................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP Package.................................................. 300°C
TOP VIEW
TMR
FREQ
SGND
SS
VFB
ITH
1
2
3
4
5
6
13
PGND
12
11
10
9
8
7
GATE
VIN
SENSE
CAP
RUN
VFBN
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7860EMSE#PBF
LTC7860EMSE#TRPBF
7860
12-Lead Plastic MSOP
–40°C to 125°C
LTC7860IMSE#PBF
LTC7860IMSE#TRPBF
7860
12-Lead Plastic MSOP
–40°C to 125°C
LTC7860HMSE#PBF
LTC7860HMSE#TRPBF
7860
12-Lead Plastic MSOP
–40°C to 150°C
LTC7860MPMSE#PBF
LTC7860MPMSE#TRPBF
7860
12-Lead Plastic MSOP
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
7860f
For more information www.linear.com/LTC7860
LTC7860
Electrical
Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
VIN
Input Voltage Operating Range
3.5
VUVLO
Undervoltage Lockout
(VIN-VCAP) Ramping Up Threshold
(VIN-VCAP) Ramping Down Threshold
Hysteresis
IQ
Input DC Supply Current
FREQ = 0V, VFB = 0.83V (No Load)
Shutdown Supply Current
RUN = 0V
l
l
3.25
3.00
60
V
3.50
3.25
0.25
3.8
3.50
V
V
V
0.77
1.2
mA
7
12
µA
0.800
0.809
V
0.005
%/V
Output Sensing
VREG
Regulated Feedback Voltage VREG = (VFB – VFBN) VITH = 1.2V (Note 4)
Feedback Voltage Line Regulation
VIN = 3.8V to 60V (Note 4)
Feedback Voltage Load Regulation
VITH = 0.6V to 1.8V (Note 4)
VITH = 1.2V, ∆IITH = ±5µA (Note 4)
l
0.791
–0.005
–0.1
–0.015
0.1
1.8
%
gm(EA)
Error Amplifier Transconductance
IFB
Feedback Input Bias Current
–50
–10
50
mS
nA
IFBN
Feedback Negative Input Bias Current
–50
–10
50
nA
85
95
103
mV
0.1
2
µA
1.26
1.32
V
Current Sensing
VILIM
Current Limit Threshold (VIN-VSENSE)
VFB = 0.77V
ISENSE
SENSE Pin Input Current
VSENSE = VIN
l
Start-Up and Shutdown
VRUN
RUN Pin Enable Threshold
VRUN Rising
l
1.22
RUN Pin Hysteresis
Soft-Start Pin Charging Current
VSS = 0V
ITPU
TMR Pull-Up Current
TMR = 1.1V, VFB = 0.83V
ITPDR
TMR Pull-Down Current Restart
TMR = 1.1V, VFB = 0.77V
ITPDC
TMR Pull-Down Current Cool Down
TMR = 1.1V, VFB = 0.77V
VGTH
TMR Gate Off Threshold
VFB = 0.77V
VFB = 0.77V
ISS
150
mV
10
µA
Fault Timer
l
–35
–30
–25
40
µA
µA
1.0
1.3
1.6
µA
l
1.25
1.29
1.35
V
l
37
VRTH
TMR Restart Threshold
TSETI(1µF)
TMR Set Time Initial for Fault Detection for 1µF
(TSETI = VGTH/ITPU)
240
TSETR(1µF)
TMR Set Time Repeat for Fault Detection for 1µF
(TSETI = (VGTH – VRTH)/ITPU)
32
ms/µF
TRSTC(1µF)
TMR Restart Cool Down Time for 1µF
(TRSTC = (VGTH – VRTH)/ITPDC)
732
ms/µF
DTYTSTR
TMR Restart Duty Cycle in a Sustained Fault
(DTYTSTR = TSETR/TRSTC)
l
3.5
44
4.5
mV
50
5.5
ms/µF
%
Switching Frequency
7860f
For more information www.linear.com/LTC7860
3
LTC7860
Electrical
Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Programmable Switching Frequency
RFREQ = 24.9kΩ
RFREQ = 64.9kΩ
RFREQ = 105kΩ
375
105
440
810
505
kHz
kHz
kHz
Low Switching Frequency
FREQ = 0V
320
350
380
kHz
485
535
585
kHz
High Switching Frequency
FREQ = Open
fFOLD
Foldback Frequency as Percentage of
Programmable Frequency
VFB = 0V, FREQ = 0V
tON(MIN)
Minimum On-Time
18
%
220
ns
Gate Driver
VCAP
Gate Bias LDO Output Voltage (VIN-VCAP)
IGATE = 0mA
RUP
Gate Pull-Up Resistance
Gate High
2
Ω
RDN
Gate Pull-Down Resistance
Gate Low
0.9
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance provided in the Pin
Configuration section for the corresponding package.
Note 3: The LTC7860 is tested under pulsed load conditions such that TJ
≈ TA. The LTC7860E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature range. The LTC7860E
specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
4
l
7.6
8.0
8.5
V
statistical process controls. The LTC7860I is guaranteed to meet
performance specifications over the –40°C to 125°C operating junction
temperature range, the LTC7860H is guaranteed over the –40°C to 150°C
operating junction temperature range, and the LTC7860MP is guaranteed
and tested over the full –55°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes; operating
lifetime is derated for junction temperatures greater than 125°C. The
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 4: The LTC7860 is tested in a feedback loop that adjust VREG
or (VFB – VFBN) to achieve a specified error amplifier output voltage
(on ITH pin).
7860f
For more information www.linear.com/LTC7860
LTC7860
Typical Performance Characteristics
Frequency Over Input Voltage
600
FREQ = OPEN
550
500
f (kHz)
500
f (kHz)
120
FREQUENCY FOLDBACK (%)
FREQ = OPEN
550
450
450
400
400
FREQ = 0V
350
0
20
10
30
VIN (V)
FREQ = 0V
350
40
50
300
–75
60
–25
25
75
125
TEMPERATURE (°C)
GATE Bias LDO (VIN - VCAP) Load
Regulation
0.1
–0.1
–0.2
–2.0
–0.3
–2.5
–0.4
–3.0
–3.5
20
0
200
400
VFB (mV)
600
800
Current Sense Voltage Over ITH
Voltage
90
80
70
60
50
40
30
20
10
0
0
5
10
IGATE (mA)
15
–0.5
20
0
5
10
IGATE (mA)
15
7860 G22
SS PULL-UP CURRENT (µA)
98
96
94
92
25
75
125
TEMPERATURE (°C)
175
0
0.4
0.8
1.2
ITH VOLTAGE (V)
1.6
TMR Pull-UP Current Over
Temperature
–25.0
VSS = 0V
12
10
8
6
–75
–25
2
7860 G24
TMR PULL–UP CURRENT (µA)
14
–25
20
SS Pin Pull-Up Current Over
Temperature
100
90
–75
–10
7860 G23
Current Sense Voltage Over
Temperature
CURRENT LIMIT SENSE VOLTAGE (mV)
40
100
CURRENT SENSE VOLTAGE (mV)
0.0
–1.5
60
7860 G21
VIN = 5V
(VIN - VCAP) DROPOUT (V)
(VIN - VCAP) REGULATION (%)
0.0
–1.0
80
0
175
GATE Bias LDO (VIN - VCAP)
Dropout Behavior
–0.5
100
7860 G20
7860 G19
0.5
Frequency Foldback % Over
Feedback Voltage
Frequency Over Temperature
600
300
TA = 25°C, unless otherwise noted.
25
75
125
TEMPERATURE (°C)
175
–27.5
–30.0
–32.5
–35.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
7860 G27
7860 G25
7860 G26
7860f
For more information www.linear.com/LTC7860
5
LTC7860
Pin Functions
TMR (Pin 1): Programmable Fault Timer. The TMR function
monitors the time spent in PROTECTIVE PWM mode and
provides fault control. During a fault, a 30μA (ITPU) current
pulls up the TMR pin. If the fault clears before the 1.29V
TMR Gate Off Threshold (VGTH) is reached, a 40μA current
(ITPDR) resets the TMR pin to ground. The gate turns off
and shuts down when VGTH is reached. In shutdown, a
1.3μA (ITPDC) current pulls TMR down to a 240mV TMR
Restart Threshold (VRTH) allowing a cool down period
before restart.
FREQ (Pin 2): Switching Frequency Setpoint Input. The
switching frequency is programmed by an external setpoint resistor RFREQ connected between the FREQ pin and
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
SGND (Pin 3): Ground Reference for Small-Signal Analog
Component (Signal Ground). Signal ground should be
used as the common ground for all small-signal analog
inputs and compensation components. Connect the signal
ground to the power ground (ground reference for power
components) only at one point using a single PCB trace.
SS (Pin 4): Soft-Start and External Tracking Input. The
LTC7860 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage.
VFB (Pin 5): Output Feedback Sense. A resistor divider
from the regulated output point to this pin sets the output
voltage. The LTC7860 will nominally regulate VFB to the
internal reference value of 0.8V. If VFB is less than 0.4V,
the switching frequency will linearly decrease and fold
back to about one-fifth of the internal oscillator frequency
to reduce the minimum duty cycle.
6
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
point. The voltage ranges from 0V to 2.9V, with 0.8V corresponding to zero sense voltage (zero current).
VFBN (Pin 7): Feedback Input for an Inverting Feedback
Option. Connect VFBN to the center of a resistor divider
between the output and VFB. The VFBN threshold is 0V.
To defeat the inverting amplifier and use Non-Inverting
feedback option, tie VFBN > 2V. VFBN can be tied to FREQ
if FREQ is floated and a 535kHz fixed operating frequency
is selected. The minimum suggested value of the feedback
resistor between VFB and VFBN for Inverting Feedback
Option is 10K.
RUN (Pin 8): Run Control Input. A RUN voltage above
the 1.26V threshold enables normal operation, while a
voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.47µF or 10X the effective
CMILLER of the P-channel power MOSFET, is required
from VIN to this pin to serve as a bypass capacitor for the
internal regulator. To ensure stable low noise operation, the
bypass capacitor should be placed adjacent to the VIN and
CAP pins and connected using the same PCB metal layer.
SENSE (Pin 10): Current Sense Input. A sense resistor,
RSENSE, from the VIN pin to the SENSE pin sets the maximum current limit. The peak inductor current limit is equal
to 95mV/RSENSE. For accuracy, it is important that the VIN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
VIN (Pin 11): Chip Power Supply. A minimum bypass
capacitor of 0.1µF is required from the VIN pin to power
ground. For best performance use a low ESR ceramic
capacitor placed near the VIN pin.
7860f
For more information www.linear.com/LTC7860
LTC7860
Pin Functions
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (VIN-VCAP)
is regulated to 8V when VIN is greater than 8V. The gate
driver is disabled when (VIN-VCAP) is less than 3.5V (typical), 3.8V maximum in start-up and 3.25V (typical) 3.5V
maximum in normal operation.
PGND (Exposed Pad Pin 13): Ground Reference for Power
Components (Power Ground). The PGND exposed pad must
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.
FUNCTIONAL Diagram
VIN
UVLO
+
–
0.4µA
RUN
1.26V
CIN
VIN
3.25V
RSENSE
SENSE
RUN
+
–
–
LOGIC
CONTROL
DRV
MP
HIGH CURRENT PATH
Q
S R R
SGND
GATE
VOUT
COUT
CCAP
IN
LDO
OUT
VIN – 8V
PLL
SYSTEM
FREQ
–
20µA VCO
RFREQ
ICMP
CAP
+
+
10µA
+
+
–
GATE OFF
VGTH
1.29V
TMR
CTMR
ITPDC
1.3µA
ITPDR
40µA
VRTH
0.24V
+
–
–
+
EA
(Gm = 1.8mS)
FAULT
TIMER
LOGIC
0.8V
EN
CSS
0.5µA
VFBN
RZ1
RFB2
VFB
COOL DOWN
NORMAL OPERATION
VIN
Z1
+
ITPU
30µA
SS
–
SLOPE
COMPENSATION
RFB1
PGND
ITH
7860 FD
RITH
CITH1
7860f
For more information www.linear.com/LTC7860
7
LTC7860
Operation
High Efficiency Switching Surge Stopper Overview
The LTC7860 is designed for use as a high efficiency
switching surge stopper and/or input inrush current limiter. Normal operation for the LTC7860 is in "dropout" or
SWITCH-ON mode. The LTC7860 switches during start-up
or in response to either an input over-voltage or output
short-circuit event (PROTECTIVE PWM mode). If the time
spent switching exceeds the time programmed by the
timer the LTC7860 will shut down.
A high efficiency surge stopper or input inrush current
limiter can be thought of as a pre-regulator. As an example
of a MIL1275 application, the input voltage connects to
a 28V vehicle power bus. The 28V power bus can go as
high as 100V with a surge profile lasting up to 500mS. The
output must be pre-regulated or limited to 34V maximum
and can go as low as 12V during engine cranking. The
LTC7860 limits the voltage seen at the output and protects any load connected to the 28V bus from potentially
destructive voltage levels. The LTC7860 timer limits
the time spent switching where excessive and thermally
destructive power loss can occur.
For both a linear surge stopper such as the LTC4363 and
the LTC7860 switching surge stopper, the power loss
increases significantly once regulation begins. In a linear
surge stopper, the power loss is the power loss of the
regulating MOSFET. In a high efficiency surge stopper or
switching surge stopper, internal power loss is determined
by conversion efficiency. A switching surge stopper will
allow higher output current and power levels than a comparable linear solution by virtue of reduced power loss. In
a switching surge stopper the internal surge power loss
can increase by as much as 10 times the normal power
loss. If the time spent in PWM mode regulation is limited,
the operating power can be pushed beyond what can be
achieved in steady state operation. This is precisely the
same concept as utilized in linear surge stoppers but
extended to a switching supply. The use of the timer
improves reliability and reduces component size when
compared to a continuous solution. By limiting the time in
8
regulation when the power loss is high, the components
and thermal design can be optimized for normal operation
and safely operate through high voltage input surges and/
or overcurrent faults.
In a switching surge stopper the insertion loss in normal
operation or SWITCH-ON mode is the primary consideration and not efficiency in switching. The LTC7860 circuit
must operate without damage during a surge or fault
event. The Switching Surge Stopper is effectively a wire
in normal operation where the insertion loss is determined
by multiplying the input current by the effective resistance.
LTC7860 Main Control Loop
The LTC7860 uses a peak current-mode control
architecture to regulate the output in a step-down DC/
DC switching regulator. The VFB input is compared to an
internal reference by a transconductance error amplifier
(EA). The internal reference can be either a fixed 0.8V
reference VREF or the voltage input on the SS pin. In
normal operation VFB regulates to the internal 0.8V
reference voltage. In soft-start, when the SS pin voltage
is less than the internal 0.8V reference voltage, VFB will
regulate to the SS pin voltage. The error amplifier output
connects to the ITH (current [I] threshold [TH]) pin. The
voltage level on the ITH pin is then summed with a slope
compensation ramp to create the peak inductor current
set point.
The peak inductor current is measured through a sense
resistor, RSENSE, placed across the VIN and SENSE pins.
The resultant differential voltage from VIN to SENSE is
proportional to the inductor current and is compared to
the peak inductor current setpoint. During normal operation the P-channel power MOSFET is turned on when the
clock leading edge sets the SR latch through the S input.
The P-channel MOSFET is turned off through the SR latch
R input when the differential voltage from VIN to SENSE
is greater than the peak inductor current setpoint and the
current comparator, ICMP, trips high.
7860f
For more information www.linear.com/LTC7860
LTC7860
Operation
Power CAP and VIN Undervoltage Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
VIN in order to provide efficient P-channel operation. The
power for the VCAP supply comes from an internal LDO,
which regulates the VIN-CAP differential voltage. A minimum capacitance of 0.47µF (low ESR ceramic) is required
between VIN and CAP to assure stability.
For VIN ≤ 8V, the LDO will be in dropout and the CAP voltage will be at ground, i.e., the VIN-CAP differential voltage
will equal VIN. If VIN-CAP is less than 3.25V (typical), the
LTC7860 enters a UVLO state where the GATE is prevented
from switching and most internal circuitry is shut down.
In order to exit UVLO, the VIN-CAP voltage would have to
exceed 3.5V (typical).
Shutdown and Soft-Start
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shutdown
state, the LTC7860 draws only 7µA. Releasing the RUN pin
allows a small internal pull-up current to pull the RUN pin
above 1.26V and enable the controller. The RUN pin can
be pulled up to an external supply of up to 60V or driven
directly by logic levels.
The start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the VFB pin
is regulated to the voltage on the SS pin. This allows the
SS pin to be used to program a soft-start by connecting
an external capacitor from the SS pin to signal ground.
An internal 10µA pull-up current charges this capacitor,
creating a voltage ramp on the SS pin. As the SS voltage rises from 0V to 0.8V, the output voltage VOUT rises
smoothly from zero to its final value. The SS time must
be sufficiently less than the TMR set time to avert a timer
shutdown in startup or fault recovery.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Frequency Selection
The switching frequency of the LTC7860 can be selected
using the FREQ pin. The FREQ pin can be tied to signal
ground, floated, or programmed through an external resistor. Tying FREQ pin to signal ground selects 350kHz,
while floating selects 535kHz. Placing a resistor between
FREQ pin and signal ground allows the frequency to be
programmed between 50kHz and 850kHz. Refer to the
chart in the Application section for switching frequency
versus resistor values.
Fault Protection
In the event of an output short-circuit or overcurrent condition that causes the output voltage to drop significantly
while in current limit, the LTC7860 operating frequency
will fold back. Anytime the output feedback VFB voltage is
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as VFB drops until reaching a minimum foldback
frequency of about 18% of the setpoint frequency. Frequency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions. Setting the foldback frequency as a percentage
of operating frequency assures that start-up characteristics
scale appropriately with operating frequency.
7860f
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9
LTC7860
Applications Information
The LTC7860 is a high efficiency switching surge stopper
which provides input voltage surge protection, input inrush
current limiting and output short protection. High Efficiency
Switching permits high output current capability and small
solution size. During an input overvoltage event, such as
a load dump in vehicles, the LTC7860 controls the gate of
an external MOSFET to act as a switching DC/DC regulator
(PROTECTIVE PWM mode). This operation regulates the
output voltage to a safe level, allowing the loads to operate
through the input over-voltage event.
During normal operation (SWITCH-ON mode), the LTC7860
turns on the external MOSFET continuously, passing the
input voltage through to the output. An internal comparator
limits the voltage across the current sense resistor and
regulates the maximum output current to protect against
over current faults.
Output Voltage Programming
The LTC7860 is highly flexible and offers application
options to address a variety of input and output voltage
ranges. These options are best divided into two categories.
The first category is operation at or below VIN = 60V. The
second category is operation above 60V. The LTC7860
input and output voltage operation in the second category
depends only on external components and can be reliably
extended up to 200V.
Operation for VIN of 60V and BELOW
For operation at VIN of 60V and BELOW, the output voltage
is programmed by connecting a feedback resistor divider
from the output to the VFB pin as shown in Figure 1a. The
front page application is an example of this configuration.
The output voltage in steady state operation is set by the
feedback resistors RFB2 and RFB1 according to the equation:
 R 
VOUT = 0.8V •  1+ FB1 
 RFB2 
Great care should be taken to route the VFB line away from
noise sources, such as the inductor or the GATE signal
that drives the external P MOSFET. The best practice is
to locate resistors RFB2 and RFB1 and capacitor CFF local
10
to the LTC7860 to keep the VFB trace short and without
VIAS. The planes for VOUT and GND are then routed to
the desired regulation point. Detailed layout suggestions
are discussed in the Layout sections later in the data
sheet. The feed-forward capacitor CFF is added to improve
transient response.
VOUT
LTC7860
RZ1
RFB2
CFF
VFB
VFBN
PGND SGND
RFB1
Z1
7860 F01a
Figure 1a. Switching Surge Stopper for VIN Operation of
60V and BELOW (VFBN > 2V)
Operation for VIN ABOVE 60V
For operation at VIN = 60V, a floating ground must be created by a bootstrapped shunt regulator such as a Zener or
similar element. To establish shunt DC bias to the LTC7860,
connect the floating ground to the LTC7860 PGND and
SGND pins. The Zener voltage or Shunt DC bias limit is
typically 12V to minimize internal power dissipation but can
be extended up to 60V. The VIN Operational Input voltage
ranges for these applications are limited only by external
components and can reliably extend to 200V and beyond.
There are two feedback options for operation above 60V
which are Inverting and Non-Inverting Feedback.
The Inverting Feedback Option uses fewer components with
slightly reduced accuracy (Figure 1b). The Non- Inverting
Feedback Option uses additional components but with better accuracy (Figure 1c). It has the additional advantage
of reducing VIN quiescent current in normal operation.
Inverting Feedback Option
In the Inverting Feedback Option for VIN ABOVE 60V, the
voltage is programmed by connecting a feedback resistor
divider from the output to ground as shown in Figure 1b.
VOUT is divided down and the voltage presented to the gate
of QFB. The gate voltage is then translated into a signal
current by QFB and RFB3 and sent to the LTC7860 Floating
Ground Inverting Feedback Pin VFBN. The resistor RFB4
7860f
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LTC7860
Applications Information
VIN
VIN
VIN
LTC7860
VFB
Z1
RFB4
CFB4
VOUT
PGND SGND
RFB2
QFB
CFF
QFBM1
VOUT
RFB2
RFB4
CFF
QFB
7860 F01c
PGND SGND
RFB3
RFB1
FLOATING GND
RFB1
Figure 1b. Switching Surge Stopper for VIN Operation
ABOVE 60V with Inverting Feedback
translates the signal current proportional to VOUT into a
feedback voltage between VFB and VFBN. The voltage at
VFBN is the input of an inverting amplifier and is nominally
equal to the Floating Ground. The output voltage in steady
state operation is set by the feedback resistors according
to the equation:

  R 
R
VOUT =  0.8V • FB3 + VGSQFB  •  1+ FB2 
RFB4

  RFB1 
The shunt DC bias or Zener and floating ground permits
the drain current of QFB to be translated to a differential
feedback voltage VFB – VFBN independent of the value
of VIN. RFB4 should be greater than 10k to avoid VFB pin
output current limitations.
The integrator capacitor, CFB4, should be sized to ensure
the negative sense amplifier gain rolls off and limits high
frequency gain peaking in the DC/DC control loop. The
integrator capacitor pole can be safely set to be two times
the switching frequency without affecting the DC/DC phase
margin according to the following equation. It is highly
recommended that CFB4 be used in most applications.
QFBM2
7860 F01b
RFB3
CFB4 =
Z2
RFBM1
VIN
LTC7860
VFBN
VFB
Z1
VFBN
FLOATING GND
RFBM2
RZ2
1
(2 • π • 2 • RFB4 • FREQSW )
Great care should be taken to route the VFB and VFB lines
away from noise sources, such as the inductor or the GATE
signal that drives the external P MOSFET.
Figure 1c. Switching Surge Stopper with VIN Operation
ABOVE 60V with Non-Inverting Feedback
Non-Inverting Feedback Option
In the Non-Inverting Feedback Option for VIN ABOVE 60V,
the voltage is programmed by connecting a feedback
resistor divider from the output to ground as shown in
Figure 1c. VOUT is divided down and the voltage presented
to the base of QFB. The base voltage is then translated into
a signal current by QFB and RFB3 and sent to PNP mirror
QFBM1, RFBM1, QFBM2 and RFBM2.
In the Non-Inverting Option, the internal inverting amplifier must be defeated by tying VFBN greater than 2V. In
Figure 1c, RZ2 and Z2 are used to tie VFBN high where Z2
is chosen greater than 2V but less than 6V. VFBN may also
be tied to the FREQ pin when the pin is floated and a fixed
535kHz switching frequency is selected. Choosing a fixed
535kHz in the Non-Inverting option can simplify the PCB
design and reduce component count.
For the Non-Inverting Option, an NPN is used for QFB, which
results in greater accuracy. The resistor RFB4 translates
the signal current proportional to VOUT into a feedback
voltage applied directly to the VFB pin. The VFBN pin is tied
high and the inverting amplifier is defeated. The output
voltage in steady state operation is set by the feedback
resistors according to the equation:

  R 
R
VOUT =  0.8V • FB3 + VBEQFB  •  1+ FB2 
RFB4

  RFB1 
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11
LTC7860
Applications Information
Switching Frequency
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating frequency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.The switching frequency and resulting
switching power loss are of secondary concern. It is
generally recommended to go with as high a switching
frequency as practical so as to limit the overall solution size.
The free-running switching frequency can be programmed
from 50kHz to 850kHz by connecting a resistor from FREQ
pin to signal ground. The resulting switching frequency
as a function of resistance on the FREQ pin is shown in
Figure 2.
1000
Current Sensing and Current Limit
Programming
The LTC7860 senses the inductor current through a current sense resistor, RSENSE, placed across the VIN and
SENSE pins. The voltage across the resistor, VSENSE, is
proportional to inductor current and in normal operation is
compared to the peak inductor current setpoint. An inductor
current limit condition is detected when VSENSE exceeds
95mV. When the current limit threshold is exceeded, the
P-channel MOSFET is immediately turned off by pulling
the GATE voltage to VIN regardless of the controller input.
The peak inductor current limit is equal to:
900
800
FREQUENCY (kHz)
Select an inductor with a saturation current rating sufficient
to cover peak current during a full load input transient
or output over load. Powder core inductors are typically
a good choice as they tend to be small and have good
saturation characteristics.
700
600
500
This inductor current limit would translate to an output
current limit based on the inductor ripple and duty factor:
400
300
200
100
0
 95mV 
IL(PEAK) ≅ 
 RSENSE 
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3863 F02
Figure 2. Switching Frequency vs Resistor on FREQ pin
Inductor Selection
A reasonable starting point for ripple current is 70% of
IOUT(MAX) at maximum VIN. The largest ripple current occurs
at the highest VIN. To guarantee that the ripple current does
not exceed a specified maximum, the inductance should
be chosen according to:
 95mV ∆IL 
IOUT(LIMIT) = 
–
 RSENSE 2 
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC7860 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
RSENSE. To ensure the integrity of the current sense signal,
VSENSE, the traces from VIN and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across RSENSE (Figure 3).
 VOUT  
VOUT 
L=
1–


 f • ∆I L(MAX)   VIN(MAX) 
12
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LTC7860
Applications Information
VIN
VIN
LTC7860
SENSE
OPTIONAL
FILTERING
CF
RSENSE
RF
MP
7860 F03
Figure 3. Inductor Current Sensing
The LTC7860 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be necessary. The filter can be created by placing a resistor from the
RSENSE resistor to the SENSE pin and a capacitor across the
VIN and SENSE pins. It is important that the VIN plane be a
clean low inductance connection with minimal PCB via's.
The maximum output current in SWITCH-ON mode is
greater than the maximum current in PROTECTIVE PWM
mode by one half the ripple current. The SWITCH-ON mode
power path components must be designed to support
the maximum power seen at the non-switching current
limit setting.
Power MOSFET Selection
The LTC7860 drives a P-channel power MOSFET that
serves as the main switch for the nonsynchronous
inverting converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage,
on-resistance RDS(ON), threshold voltage VGS(TH), and the
MOSFET’s thermal resistance θJC(MOSFET) and θJA(MOSFET).
The drain-to-source breakdown voltage must meet the
following condition:
BVDSS > VIN(MAX)
The most important parameter for selection of the PMOS
switch (after voltage rating) is RDS(ON). This will determine
PMOS loss during SWITCH-ON operation.
The gate driver bias voltage VIN-VCAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below VIN. A minimum 0.47µF capacitor
is required across the VIN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from VIN to CAP. As a result, a minimum 10V VGS rated
MOSFET is required.
Diode Selection
When the P-channel MOSFET is turned off, a commutating
diode carries the inductor current. This diode is only used
during switching and does not conduct in SWITCH-ON
mode. The average forward diode current is described as:
IF(AVG) = IOUT • (1 – D)
The worst-case condition for diode conduction is a short
circuit condition where the diode must handle the maximum
current as the P-channel MOSFET’s duty factor approaches
0%. The diode therefore must be chosen carefully to meet
worstcase voltage and current requirements. A good
practice is to choose a diode that has a forward current
rating higher than IOUT(MAX).
The diode reverse breakdown voltage must meet the following condition:
VR > VIN(MAX)
CIN and COUT Selection (Buck Mode)
The input capacitance, CIN, is required to filter the square
wave current through the P-channel MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current:
ICIN(RMS) = IOUT(MAX) •
VOUT
VIN
•
–1
VIN
VOUT
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13
LTC7860
Applications Information
The formula has a maximum at VIN = 2VOUT, where
ICIN(RMS) = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based
on only 2000 hours of life. Ripple currents will only be
applied during PROTECTIVE PWM operation, so de-rating
requirements are minimal.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The ∆VOUT is approximately bounded by:


1
∆VOUT ≤ ∆I L  ESR +
8 • f •COUT 

Soft-start is enabled by connecting a capacitor from the
SS pin to ground. An internal 10µA current source charges
the capacitor, providing a linear ramping voltage at the
SS pin that causes VOUT to rise smoothly from 0V to its
final value. The total soft-start time will be approximately:
t SS = CSS •
0.8V
10µA
Short-Circuit Faults: Current Limit and Foldback
Since �IL increases with input voltage, the output ripple
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfied, the capacitance is adequate
for filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and longterm reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
External Soft-Start
Start-up characteristics are controlled by the voltage on
the SS pin. When the voltage on the SS pin is less than
the internal 0.8V reference, the LTC7860 regulates the
VFB pin voltage to the voltage on the SS pin. When the SS
pin is greater than the internal 0.8V reference, the VFB pin
voltage regulates to the 0.8V internal reference. The SS
pin is used to program an external soft-start function. The
14
primary function of the external SOFT START feature for
a Switching Surge Stopper is as an inrush current limiter
in startup and fault recovery.
The inductor current limit is inherently set in a current mode
controller by the maximum sense voltage and RSENSE. In
the LTC7860, the maximum sense voltage is 95mV, measured across the inductor sense resistor, RSENSE, placed
across the VIN and SENSE pins. The output current limit
is approximately:
 95mV ∆IL 
ILIMIT(MIN) = 
–
 RSENSE 2 
The current limit must be chosen to ensure that
ILIMIT(MIN) > IOUT(MAX) under all operating conditions.
Short-circuit fault protection is assured by the combination
of current limit and frequency foldback. When the output
feedback voltage, VFB, drops below 0.4V, the operating
frequency, f, will fold back to a minimum value of 0.18 • f
when VFB reaches 0V. Both current limit and frequency
foldback are active in all modes of operation. In a shortcircuit fault condition, the output current is first limited
by current limit and then further reduced by folding back
the operating frequency as the short becomes more severe. The worst-case fault condition occurs when VOUT
is shorted to ground.
Short-Circuit Recovery and Internal Soft-Start
An internal soft-start feature guarantees a maximum positive output voltage slew rate in all operational cases. In a
short-circuit recovery condition for example, the output
recovery rate is limited by the internal soft-start so that
7860f
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LTC7860
VIN
VOUT
INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
~650µs
TIME
VOLTAGE
(4a)
VOUT
SHORT-CIRCUIT
INTERNAL SOFT-START
INDUCED RECOVERY
TIME
7860 F05
(4b)
Figure 4. Internal Soft-Start (4a) Allows Soft-Start without an
External Soft-Start Capacitor and Allows Soft Recovery from (4b)
a Short-Circuit
output voltage overshoot and excessive inductor current
buildup is prevented.
The internal soft-start voltage and the external SS pin
operate independently. The output will track the lower of
the two voltages. The slew rate of the internal soft-start
voltage is roughly 1.2V/ms, which translates to a total
soft-start time of 650µs. If the slew rate of the SS pin is
greater than 1.2V/ms the output will track the internal softstart ramp. To assure robust fault recovery, the internal
soft-start feature is active in all operational cases. If a
short-circuit condition occurs which causes the output to
drop significantly, the internal soft-start will assure a soft
recovery when the fault condition is removed.
The internal soft-start assures a clean soft ramp-up from
any fault condition that causes the output to droop, guaranteeing a maximum ramp rate in soft-start, short-circuit
fault release. Figure 4 illustrates how internal soft-start
controls the output ramp-up rate under varying scenarios.
VIN Undervoltage Lockout (UVLO)
nificantly, the LTC7860 is guaranteed to operate down to
a VIN of 3.5V over the full temperature range.
The implications of both the UVLO rising and UVLO falling
specifications must be carefully considered for low VIN
operation. The UVLO threshold with VIN rising is typically 3.5V (with a maximum of 3.8V) and UVLO falling is
typically 3.25V (with a maximum of 3.5V). The operating
input voltage range of the LTC7860 is guaranteed to be
3.5V to 60V over temperature, but the initial VIN ramp
must exceed 3.8V to guarantee start-up.
For example, Figure 5 illustrates LTC7860 operation
when an automotive battery droops during a cold crank
condition. The typical automotive battery voltage is 12V to
14.4V, which is more than enough headroom above 3.8V
for the LTC7860 to start up. Onboard electronics which
are powered by a DC/DC regulator require a minimum
supply voltage for seamless operation during the cold
crank condition, and the battery may droop close to these
minimum supply requirements during a cold crank. The
DC/DC regulator should not exacerbate the situation by
having excessive voltage drop between the already suppressed battery voltage input and the output of the regulator
which powers these electronics. As seen in Figure 5, the
LTC7860’s 100% duty cycle capability allows low dropout
from the battery to the output. The drop from VIN to VOUT
is determined by the output Load current multiplied by
the total series resistance of the switching surge stopper.
The 3.5V guaranteed UVLO assures sufficient margin for
continuous, uninterrupted operation in extreme cold crank
battery drooping conditions. However, additional input
capacitance or slower soft start-up time may be required
at low VIN (e.g. 3.5V to 4.5V) in order to limit VIN droop
caused by inrush currents, especially if the input source
has a sufficiently large output impedance.
VBATTERY
12V
VOLTAGE
VOLTAGE
Applications Information
VOUT
5V
The LTC7860 is designed to accommodate applications
requiring widely varying power input voltages from 3.5V
to 60V. To accommodate the cases where VIN drops sig-
LTC7860’s 100% DUTY CYCLE CAPABILITY ALLOWS
VOUT TO RIDE VIN WITHOUT SIGNIFICANT DROP-OUT
TIME
7860 F06
Figure 5. Typical Automotive Cold Crank
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15
LTC7860
Applications Information
Minimum On-Time Considerations
The minimum on-time, tON(MIN), is the smallest time
duration that the LTC7860 is capable of turning on the
power MOSFET, and is typically 220ns. It is determined
by internal timing delays and the gate charge required to
turn on the MOSFET. Low duty cycle applications may
approach this minimum on-time limit, so care should be
taken to ensure that:
tON(MIN) <
VOUT
VIN(MAX) • f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will skip cycles.
However, the output voltage will continue to regulate.
Thermal Considerations
The sustained or static power loss in SWITCH-ON operation must be limited so as to ensure suitable maximum
component temperatures during all normal operating
conditions. The temperature rise of a Switching Surge
Stopper is best measured empirically. Power Loss for
the SWITCH-ON power paths is I2RSW-ON and may be
calculated according to the equation below.
I2RSW-ON = I2 • (RSENSE + RDS(ON) + RINDUCTOR)
The dynamic or transient power loss in PROTECTIVE
PWM operation is of concern with respect to component
temperature rise and is principally managed by the timer
function which sets a maximum time in this mode. Thermal
mass and thermal resistance play key roles in determining
the peak temperatures of components at the point in time
when the timer cycles off and shuts down.
Worst-case operation for a single fault shorted output is
typically with the input voltage in the high normal operating range and the output shorted. For this condition,
the catch diode is typically the hottest component, as it
conducts nearly all the peak current at a high duty cycle.
Worst-case operation for a single fault input voltage surge
is with the input at the maximum expected input voltage or
16
profile at the maximum operational load current. An input
voltage surge and output short is a double fault and may
not be required. Specific fault testing and design margin
is determined by system requirements.
Thermal evaluation and timer setting can be most easily
done empirically by observing key component temperatures dynamically in various fault conditions. Observe
peak temperatures with an instrument with sufficient
bandwidth to track temperatures, such as an infrared
(IR) camera. One with video capability is ideal.
Set a maximum temperature rise goal based on component maximum junction temperature ratings, maximum
expected ambient temperature, and allowed junction to
case temperature rise. Start at lower input voltages and/
or shorter TMR timer settings and increase after empirical
system verification and measurement.
OPTI-LOOP® Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for a
wide range of loads and output capacitors. The ITH pin not
only allows optimization of the control loop behavior but
also provides a test point for the regulator ’s DC-coupled
and AC-filtered closed-loop response. The DC step, rise
time and settling at this test point truly reflects the closedloop response. Assuming a predominantly second order
system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant polezero loop compensation. Additionally, a small capacitor
placed from the ITH pin to signal ground, CITH2, may be
required to attenuate high frequency noise. The values can
be modified to optimize transient response once the final
PCB layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected because their various types and values
determine the loop feedback gain and phase. An output
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Applications Information
current pulse of 20% to 100% of full load current having
a rise time of 1μs to 10μs will produce output voltage and
ITH pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
fault timer
The LTC7860 is a Switching Surge Stopper. The LTC7860
switches only during startup, during an overcurrent fault
and during an input overvoltage surge (PROTECTIVE
PWM operation). The primary function of a surge stopper
is to limit the output to a programmed maximum voltage
during an input voltage surge. Limiting the output voltage
“Surge Stops” the input voltage surge and prevents it from
propagating to the system and potentially causing damage.
The Switching Surge Stopper external components are optimized to minimize total line resistance in normal operation
or SWITCH-ON mode rather than overload operation. The
fault timer limits the switching time during an overload.
The fault timer is programmed to allow the Switching
Surge Stopper to operate below a safe peak temperature
with the PWM power losses in startup, in a current limit
fault or in an input voltage surge. Since the device shuts
down before reaching thermal equilibrium, the power rating
can be significantly increased over continuous operation.
The fault timer saves system cost and size by allowing
component selections to be determined by normal or
SWITCH-ON mode rather than Protective PWM operating
mode. The timer indirectly limits the peak Switching Surge
Stopper temperatures by limiting the total time spent in
higher power loss PROTECTIVE PWM operating mode.
reverses before reaching the fault set Gate Off threshold or
VGTH the TMR pin reverses and pulls to ground by ITPDR.
Please reference Figure 6, Timer (TMR) Functional Diagram.
When the TMR pin exceeds VGTH, a fault is detected and
the PMOS Gate is turned off and is held off for a cool
down time. Once VGTH threshold is reached, the pull down
current source ITPDC pulls down the TMR until reaching
the TMR Reset Threshold or VRTH. The time the PMOS
gate is shutdown after VGTH is reached until the fault is
reset is called the cool down time. Once the fault is reset,
the TMR pin will either pull-down to ground if the fault
condition has been cleared or pulled up to VGTH if the fault
is present. In the case of a persistent fault caused by a
short circuit, TMR will continuously retry and shutdown.
Programming the Fault Timer
The TMR Initial Set Time for Fault Detection (TSETI) is the
total time allowed in PWM Regulation before the PMOS
Gate is turned off and shutdown. The constant TSETI(1µF) is
measured and can be used to calculate TSETI. The constant
includes extension (1µF) to indicate that the time is for
a 1µF capacitor and needs to be scaled by CTMR in µF’s.
TSETI can be calculated using the equations below:
TSET1 = CTMR •
VGTH
ITPU
TSET1 = CTMR • TSET(1µF)
GATE OFF
ITPU
30µA
VGTH
1.29V
TMR
CTMR
VRTH
0.24V
ITPDC
1.3µA
Fault Timer Functionality
In normal operation the TMR pin voltage is held at ground
by the current source TMR Pull-Down Reset ITPDR. When
switching is detected, the TMR Pull-Up current or ITPU
pulls up the TMR pin. If the fault is removed and the TMR
ITPDR
40µA
+
–
+
–
FAULT
TIMER
LOGIC
COOL DOWN
NORMAL OPERATION
7860 F07
Figure 6. Timer (TMR) Functional Diagram
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17
LTC7860
Applications Information
The TMR Reset Cool Down Time is TRSTC and is the total
time allowed for the system to cool down before the
PMOS Gate is turned on again after a fault. The constant
TRSTC(1µF) is measured and can be used to calculate TRSTC.
The constant includes extension (1µF) to indicate that the
time is for a 1µF capacitor and needs to be scaled by CTMR
in µF’s. TRSTC can be calculated using the equations below:
TRSTC = CTMR •
VGTH – VRTH
ITPDC
TRSTC = CTMR • TRSTC(1µF)
TSETI determines how long the switcher is allowed to
switch before shutting down. TRSTC determines how long
the switcher cools down before the PMOS Gate can be
turned on again. For a single fault exceeding TSET1, that
shuts down the Switching Surge Stopper, it will restart
after the TMR Reset Cooldown period (TRSTC).
In the case of a sustained fault the TMR pin rises after the
cool down period expires. In a sustained fault, the TMR pin
will pull up from the VRTH threshold. The TMR Set Time
Repeat after cool down is TSETR. The constant TSETR(1µF)
is measured and can be used to calculate TSETR. The constant includes extension (1µF) to indicate that the value
is for a 1µF capacitor and needs to be scaled by CTMR in
µF’s. TSETR can be calculated using the equations below:
TSETR
V −V
= CTMR • GTH RTH
ITPU
In a sustained fault, the Switching Surge Stopper will
continuously start, shutdown, cool down and restart at a
fixed duty factor. The TMR Reset duty cycle in a sustained
fault is DTYTSTR. DTYTSTR is measured and is calculated
according to the equation below.
18
TSETR
TRSTC
A Switching Surge Stopper can be designed for performance in normal operation or SWITCH-ON mode. Its
components and thermal design are optimized for normal
operation and safely operate through high voltage input
surges and/or overcurrent faults. Transient operation due
to surges and other faults can be survived because the
time in regulation is strictly limited when power loss is
high. The principle design criterion in normal operation
is the total resistance from VIN to VOUT with the resulting
power loss and thermal considerations.
As a design example, take an application with the following specifications: VIN = 8V to 14V DC with an input
voltage transient of 60V and a decay constant of 500ms,
VOUT < 18V, with a continuous output load current rating
of 5A.
We choose a P-channel MOSFET with the appropriate
BVDSS and ID rating. In this example a good choice is
the Vishay Si7461DP (BVDSS = 60V, RDS(ON) = 11.5mΩ
(typ), ρ120 = 1.6). The expected power dissipation from
the P-channel in normal operation or SWITCH-ON mode
can be calculated at TJ = 120ºC for VIN at 12V and IOUT
equal to 5A.
PPMOS = IOUT2 • RDS(ON) = 5A2 • 14.5mΩ (1.6) = 580mW
Next, set the inductor value to give 70% ripple current at
maximum VIN = 60V.

  17.2V 
17.2V
L=
  1− 60V  = 6.5µH

540kHz
•
(0.7
•
5A)
TSETR = CTMR • TSET(1µF)
DTYTSTR =
Design Example
Select 6.8µH as the nearest standard value. A good choice
for this application is the Coilcraft XAL6060-682ME, with
a DCR value of 19mΩ. The resulting ripple current is:
17.2V

  17.2V 
IRIPPLE = 
 1−
 = 3.33A
 540kHz • 6.8µH  
60V 
7860f
For more information www.linear.com/LTC7860
LTC7860
Applications Information
The output voltage is programmed according to:
 R 
VOUT = 0.8V •  1+ FB2 
 RFB1 
If RFB2 is chosen at 1M, then RFB1 is 48.7k.
The FREQ pin is floated in order to program the switching frequency to 540kHz. The on-time required at 60V to
generate 17.2V output can be calculated as:
tON =
VOUT
17.2V
=
= 531ns
VIN • f 60V • 540kHz
The average output current limit during a surge is the Normal Operation current limit minus half the ripple current.
The maximum current delivered during a surge will always
be less than in Normal Operation or SWITCH-ON mode.
ILIMIT(SURGE) =
95mV 3.33
−
= 6.25A
12mΩ
2
The total SWITCH-ON resistance RSW-ON from VIN to
VOUT is:
RSW-ON = RSENSE + RDS(ON) + RINDUCTOR
RSW-ON = 12mΩ + 11.5mΩ • (1.6) + 19mΩ = 49.4mΩ
This on-time is larger than the LTC7860’s minimum ontime with sufficient margin to prevent cycle skipping.
The total insertion loss in Normal Operation or SWITCHON mode can be calculated below.
Set the RSENSE resistor value to ensure the converter can
deliver a maximum output current of 5.0A during an input
surge with sufficient margin to account for component
variations and worst-case RSENSE data sheet tolerance.
VDROP = IOUT • RSW-ON = 5A • 49.4mΩ = 247mW
RSENSE =
85mV
= 12.1mΩ
3.33A 

1.05 •  5A +


2 
The nearest standard value for RSENSE is 12mΩ.
The current limit in Normal Operation or SWITCH-ON mode
is not reduced by the ripple current and is:
ILIMIT(SURGE) =
95mV
= 7.9A
12mΩ
RSENSE power loss for normal operation and at current
limit can be calculated according to the equations below.
PRSENSE = IOUT2 • RSENSE = 5A2 • 12mΩ = 300mW
PRSENSE = IOUT2 • RSENSE = 7.9A2 • 12mΩ = 750mW
Select a 12mΩ resistor capable of dissipating at least
one watt.
The system will need to be designed to operate in this
mode continuously. Temperature rise during a surge or
fault operation will be limited by the timer.
Choose an appropriate diode that will handle the power
requirements during the surge or fault condition. The diode
will never engage during normal operation or SWITCH-ON
mode but only during a surge or fault. The PDS5100-13
Schottky diode is selected (VF(5A, 125ºC) = 0.60V) for this
application. The continuous current rating of 5A is sufficient
during the TMR limited PROTECTIVE PWM operation. The
power dissipated during a surge or fault is.
 17.2V 
PDIODE(SURGE) = 5A •  1−
 • 0.60V = 2.14W

60V 
A soft-start time of 8ms can be programmed through a
0.1µF capacitor on the SS pin:
CSS =
8ms • 10µA
= 0.1µF
0.8V
7860f
For more information www.linear.com/LTC7860
19
LTC7860
Applications Information
A 700ms minimum time limit was chosen based on input
surge specifications. We will calculate CTMR for the worst
case using TSET(1μF) minimum and allow for a 10% tolerance and a 10% variation in capacitance over temperature.
We can calculate the required CTMR by using TSET(1µF)MIN
according to the equation below.
CTMR =
TSETIMIN
TSET(1µF)MIN
•
1 700 1
•
•
= 21µF
0.9 37 0.9
The nearest standard value for CTMR is 22µF which results
in the TMR Set Time Initial or TSETI values given by the
equations below. We assume 10% tolerance for capacitors
over temperature.
TSETITYP = TSET(1µF) • 22µF = 44 • 22µF = 968ms
TSETIMIN = TSET(1µF) • 22µF = 37 • 22µF • 0.90 = 732ms
TSETIMAX = TSET(1µF) • 22µF = 50 • 22µF • 1.1 = 1210ms
Once TSET is tripped there will be a defined TMR Reset
Cool Down Time TRSTCTYP.
TRSTCTYP = TRSTC(1µF) • 22µF = 732 • 22µF = 16.1s
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and optimized for stability.
Compensation is chosen to be 680pF and 10K.
Gate Driver Component Placement,
Layout and Routing
It is important to follow recommended power supply PC
board layout practices such as placing external power elements to minimize loop area and inductance in switching
paths. Be careful to pay particular attention to gate driver
component placement, layout and routing.
We recommend a ceramic 0.47µF 16V capacitor with a high
quality dielectric such as X5R or X7R. Some high current
applications with large Qg PMOS switches may benefit
from an even larger CCAP capacitance. The effective CCAP
capacitance should be greater than 0.1µF minimum in all
operating conditions. Operating voltage and temperature
both decrease the rated capacitance to varying degrees
depending on dielectric type. The LTC7860 is a PMOS
controller with an internal gate driver and boot-strapped
LDO that regulates the differential CAP voltage (VIN – VCAP)
to 8V nominal. The CCAP capacitance needs to be large
enough to assure stability and provide cycle-to-cycle current to the PMOS switch with minimum series inductance.
Figure 7 shows the LTC7860 Generic Application Schematic which includes an optional current sense filter and
series gate resistor. Figure 8 illustrates the recommended
gate driver component placement, layout and routing of
the GATE, VIN, SENSE and CAP pins and key gate driver
components. It is recommended that the gate driver layout
follow the example shown in Figure 8 to assure proper
operation and long term reliability.
The LTC7860 gate driver should connect to the external
power elements in the following manner. First route the
VIN pin using a single low impedance isolated trace to
the positive RSENSE resistor PAD without connection to
the VIN plane. The reason for this precaution is that the
VIN pin is internally Kelvin connected to the current sense
comparator, internal VIN power and the PMOS gate driver.
20
7860f
For more information www.linear.com/LTC7860
LTC7860
Connecting the VIN pin to the VIN power plane adds noise
and can result in jitter or instability. Figure 8 shows a single
VIN trace from the positive RSENSE pad connected to CSF,
CCAP, VIN pad and CINB. The total trace length to RSENSE
should be minimized and the capacitors CCF, CCAP and
CINB should be placed near the VIN pin of the LTC7860.
CCAP should be placed near the VIN and CAP pins. Figure 8
shows CCAP placed adjacent to the VIN and CAP pins with
SENSE routed between the pads. This is the recommended
layout and results in the minimum parasitic inductance.
The gate driver is capable of providing high peak current.
Parasitic inductance in the gate drive and the series inductance between VIN to CAP can cause a voltage spike
between VIN and CAP on each switching cycle. The voltage
spike can result in electrical over-stress to the gate driver
and can result in gate driver failures in extreme cases. It
is recommended to follow the example shown in Figure 8
for the placement of CCAP as close as is practical.
KELVIN CONNECT THE VIN PIN, CINB, CSF, CCAP CONNECTION TO
RSENSE+, DO NOT CONNECT THIS TRACE TO THE VIN POWER PLANE.
CINB
VIN PLANE
CCAP
CSS
The bypass capacitor CINB is used to locally filter the
VIN supply. CINB should be tied to the VIN pin trace and
to the PGND exposed pad. The CINB positive pad should
connect to RSENSE positive though the VIN pin trace. The
CINB ground trace should connect to the PGND exposed
pad connection.
VIN
TMR
CPITH
ZRG
CSF
SRG
SENSE
SS
CITH
RITH
RFREQ
RSF
RGATE
GATE
+
RSENSE
–
Q1
LTC7860
ITH
ROUTE VIN POWER PLANE TO
THE POSITIVE POWER INPUT
TO SENSE RESISTOR. DO NOT
CONNECT THE VIN PIN TRACE.
FREQ
SGND
VFBN
PGND
VFB
7860 F08
Figure 7. LTC7860 Generic Application Schematic with Optional
Current Sense Filter and Series Gate Resistor
RGATE resistor pads can be added with a 1Ω resistor to
allow the damping resistor to be added later. The total
length of the gate drive trace to the PMOS gate should
be minimized and ideally be less than 1cm. In most cases
with a good layout the RGATE resistor is not needed. The
RGATE resistor should be located near the gate pin to reduce peak current through GATE and minimize reflected
noise on the gate pin.
The RSF and CSF pads can be added with a zero ohm resistor for RSF and CSF not populated. In most applications,
external filtering is not needed. The current sense filter
RSF and CSF can be added later if noise if demonstrated
to be a problem.
CAP
RUN
VIN
CIN
CINB
TO Q1 GATE
RGATE
GATE
CSF
TO RSENSE+
VIN
SENSE
CAP
CCAP
RSF
TO RSENSE–
7860 F09
Figure 8. LTC7860 Recommended Gate Driver PC Board
Placement, Layout and Routing
The Zener ZRG and Schottky SRG are recommended when
driving large Power MOSFET's and should always be used
in combination with RGATE equal to 1Ω. We recommend
using a 9.1V Zener in parallel with a Schottky diode when
either the rise or fall time is measured to be greater than
30ns. The purpose of the diodes is to protect the internal
multi-Amp gate driver against possible electrical over stress
when switching the high capacitance power MOSFET Gate
through an inductive gate trace at high current.
7860f
For more information www.linear.com/LTC7860
21
LTC7860
Applications Information
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC7860.
1.Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking purposes. Use wide rails and/or entire planes for VIN, VOUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of CIN, sense resistor,
P-channel MOSFET, Schottky diode, inductor, and COUT.
Flood unused areas of all layers with copper for better
heat sinking.
2.Keep signal and power grounds separate except at the
point where they are shorted together. Short the signal
and power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small-signal components (e.g.,
CITH1, RFREQ, CSS etc.) should be referenced to the
signal ground.
3.Place CIN, sense resistor, P-channel MOSFET, inductor, and primary COUT capacitors close together in
one compact area. The junction connecting the drain
of the P‑channel MOSFET, cathode of the Schottky,
and (+) terminal of the inductor (this junction is commonly referred to as switch or phase node) should be
compact but be large enough to handle the inductor
currents without large copper losses. Place the sense
resistor and source of P-channel MOSFET as close
as possible to the (+) plate of the CIN capacitor(s)
22
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the (–)
terminal of the inductor as close as possible to the
(–) terminal of the same CIN capacitor(s). The high
dI/dt loop formed by CIN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (+) terminal of the primary COUT
capacitor(s) which filter the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of CIN.
4.Place Pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small-signal traces and components.
5.Place the sense resistor close to the (+) terminal of CIN
and source of P-channel MOSFET. Use a Kelvin (4-wire)
connection across the sense resistor and route the traces
together as a differential pair into the VIN and SENSE
pins. An optional RC filter could be placed near the VIN
and SENSE pins to filter the current sense signal.
6.Place the feedback divider RFB1/2 as close as possible to
the VFB and VFBN pins. The (–) terminal of the feedback
divider should connect to the output regulation point
and the (+) terminal of the feedback divider should
connect to VFB.
7.Place the ceramic CCAP capacitor as close as possible to
the VIN and CAP pins. This capacitor provides the gate
discharging current for the power P-channel MOSFET.
8.Place small signal components as close to their respective pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to VFB,
ITH, and FREQ pins.
7860f
For more information www.linear.com/LTC7860
LTC7860
Typical Applications
3.5V to 60V Input, 12V/18V Maximum 5A Output at 535kHz
OPTIONAL REVERSE
BATTERY PROTECTION
L1
MP1
6.8µH
Si7461DP XAL6060-682ME
RSENSE
12mΩ
ALT VIN
60V MAX OPT REV
12V NOM
MP2
–60V MIN Si7461DP
VIN
60V MAX
12V NOM
3.5V MIN
CIN1
10µF
CSF
100pF
VIN
D1
PDS5100-13
RSF
OPT
CFF
3.9pF
SENSE GATE
VFBN
VOUT
18V MAX
12V NOM
3.5V MIN
5A
RFB2
1M
COUT1
10µF
VFB
FREQ
CCAP1
0.47µF
RRUN1
100k
CITH1
680pF
0.1µF RITH1
10k
CITH2
10pF
RFB1
48.7k
CAP
TMR
LTC7860
RUN
SS
ITH
CTMR
22µF
CSS1
0.1µF
SGND PGND
7860 TA02a
PROTECTIVE PWM: VOUT Clamped
to 18V During a VIN Surge
60V INPUT SURGE
PROTECTIVE PWM: VOUT Clamped
for TMR Timer Set Initial (TSETI)
PROTECTIVE PWM: VOUT Shutdown
for TMR Reset Cool Down (TRSTC)
CTMR = 22µF
CTMR = 22µF
CTMR = 22µF
60V INPUT SURGE
VIN
20V/DIV
VIN
10V/DIV
VOUT
10V/DIV
60V INPUT SURGE
VOUT
20V/DIV
18V ADJUSTABLE CLAMP
VIN
20V/DIV
OUTPUT CLAMP
VOUT
20V/DIV
TSETI
VTMR
1V/DIV
VTMR
1V/DIV
100ms/DIV
7860 TA02b
TMR TIME SET INITIAL (TSETI)
200ms/DIV
7860 TA02c
VTMR
1V/DIV
OUTPUT SHUTDOWN
TRSTC
TMR RESET COOL DOWN (TRSTC)
2s/DIV
7860 TA02d
7860f
For more information www.linear.com/LTC7860
23
LTC7860
Typical Applications
8V to 100V Input, 28V Nominal/34V Maximum, 10A Output at 400kHz with Non-Inverting Feedback Option
OPTIONAL REVERSE
BATTERY PROTECTION
ALT VIN
100V MAX
28V NOM
–100V MIN
RSENSE
7mΩ
MP2
OPT REV SUM90P10-19L
VIN
100V MAX
28V NOM
8V MIN
+
CIN1
1µF 250V
×3
CIN2
OPT
MP1
SUM90P10-19L
RSENSE
100Ω
RG
1Ω
L1
33µH
7443633300
D2
STPS30M100DJF
+
COUT1
150µF
VOUT
34V MAX
28V NOM
8V MIN
10A
COUT2
10µF 50V
×3
CGATE
1000pF
R1
100k
D7
CM024L3
4.3V
VIN
VFBN
CCAP
0.47µF
CIN3
0.1µF
RRUN
100k
R5
100k
CVIN1
0.1µF
D5
CMHZ5242B
12V
RFREQ1
61.9k
CITH1
3.3µF
RITH1
10k
CSENSE
100pF
R3
4.99k
GATE
SENSE
PNP
Q1
CAP
PNP
Q2
Q1, Q2
BC857BS
VFB
RUN
LTC7860
RFB4
10k
TMR
SS
FREQ
ITH
CTMR
22µF
CSS1
0.1µF
SGND PGND
PBHV9215Z115
Q5
D4
CMHZ5242B
12V
R4
4.99k
RFB1
10k
Q3
KST43
MN1
TN5325K1G
RFB3
205k
R2
1k
RFB2
10k
7860 TA03a
PROTECTIVE PWM: VOUT Clamped
to 34V During a VIN Surge
100V INPUT SURGE
VIN
25V/DIV
VOUT
25V/DIV
34V ADJUSTABLE CLAMP
VTMR
1V/DIV
VTMR
1V/DIV
100ms/DIV
24
7860 TA03b
PROTECTIVE PWM: VOUT Shutdown
for TMR Reset Cool Down (TRSTC)
CTMR = 22µF
CTMR = 22µF
VIN
20V/DIV
VOUT
20V/DIV
PROTECTIVE PWM: VOUT Clamped
for TMR Timer Set Initial (TSETI)
100V INPUT SURGE
VIN
25V/DIV
VOUT
25V/DIV
OUTPUT CLAMP
TSETI
VTMR
1V/DIV
TMR TIME SET INITIAL (TSETI)
200ms/DIV
CTMR = 22µF
7860 TA03c
100V INPUT SURGE
OUTPUT SHUTDOWN
TRSTC
TMR RESET COOL DOWN (TRSTC)
2s/DIV
7860 TA03c
7860f
For more information www.linear.com/LTC7860
LTC7860
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.23
(.206)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
6
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
12
0.65
0.42 ±0.038
(.0256)
(.0165 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
1 2 3 4 5 6
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0911 REV F
7860f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC7860
25
LTC7860
Typical Application
8V to 100V Input, 28V Nominal/34V Maximum, 10A Output at 400kHz with Inverting Feedback Option
OPTIONAL REVERSE
BATTERY PROTECTION
RSENSE
7mΩ
MP2
ALT VIN
100V MAX OPT REV SUM90P10-19L
28V NOM
VIN
–100V MIN
100V MAX
28V NOM
8V MIN
+
CIN2
OPT
CIN1
1µF 250V
×3
MP1
SUM90P10-19L
RSF
100Ω
CGATE
1000pF
L2
33µH
7443633300
D1
STPS30M100DJF
+
COUT1
10µF 50V
×3
COUT2
150µF
RG
1Ω
VOUT
34V MAX
28V NOM
8V MIN
10A
CSF
100pF
VIN
SENSE
CCAP
0.47µF
CIN3
0.1µF
RRUN
100k
R5
100k
CVIN1
0.1µF
D6
CMHZ5242B
12V
RFREQ
61.9k
RITH1
10k
CITH1
3.3nF
VFB
CAP
RUN
GATE
CFB1
47pf
LTC7860
VFBN
TMR
FREQ
SGND PGND
PBHV9215Z115
Q1
D3
CMHZ5242B
12V
CTMR
22µF
SS
ITH
RFB4
10k
CSS1
0.1µF
RFBN2
1M
RFBN1
10k
RFB1
10k
MN2
TN5325K1G
MN1
TN5325K1G
R2
1k
RFB3
191k
RFB2
10k
7860 TA04
Related Parts
PART NUMBER
LT4356-1
DESCRIPTION
High Voltage Surge Stopper
COMMENTS
100V Overvoltage and Overcurrent Protection, Latch-Off and Auto-Retry Option
LTC4364
LT4363
Surge Stopper with Ideal Diode
High Voltage Surge Stopper
4V to 80V Operation; –40V Reverse Input, –20V Reverse Output Protection
100V Overvoltage and Overcurrent Protection, Latch-Off and Auto-Retry Options
LTC4366-1, LTC4366-2
LTC3864
High Voltage Surge Stopper
Low IQ, High Voltage Step-Down DC/DC
Controller with 100% Duty Cycle
Wide Operating Voltage Range: 9V to >500V Rugged Floating Topology
Fixed Frequency 50kHz to 850kHz, 3.5V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN,
IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12
26 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC7860
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com/LTC7860
7860f
LT 0215 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015