DATASHEET

EL7566
®
Data Sheet
May 8, 2006
Monolithic 6A DC/DC Step-Down
Regulator
FN7102.7
Features
• Integrated MOSFETs
The EL7566 is a full-feature synchronous step-down regulator
capable of up to 6A and 96% efficiency. The device operates
from 3V to 6V input supply (VIN). With internal CMOS power
FETs, the device can operate at up to 100% duty ratio,
allowing for an output voltage range of 0.8V to nearly VIN. An
adjustable switching frequency up to 1MHz enables the use of
small components, thereby reducing board area consumption
to under 0.72sq-in on one side of a PCB. The EL7566
operates in constant frequency PWM mode, making external
synchronization possible. A soft-start feature is integrated in
the EL7566 to limit in-rush currents and allow for a smooth
voltage ramp from zero to regulation. Other start-up features
are integrated to add flexibility for synchronizing many
supplies in multiple configurations. The EL7566 also offers a
voltage margining capability that shifts the output voltage ±5%
for validation of system card performance and reliability during
manufacturing tests. A junction temperature indicator
conveniently monitors the silicon die temperature, saving time
in thermal characterization.
An easy-to-use simulation tool is available for download and
can be used to modify design parameters such as switching
frequency, voltage ripple, ambient temperature, as well as
view schematics waveforms, efficiency graphs, and
complete BOM with Gerber layout.
• 6A continuous output current
• Up to 96% efficiency
• Multiple supply start-up tracking
• Built-in ±5% voltage margining
• 3V to 6V input voltage
• 0.72 in2 footprint with components on one side of PCB
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• 100% duty ratio
• Junction temperature indicator
• Over-temperature protection
• Internal soft-start
• Variable output voltage down to 0.8V
• Power-good indicator
• 28 Ld HTSSOP package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Point-of-regulation power supplies
• FPGA Core and I/O supplies
• DSP, CPU Core, and IO supplies
• Logic/Bus supplies
• Portable equipment
Related Documentation
• Technical Brief 415 - Using the EL7566 Demo Board
• Easy-to-use applications software simulation tool available
at www.intersil.com/dc-dc
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7566
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL TEMP RANGE (°C)
PACKAGE
PKG. DWG. #
EL7566DRE
7566DRE
-
0 to 85
28 Ld HTSSOP
MDP0048
EL7566DRE-T7
7566DRE
7”
0 to 85
28 Ld HTSSOP
MDP0048
EL7566DRE-T13
7566DRE
13”
0 to 85
28 Ld HTSSOP
MDP0048
EL7566DREZ (Note)
7566DREZ
-
0 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
EL7566DREZ-T7 (Note)
7566DREZ
7”
0 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
EL7566DREZ-T13 (Note)
7566DREZ
13”
0 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
EL7566AIREZ (Note)
7566AIREZ
-40 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
EL7566AIREZ-T7 (Note)
7566AIREZ
7”
-40 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
EL7566AIREZ-T13 (Note)
7566AIREZ
13”
-40 to 85
28 Ld HTSSOP (Pb-free)
MDP0048
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Typical Application Diagram
R2
10K
CC
RC
8200pF
10K
1 COMP
SGND 28
2 VREF
COSC 27
270pF
0.047µF
R1
21.5K
3 FB
STN 26
4 VO
STP 25
5 VTJ
EN 24
6 TM
PG 23
0.22µF
7 SEL
2.7µH
VOUT
(2.5V, 6A)
150µF
2
VDD 22
8 LX
VIN 21
9 LX
VIN 20
10 LX
VIN 19
11 LX
PGND 18
12 LX
PGND 17
13 LX
PGND 16
14 NC
NC 15
VIN
(3V TO
6V)
100µF
FN7102.7
May 8, 2006
EL7566
Absolute Maximum Ratings (TA = 25°C)
VIN, VDD to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN +0.3V
SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
COMP, VREF, FB, VO, VTJ, TM,
SEL, PG, EN, STP, STN, COSC to SGND . . . . . -0.3V to VDD +0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Operating Ambient Temperature DRE . . . . . . . . . . . . . 0°C to +85°C
Operating Ambient Temperatute AIRE . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VDD = VIN = 3.3V, TA = TJ = 25°C, COSC = 390pF, Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
VIN
Input Voltage Range
3
VREF
Reference Accuracy
1.24
VREFTC
Reference Temperature Coefficient
VREFLOAD
Reference Load Regulation
VRAMP
Oscillator Ramp Amplitude
IOSC_CHG
Oscillator Charge Current
IOSC_DIS
TYP
1.26
MAX
UNIT
6
V
1.28
V
50
0 < IREF < 50µA
ppm/°C
-1
%
1.15
V
0.1V < VOSC < 1.25V
200
µA
Oscillator Discharge Current
0.1V < VOSC < 1.25V
8
mA
IVDD
VDD Supply Current
VEN = 1 (L disconnected)
IVDD_OFF
VDD Standby Current
EN = 0
VDD_OFF
VDD for Shutdown
VDD_ON
VDD for Startup
2
2.7
5
mA
1
1.5
mA
2.4
2.65
V
2.6
2.95
V
TOT
Over-temperature Threshold
135
°C
THYS
Over-temperature Hysteresis
20
°C
ILEAK
Internal FET Leakage Current
ILMAX
Peak Current Limit
EN = 0, LX = 6V (low FET), LX = 0V (high FET)
10
7.8
µA
A
RDSON1
PMOS On Resistance
29
RDSONTC2
NMOS On Resistance
25
mΩ
RDSONTC
RDSON Tempco
0.2
mΩ/°C
2.5
µA
ISTP
STP Pin Input Pull-down Current
VSTP = VIN/2
ISTN
STN Pin Input Pull-up Current
VSTN = VIN/2
VPGP
Positive Power Good Threshold
With respect to target output voltage
VPGN
Negative Power Good Threshold
VPG_HI
VPG_LO
VOVP
µA
6
14
%
With respect to target output voltage
-14
-6
%
Power Good Drive High
IPG = 1mA
2.6
Power Good Drive Low
IPG = -1mA
10
ILOAD = 0A
VFB_LINE
Output Line Regulation
VIN = 3.3V, ΔVIN = 10%, ILOAD = 0A
Error Amplifier Transconductance
VCC = 0.65V
Output Temperature Stability
0°C < TA < 85°C, ILOAD = 3A
FS
Switching Frequency
IFB
Feedback Input Pull-up Current
3
V
0.5
Output Overvoltage Protection
Output Initial Accuracy
VFB_TC
2.5
mΩ
4
VFB
GMEA
-4
50
0.79
85
VFB = 0V
%
0.8
0.81
V
0.2
0.5
%
125
165
µs
±1
300
V
%
370
440
kHz
100
200
nA
FN7102.7
May 8, 2006
EL7566
DC Electrical Specifications
PARAMETER
VDD = VIN = 3.3V, TA = TJ = 25°C, COSC = 390pF, Unless Otherwise Specified (Continued)
DESCRIPTION
VEN_HI
EN Input High Threshold
VEN_LO
EN Input Low Threshold
IEN
Input High Level
TM, SEL_LO
Input Low Level
MIN
TYP
MAX
UNIT
2.6
V
1
Enable Pull-up Current
TM, SEL_HI
CONDITIONS
VEN = 0
-4
V
-2.5
µA
2.6
V
1
V
Pin Descriptions
PIN NUMBER
PIN NAME
1
COMP
Error amplifier output; place loop compensation components here
2
VREF
Bandgap reference bypass capacitor; typically 0.022µF to 0.047µF to SGND
3
FB
Voltage feedback input; connected to external resistor divider between VOUT and SGND for adjustable
output; also used for speed-up capacitor connection
4
VO
Output sense for fixed output option. This pin can be open for EL7566
5
VTJ
Junction temperature monitor output
6
TM
Stress test enable; allows ±5% output movement; connect to SGND if function is not used
7
SEL
Positive or negative stress select; see text
8, 9, 10, 11, 12, 13
LX
Inductor drive pin; high current output whose average voltage equals the regulator output voltage
14, 15
NC
Not used
16, 17, 18
PGND
19, 20, 21
VIN
Power supply input of the regulator; connected to the drain of the high-side PMOS Power FET
22
VDD
Control circuit positive supply; connected to VIN through an internal 20Ω resistor
23
PG
Power-good window comparator output; logic 1 when regulator output is within ±10% of target output
voltage
24
EN
Chip enable, active high; a 2.5µA internal pull-up current enables the device if the pin is left open; a
capacitor can be added at this pin to delay the start of a converter
25
STP
Auxilliary supply tracking positive input; tied to regulator output to synchronize start-up with a second
supply; leave open for standalone operation; 2µA internal pull-up current
26
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start-up;
leave open for standalone operation; 2µA internal pull-up current
27
COSC
Oscillator timing capacitor (see performance curves)
28
SGND
Control circuit negative supply or signal ground
4
PIN FUNCTION
Ground return of the regulator; connected to the source of the low-side synchronous NMOS Power FET
FN7102.7
May 8, 2006
EL7566
Block Diagram
TM
0.047µF
SEL
COSC
VREF
VTJ
VDD
2.2nF
JUNCTION
TEMPERATURE
VOLTAGE
REFERENCE
390pF
OSCILLATOR
VDD
EN
20Ω
0.22µF
VIN
STP
POWER
TRACKING
STN
PWM
CONTROLLER
VIN
100µF
POWER
FET
2.7µH
DRIVERS
VOUT
(2.5V, 6A)
POWER
FET
150µF
PGND
EA
CURRENT
SENSE
COMP
VDD
RC
VREF
CC
SGND
FB
R1
+
PG
VO
R2
5
FN7102.7
May 8, 2006
EL7566
Typical Performance Curves
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.7µH, CIN = 100µF, COUT = 150µF, TA = 25°C unless otherwise noted.
100
100
VO=3.3V
90
85
VO=0.8V
80
75
VO=1V
70
VO=1.2V
VO=2.5V
95
EFFICIENCY (%)
EFFICIENCY (%)
95
VO=2.5V
VO=1.8V
65
VO=1.8V
90
85
VO=0.8V
80
VO=1V
75
70
VO=1.2V
65
60
60
0
1
2
3
4
5
6
0
1
2
3
IO (A)
4
5
6
IO (A)
FIGURE 1. EFFICIENCY (VIN = 5V)
FIGURE 2. EFFICIENCY (VIN = 3.3V)
1.265
1.6
VDD=3.3V
1.26
1.5
VTJ
VDD=5V
1.25
1.3
1.2
VDD=3.3V
VDD=5V
1.1
1.24
1
1.245
0
50
100
0
150
0
50
JUNCTION TEMPERATURE (°C)
FIGURE 3. VREF vs TEMPERATURE
1200
3.5
1000
VEN_HI
800
2.5
2
VEN_LOW
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 5. VEN_HI & VEN_LOW vs VDD
6
VDD=3.3V
200
1
3
VDD=5V
600
500
1.5
150
FIGURE 4. VTJ vs TEMPERATURE
4
3
100
JUNCTION TEMPERATURE (°C)
FS (kHz)
VREF
1.4
1.255
6
0
100
200
300
400
500
600
700
COSC (pF)
FIGURE 6. FS vs COSC
FN7102.7
May 8, 2006
EL7566
Typical Performance Curves
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.7µH, CIN = 100µF, COUT = 150µF, TA = 25°C unless otherwise noted. (Continued)
526
0.1
0.05
522
0
VIN=5V
520
-0.05
518
516
(%)
SWITCHING FREQUENCY
524
514
512
-0.2
VIN=3.3V
510
-0.1
-0.15
-0.25
508
506
-0.3
504
-0.35
1
0
3
2
5
4
6
0
1
2
IO (A)
3
4
5
6
IO (A)
FIGURE 7. FS vs LOAD CURRENT
FIGURE 8. LOAD REGULATIONS
50
CONDITION:
28-Pin HTSSOP THERMAL PAD
SOLDERED TO 2-LAYER PCB
WITH 0.039" THICKNESS AND
1 OZ. COPPER ON BOTH SIDES
θJA (°C/W)
45
40
35
30
25
1
2
3
4
5
6
7
8
3.0
8
P2
SO C/W
TS 30°
H
=
A
θJ
ALLOWABLE POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
3.5
2.5
2.0
1.5
1.0
0.5
0
9
0
25
PCB AREA (in2)
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.00
0.90
0.80
H
8
P2 W
/
S O °C
TS 10
=1
0.70
A
θJ
ALLOWABLE POWER DISSIPATION (W)
FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA
(NO AIR FLOW)
0.60
0.50
0.40
0.30
0.20
0.10
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
7
FN7102.7
May 8, 2006
EL7566
Waveforms
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.7µH, CIN = 100µF, COUT = 150µF, TA = 25°C unless otherwise noted.
ΔVIN (200mV/DIV)
VIN (5V/DIV)
IL (2A/DIV)
IIN (2A/DIV)
VO (2V/DIV)
VLX (5V/DIV)
PG
ΔVO (50mV/DIV)
1µs/DIV
0.5ms/DIV
FIGURE 12. START-UP
FIGURE 13. STEADY-STATE OPERATION
4.5A
VEN
IO
1.5A
IIN (2A/DIV)
ΔVO (100mV/DIV)
VO (2V/DIV)
50µs/DIV
100µs/DIV
FIGURE 14. SHUT-DOWN
FIGURE 15. TRANSIENT RESPONSE
TM
PG
SEL
VO (2V/dIv)
ΔVO (200mV/DIV)
VLX (5V/DIV)
1ms/DIV
0.5ms/DIV
FIGURE 16. VOLTAGE MARGINING
8
FIGURE 17. OVERVOLTAGE SHUT-DOWN
FN7102.7
May 8, 2006
EL7566
Waveforms
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.7µH, CIN = 100µF, COUT = 150µF, TA = 25°C unless otherwise noted. (Continued)
VIN (5V/DIV)
VIN (5V/DIV)
IIN (2A/DIV)
VO1=2.5V
VO (2V/DIV)
VO2=1.8V
PG
5ms/DIV
5ms/DIV
FIGURE 18. ADJUSTABLE START-UP
FIGURE 19. TRACKING START-UP
Detailed Description
The EL7566 is a 6A capable buck regulator operating from
an input voltage range of 3V to 6V. The duty cycle can be
adjusted from 0% to 100% allowing for a wide range of
programmable output voltages. Patented on-chip
resistorless current-sensing enables current mode control
for excellent step load response. Overcurrent, Overvoltage,
input Undervoltage, and thermal protection is integrated
along with soft-start and power-up sequencing features to
produce an overall robust power solution for general
purpose applications.
placed from the EN pin to GND to program a delay between
when the rising POR threshold for VIN is met and when softstart begins. The programmable delay time, TD, is governed
by Equation 1.
V EN_HI
T D = C EN × -------------------I
EN
where:
• CEN is the capacitance at EN pin
EL7566DRE vs. EL7566AIRE
• VEN_HI is the EN input high level (function of VDD voltage,
see Figure 5)
The EL7566AIRE includes the following feature changes
from the EL7566DRE:
• IEN is the EN pin pull-up current, nominal 2.5µA
• Up to 6A Current Sinking Capability
Steady-State Operation
• Expanded Temperature Range: -40oC to 85oC
• No Overvoltage Protection
Start-Up
The EL7566 employs a digital soft-start feature to suppress
the in-rush current needed to charge the output capacitance
and smoothly ramp the output voltage to regulation (See
Figure 12). The normal start-up process begins when the
input voltage reaches the rising POR threshold (~2.8V) and
EN pin is transitioned HIGH by an internal 2.5µA current
source. The output voltage is then digitally ramped to
regulation over a 2ms period. The 2ms soft start-up time can
be extended if needed by configuring the STP and STN pins.
(refer to Full Start-Up Control section).
If the input voltage is ramped slowly, soft-start may be
initiated before the input supply has reached regulation. The
lower input voltage will have increased current demand
during start-up and may risk an overcurrent event. To
prevent such an event from occurring, a capacitor can be
9
Under all steady-state conditions the converter will operate
in fixed frequency continuous-conduction mode. For fast
transient response and ease of controllability, a peak
current-mode control method is employed. The inductor
current is sensed from the upper PMOS. This current signal
serves as the ramp to the PWM comparator and is compared
against the difference signal generated by the
transconductance error amplifier. Slope compensation for
the ramp is used to allow for 100% duty cycle operation (see
Figure 20). The pulse-width modulated square wave output
of the PWM comparator is amplified and serves as the gate
drive signals for the switching power FETs.
100% DUTY RATIO
EL7566 uses CMOS as internal synchronous power
switches. The upper and lower switches are PMOS and
NMOS respectively. The upper PMOS saves the need for a
boot capacitor normally seen in NMOS/NMOS half-bridges.
FN7102.7
May 8, 2006
EL7566
It also allows 100% turn-on of the upper PMOS switch,
achieving VO close to VIN. The maximum achievable VO is:
V O = V IN – ( R L + R DSON1 ) × I O
OSC pin to GND (COSC). The triangle waveform has 95%
duty ratio and runs from 0.2V to 1.2V. Refer to the curve in
Figure 6 for the appropriate value of COSC for the desired
frequency. If external synchronization is desired, the circuit
in Figure 21 can be used.
Where RL is the DC resistance on the inductor and RDSON1
is the PMOS on-resistance, nominally 30mΩ at room
temperature with a temperature coefficient of 0.2mΩ/°C.
100pF
EL7566
OUTPUT VOLTAGE SELECTION
COSC
The output voltage can be as high as the input voltage minus
the PMOS and inductor voltage drops (as seen previously in
Equation 2). Referring to the Typical Application Circuit on
page 2, use R1 and R2 to set the output voltage according to
the following formula:
R 1⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R
⎝
2⎠
EXTERNAL SYNC
SOURCE
FIGURE 20. EXTERNAL SYNC CIRCUIT
Always choose the converter self-switching frequency 20%
lower than the sync frequency to accommodate component
variations.
Protection Features
Some standard values of R1 and R2 are listed in Table 1.
TABLE 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
2
Open
1
2.49
10
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
36
11.5
It is important that the series combination of R1 and R2 is
large enough as to not draw excessive current from the
output.
VOLTAGE MARGINING
The EL7566 has built-in 5% load stress test (commonly
called voltage margining) function. Combinations of TM and
SEL set the margins shown in Table 2. When this function is
not used, both pins should be connected to SGND, either
directly or through a 10kΩ resister. Figure 16 shows this
feature.
TABLE 2.
CONDITION
TM
SEL
VO
Normal
0
X
Nominal
High Margin
1
1
Nominal + 5%
Low Margin
1
0
Nominal - 5%
SWITCHING FREQUENCY
The regulator has a programmable switching frequency of
200kHz to 1MHz. The switching frequency is generated by a
relaxation comparator and adjusted by a capacitor from the
10
The EL7566 features a wide range of protective measures to
prevent the persistence of damaging system conditions.
These features are overvoltage, overcurrent, Power-OnReset (POR), and Thermal Shutdown protection.
OVERVOLTAGE PROTECTION (OVP)
The EL7566 monitors the output voltage and will shut down
if it exceeds 110% of the set regulation point. This is
accomplished by comparing the reference to the FB pin
voltage. If an overvoltage condition is met, the controller will
turn the high-side switch off, the low-side switch on, and pull
PGOOD low. The converter will not latch off and will proceed
with a soft-start as soon as the fault condition is cleared.
OVERCURRENT PROTECTION (OCP)
The current information for PWM ramp generation is also
used for overcurrent protection. The measured current is
compared against a preset Overcurrent threshold (~7-10A).
If the output current exceeds the threshold, the output will
shut down by turning off the high-side switch and turning the
low-side switch on. This event, like OVP, will not latch the
converter off. A soft-start will be initiated when the fault is
cleared.
POWER-ON RESET (POR)
To ensure proper regulator operation, a power-on reset
feature monitors the input voltage. When adequate input
voltage is achieved (VDD > 2.8V), the converter is allowed to
soft-start. However, if VDD falls below 2.5V, the regulator will
shut down in the same manner as OVP or OCP.
THERMAL PROTECTION AND JUNCTION
TEMPERATURE INDICATOR
An internal temperature sensor continuously monitors the
junction temperature. If the junction temperature exceeds
135°C, the regulator is in a fault condition and will shut
down. When the temperature falls back below 110°C, the
regulator goes through the soft-start procedure again.
FN7102.7
May 8, 2006
EL7566
The VTJ pin reports a voltage proportional to the junction
temperature. Equation 3 illustrates the relationship and can
be used to accurately evaluate thermal design points.
1.2 – V TJ
T J = 75 + -----------------------0.00384
LINEAR START-UP
In the linear start-up tracking configuration, the regulator with
lower output voltage, VO2, tracks the one with higher output
voltage, VO1.
C
Full Start-Up Control
The EL7566 offers full start-up control. The core of this
control is a start-up comparator in front of the main PWM
controller. The STP and STN are the inputs to the
comparator, whose HI output forces the PWM comparator to
skip switching cycles. The user can choose any of the
following control configurations:
+
VO2
+
STN
STP
R
VO1
EL7566
VIN
EL7566
VIN
VO1
VO2
ADJUSTABLE SOFT-START
In this configuration, the ramp-up time is adjustable to any
time longer than the building soft-start time of 2ms. The
approximate ramp-up time, TST, is:
⎛ VO ⎞
T ST = RC ⎜ ---------⎟
⎝ V IN⎠
FIGURE 23. LINEAR START-UP TRACKING
OFFSET START-UP
Compared with the cascade start-up, this configuration
allows Regulator 2 to begin the start-up process when VO1
reaches a particular value of VREF*(1+RB/RA) before PG
goes HI, where VREF is the regulator reference voltage.
VREF=1.26.
+
VO
STN
C
STP
R
200K
EL7566
0.1µF
VO
VREF
VIN
VO2
TST
RB
+
RA
VO1
EL7566
FIGURE 21. ADJUSTABLE START-UP
VIN
EL7566
CASCADE START-UP
VIN
VREF(1+RB/RA)
In this configuration, EN pin of Regulator 2 is connected to
the PG pin of Regulator 1 (Figure 22). VO2 will only start
after VO1 is good.
VO1
VO2
FIGURE 24. OFFSET START-UP TRACKING
EN
VO2
PG
VO1
EL7566
Component Selection
VIN
EL7566
VO1
VO2
FIGURE 22. CASCADE START-UP
INPUT CAPACITOR
The main functions of the input capacitor(s) are to maintain
the input voltage steady and to filter out the pulse current
passing through the upper switch. The root-mean-square
value of this current is:
V O × ( V IN – V O )
I IN,RMS = ----------------------------------------------- × I O ≈ 1/2 ( I O )
V IN
for a wide range of VIN and VO.
For long-term reliability, the input capacitor or combination of
capacitors must have the current rating higher than IIN,RMS.
Use X5R or X7R type ceramic capacitors, or SPCAP or
POSCAP types of Polymer capacitors for their high current
handling capability.
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EL7566
INDUCTOR
where:
The NMOS positive current limit is set at about 8A. For
optimal operation, the peak-to-peak inductor current ripple
ΔIL should be less than 1A. The following equation gives the
inductance value:
• GMPWM is the transconductance of the PWM comparator,
GMPWM = 120S
( V IN – V O ) × V O
L = -------------------------------------------V IN × ΔI L × F S
VO
R OUT = -------IO
• ESR is the ESR of the output capacitor
The peak current the inductor sees is:
• COUT is output capacitance
• GMEA is the transconductance of the error amplifier,
GMEA = 120µS
ΔI L
I LPK = I O + -------2
When inductor is chosen, it must be rated to handle the peak
current and the average current of IO.
• FC is the intended crossover frequency of the loop. For
best performance, set this value to about one-tenth of the
switching frequency.
• Once RC is chosen, CC is decided by:
OUTPUT CAPACITOR
Output voltage ripple and transient response are the
predominant factors when choosing the output capacitor.
Initially, output capacitance should be sized with an ESR to
satisfy the output ripple ΔVO requirement:
R OUT
C C = 1.5 × C OUT × ---------------RC
Design Example
A 5V to 2.5V converter with a 6A load requirement.
ΔV O = ΔI L × ESR
1. Choose the input capacitor
When a step load change, ΔIO, is applied to the converter,
the initial voltage drop can be approximated by ESR*ΔIO.
The output voltage will continue to drop until the control loop
begins to correct the output voltage error. Increasing the
output capacitance will lessen the impact of load steps on
output voltage. Increasing loop bandwidth will also reduce
output voltage deviation under step load conditions. Some
experimentation with converter bandwidth and output
filtering will be necessary to generate a good transient
response (Reference Figure 15).
As with the input capacitor, it is recommended to use X5R or
X7R type of ceramic capacitors. SPCAP or POSCAP type
Polymer capacitors can also be used for the low ESR and
high capacitance requirements of these converters.
Generally, the AC current rating of the output capacitor is not
a concern because the RMS current is only 1/8 of ΔIL.
LOOP COMPENSATION
Current-mode control in system forces the inductor current
to be proportional to the error signal. This has the advantage
of eliminating the double pole response of the output filter,
and reducing complexity in the overall loop compensation. A
simple Type 1 compensator is adequate to generate a
stable, high-bandwidth converter. The compensation resister
is decided by:
F C × 2 × π × ( ESR + R OUT ) × C OUT
IO
R C = ------------ × ------------------------------------------------------------------------------------------------VFB
GM PWM × GM EA
12
The input capacitor or combination of capacitors has to be
able to take about 1/2 of the output current, e.g., 3A.
Panasonic EEFUD0J101XR is rated at 3.3A, 6.3V, meeting
the above criteria.
2. Choose the inductor. Set the converter switching
frequency at 500kHz:
( V IN – V O ) × V O
L = -------------------------------------------V IN × ΔI L × F S
ΔIL = 1A yields 2.3µH. Leave some margin and choose
L = 2.7µH. Coilcraft's DO3316P-272HC has the required
current rating.
3. Choose the output capacitor
L = 2.7µH yields about 1A inductor ripple current. If 25mV of
ripple is desired, COUT's ESR needs to be less than 25mΩ.
Panasonic's EEFUD0G151XR 150µF has an ESR of 12mΩ
and is rated at 4V.
ESR is not the only factor deciding the output capacitance.
As discussed earlier, output voltage droops less with more
capacitance when converter is in load transient. Multiple
iterations may be needed before final components are
chosen.
4. Loop compensation
50kHz is the intended crossover frequency. With the
conditions RC and CC are calculated as:
RC = 10.5kΩ and CC = 8900pF, round to standard value of
8200pF.
FN7102.7
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EL7566
For convenience, Table 3 lists the compensation values for
frequently used output voltages.
TABLE 3. COMPENSATION VALUES
VO (V)
RC (kΩ)
CC (pF)
3.3
13.7
8200
2.5
10.5
8200
1.8
7.68
8200
1.5
6.49
8200
1.2
5.23
8200
1
4.42
8200
0.8
3.57
8200
Thermal Management
The EL7566 is packaged in a thermally-efficient HTSSOP-28
package, which utilizes the exposed thermal pad at the
bottom to spread heat through PCB metal.
Layout Considerations
The layout is very important for the converter to function
properly. Follow these tips for best performance:
1. Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the SGND pin
2. Place the input capacitor(s) as close to VIN and PGND
pins as possible
3. Make as small as possible the loop from LX pins to L to
CO to PGND pins
4. Place R1 and R2 pins as close to the FB pin as possible
5. Maximize the copper area around the PGND pins; do not
place thermal relief around them
6. Thermal pad should be soldered to PCB. Place several
via holes under the chip to the ground plane to help heat
dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7566 Application Brief.
Therefore:
1. The thermal pad must be soldered to the PCB.
2. Maximize the PCB area.
3. If a multiple layer PCB is used, thermal vias (13 to 25 mil)
must be placed underneath the thermal pad to connect to
ground plane(s). Do not place thermal reliefs on the vias.
Figure 25 shows a typical connection.
The thermal resistance for this package is as low as 26°C/W
for 2 layer PCB of 0.39" thickness (See Figure 9). The actual
junction temperature can be measured at VTJ pin.
The thermal performance of the IC is heavily dependent on
the layout of the PCB. The user should exercise care during
the design phase to ensure the IC will operate within the
recommended environmental conditions.
COMPONENT SIDE
CONNECTION
GROUND PLANE
CONNECTION
FIGURE 25. PCB LAYOUT - 28-PIN HTSSOP PACKAGE
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FN7102.7
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EL7566
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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