EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Features General Description • Integrated synchronous MOSFETs and current mode controller • 4A continuous output current • Up to 95% efficiency • Internal patented current sense • Cycle-by-cycle current limit • 3V to 3.6V input voltage • Adjustable output voltage 1V to 2.5V • Precision reference • ±0.5% load and line regulation • Adjustable switching frequency to 1MHz • Oscillator synchronization possible • Internal soft-start • Over-voltage protection • Junction temperature indicator • Over-temperature protection • Under-voltage lockout • Multiple supply start-up tracking • Power-good indicator • 20-pin SO (0.300”) package • 28-pin HTSSOP package The EL7563C is an integrated, full-featured synchronous step-down regulator with output voltage adjustable from 1.0V to 2.5V. It is capable of delivering 4A continuous current at up to 95% efficiency. The EL7563C operates at a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented onchip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. The EL7563C features power tracking, which makes the start-up sequencing of multiple converters possible. A junction temperature indicator conveniently monitors the silicon die temperature, saving the designer time on the tedious thermal characterization. The minimal external components and full functionality make this EL7563C ideal for desktop and portable applications. The EL7563C is specified for operation over the full -40°C to +85°C temperature range. Typical Application Diagram (EL7563CM) C5 22Ω Ordering Information Package Tape & Reel Outline # EL7563CM 20-Pin SO (0.300”) - MDP0027 EL7563CM-T13 20-Pin SO (0.300”) 13” MDP0027 EL7563CRE-T7 28-Pin HTSSOP 7” MDP0048 EL7563CRE-T13 28-Pin HTSSOP 13” MDP0048 FB 19 3 COSC PG 18 C3 0.22µF C2 VIN 3.3V D3 5 PSHR VHI 16 6 PGND LX 15 C6 0.22µF 7 PGND LX 14 L1 2.2nF C1 330µF D4 D2 VDRV 17 4 VS 8 VIN PGNDP 13 9 STP PGND 12 10 STN PGND 11 D1 C8 0.22µF C9 0.1µF VOUT C10 2.2nF 4.7µH C7 330µF 2.5V 4A R2 1.54kΩ R1 1kΩ EL7563CM Typical Application Diagrams continued on page 3 Manufactured Under U.S. Patent No. 5,7323,974 Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 2001 Elantec Semiconductor, Inc. October 5, 2001 Part No 2 SGND 390pF R4 DSP, CPU Core, and I/O Supplies Logic/Bus supplies Portable equipment DC:DC converter modules GTL + Bus power supply EN 20 C4 Applications • • • • • 1 CREF 0.1µF EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Absolute Maximum Ratings (T Supply Voltage between VIN or VDD and GND VLX Voltage Input Voltage VHI Voltage A = 25°C) +4.5V VIN +0.3V GND -0.3V, VDD +0.3V GND -0.3V, VLX +6V Storage Temperature Operating Ambient Temperature Operating Junction Temperature -65°C to +150°C -40°C to +85°C +135°C Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. DC Characteristics VDD = VIN = 3.3V, TA = TJ = 25°C, COSC = 1.2nF, unless otherwise specified. Parameter Description VREF Reference Accuracy VREFTC Reference Temperature Coefficient VREFLOAD Reference Load Regulation VRAMP Oscillator Ramp Amplitude IOSC_CHG Oscillator Charge Current Conditions Min Typ Max 1.24 1.26 1.28 50 0<IREF<50µA IOSC_DIS Oscillator Discharge Current 0.1V<VOSC<1.25V IVDD+VDRV VDD+VDRV Supply Current VEN = 4V, FOSC = 120kHz EN = 0 % 1.15 V 200 µA 8 2 V ppm/°C -1 0.1V<VOSC<1.25V Unit 3.5 1 mA 5 mA 1.5 mA IVDD_OFF VDD Standby Current VDD_OFF VDD for Shutdown 2.4 2.65 V VDD_ON VDD for Startup 2.6 2.95 V TOT Over Temperature Threshold 135 THYS Over Temperature Hysteresis 20 ILEAK Internal FET Leakage Current ILMAX Peak Current Limit RDSON FET On Resistance RDSONTC RDSON Tempco ISTP Auxilliary Supply Tracking Positive Input Pull Down Current VSTP = VIN/2 ISTN Auxilliary Supply Tracking Negative Input Pull Up Current VSTN = VIN/2 VPGP Positive Power Good Threshold With respect to target output voltage VPGN Negative Power Good Threshold With respect to target output voltage VPG_HI Power Good Drive High IPG = 1mA 2.7 VPG_LO Power Good Drive Low IPG = -1mA VOVP Over Voltage Protection VFB Output Initial Accuracy ILOAD = 0A VFB_LINE Output Line Regulation VIN = 3.3V, ∆VIN = 10%, ILOAD = 0A 0.5 % VFB_LOAD Output Load Regulation 0.5A< ILOAD <4A 0.5 % VFB_TC Output Temperature Stability -40°C < TA<85°C, ILOAD = 2A ±1 IFB Feedback Input Pull Up Current VFB = 0V 100 VEN_HI EN Input High Level VEN_LO EN Input Low Level IEN Enable Pull Up Current EN = 0, LX = 3.3V (low FET), LX = 0V (high FET) °C °C 10 µA 60 mΩ 5 Wafer level test only A 30 -4 0.2 mΩ/°C 2.5 µA 2.5 4 µA 8 16 % -16 -8 % V 0.5 10 0.977 0.992 1.007 VEN = 0 -4 2 V % 200 2.7 1 V % nA V V -2.5 µA Closed Loop AC Electrical Characteristics VS = VIN = 3.3V, TA = TJ = 25°C, COSC = 1.2nF, unless otherwise specified. Parameter Description Conditions Min Typ Max Unit 100 115 125 kHz FOSC Oscillator Initial Accuracy tSYNC Minimum Oscillator Sync Width 25 ns MSS Soft Start Slope 0.5 V/ms tBRM FET Break Before Make Delay 15 ns tLEB High Side FET Minimum On Time 150 ns DMAX Maximum Duty Cycle 95 % Typical Application Diagrams (Continued) C5 1 CREF EN 28 2 SGND FB 27 3 COSC PG 26 0.1µF C4 22Ω C3 0.22µF 4 VS C1 330µF D4 VDRV 25 C2 D3 5 PSHR VHI 24 6 PGND LX 23 C6 0.22µF 7 PGND LX 22 L1 8 PGND LX 21 4.7µH 9 PGND LX 20 10 VIN LX 19 11 VIN LX 18 12 NC NC 17 2.2nF VIN 3.3V D2 390pF R4 13 STP PGND 16 14 STN PGND 15 D1 C9 0.1µF VOUT C10 2.2nF C7 330µF EL7563CRE For the package information, please refer to the Elantec website at http://www.elantec.com/pages/package_outline.html 3 C8 0.22µF 2.5V 4A R2 1.54kΩ R1 1kΩ EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Pin Descriptions Pin Number Pin Name 1 VREF Bandgap reference bypass capacitor; typically 0.1µF to SGND Pin Function 2 SGND Control circuit negative supply or signal ground 3 COSC Oscillator timing capacitor (see performance curves) 4 VDD Control circuit positive supply; normally connected to VIN through an RC filter 5 VTJ Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND 6 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 7 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 8 VIN Power supply input of the regulator; connected to the drain of the high-side NMOS power FET 9 STP Auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for stand alone operation; 2µA internal pull down current 10 STN Auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand alone operation; 2µA internal pull up current 11 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 12 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 13 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET 14 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage 15 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage 16 VHI Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor 17 VDRV 18 PG Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage 19 FB Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces VOUT to SGND in the event that FB is floating 20 EN Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of converter Positive supply of low-side driver and input voltage for high side boot strap 4 Typical Performance Curves (20-Pin SO Package) *Note: The 28-Pin HTSSOP Package Offers Improved Performance *Efficiency vs I O VIN=3.3V 100 100 VO=2.5V VO=1.8V 90 90 85 85 80 VO=1.2V 75 VO=1V 70 65 0 0.5 1.5 1 VIN=3.3V VIN=3.6V 80 75 70 65 Measured with SO20 package 60 VIN=3V 95 Efficiency (%) Efficiency (%) 95 *Efficiency vs I O VO=2.5V 2 2.5 3 3.5 60 4 Measured with SO20 package 0 0.5 1 1.5 *Converter Total Power Loss vs IO VIN=3.3V 1.8 1.4 VO=1.8V 1 0.8 VO=1V 0.6 0.4 VO=2.5V 0 0 0.5 1 1.5 2 2.5 3 3.5 VIN=3.3V 2.49 2.485 VIN=3V 2.48 2.475 2.465 0.5 4 1 1.5 Line Regulation VO=3.5V 2.5 3 3.5 4 VREF vs Junction Temperature 1.27 1.268 IO=0.5A 2.495 2 Load Current IO (A) 2.5 1.266 VREF (V) 2.49 VO (V) 4 VIN=3.6V Output Current IO (A) IO=2A 2.485 2.48 1.264 1.262 1.26 2.475 IO=4A 2.47 2.465 3.5 2.47 0.2 2.505 3 2.495 VO=1.2V 1.2 2.5 Load Regulation VO=2.5V 2.5 Output Voltage (V) Power Loss (W) 2.505 Measured with SO20 package 1.6 2 Load Current IO (A) Load Current IO (A) 3 3.1 1.258 3.2 3.3 3.4 3.5 1.256 -50 3.6 VIN (V) -10 30 70 Junction Temperature (°C) 5 110 150 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Monolithic 4 Amp DC:DC Step-down Regulator Typical Performance Curves *Note: The 28-Pin HTSSOP Package Offers Improved Performance Switching Frequency vs COSC VTJ vs Junction Temperature 1.5 1000 900 800 1.3 600 VPSHR FS (KHz) 700 500 1.1 400 300 200 100 100 200 300 400 500 600 700 800 0.9 900 1000 50 0 25 50 Switching Waveforms VIN=3.3V, VO=1.8V, I O=4A *θJA vs Copper Area SO20 Package 46 ∆VIN VLX with no airflow 42 iL 38 ∆VO with 100 LFPM airflow 34 30 Test Condition: Chip in the center of copper area 1 1.5 2 2.5 75 100 Junction Temperature (°C) COSC (pF) Thermal Resistance (°C/W) EL7563C EL7563C 1 oz. copper PCB used 3 3.5 4 PCB Copper Heat-Sinking Area (in2) Transient Response VIN=3.3V, VO=1.8V, IO=0.2A-4A Power-Up VIN=3.3V, VO=1.8V, I O=0.2A IO ∆VO 6 125 150 Typical Performance Curves Power-Down VIN=3.3V, VO=1.8V, IO=4A Enable VIN=3.3V, VO=1.8V at 4A VIN EN VO VO Disable VIN=3.3V, VO=1.8V at 4A Short-Circuit Protection VIN=3.3V, VO=1.8V, IO=4A to short EN IO VO VO 7 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Block Diagram 0.1µF 390pF VREF VTJ Junction Temperature Voltage Reference COSC D2 Oscillator 0.22µF 2.2nF VHI Controller Supply 22Ω 3.3V VDD 0.22µF Power FET 0.22µF Power FET 330µF PGND Power Tracking Current Sense VREF SGND PG + FB 8 D1 0.1µF 4.7µH Drivers EN STN D3 VIN PWM Controller STP D4 VDRV 1.58kΩ 1kΩ 2.2nF VOUT (2.5V, 4A) Applications Information Circuit Description output, the relatively large LC time constant found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter and can react more quickly to changes in line and load conditions. This feed-forward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the current-feedback to voltage-feedback ratio the overall loop response will approach a onepole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. General The EL7563C is a fixed frequency, current mode controlled DC:DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all the active circuitry required to implement a cost effective, user-programmable 4A synchronous step-down regulator suitable for use in DSP core power supplies. By combining fused-lead packaging technology with an efficient synchronous switching architecture, high power output (10W) can be realized without the use of discrete external heat sinks. Theory of Operation The EL7563C is composed of 7 major blocks: The heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. The slope compensation is fixed internally and optimized for 500mA inductor ripple current. The power tracking will not contribute any input to the comparator steady-state operation. Current feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on. The comparator inputs are gated off for a minimum period of time of about 150ns (LEB) after the high-side switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. If the inductor current exceeds the maximum current limit (ILMAX) a secondary overcurrent comparator will terminate the high-side switch on time. If ILMAX has not been reached, the feedback voltage FB derived from the regulator output voltage VOUT is then compared to the internal feedback reference voltage. The resultant error voltage is summed with the current feedback and slope compensation ramp. The 1. PWM Controller 2. NMOS Power FETs and Drive Circuitry 3. Bandgap Reference 4. Oscillator 5. Temperature Sensor 6. Power Good and Power On Reset 7. Auxiliary Supply Tracking PWM Controller The EL7563C regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. Unlike pure voltagemode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-averaged of the modulator 9 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator tor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1µF is recommended. high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-before-make delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic control signal. Oscillator The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. Output Voltage Setting In general: R 2 V OUT = 0.992V × 1 + ------ R 1 When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommodate component and temperature variations. Figure 1 shows a typical connection. However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loop-gain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating. NMOS Power FETs and Drive Circuitry 100pF BAT54S External Oscillator The EL7563C integrates low on-resistance (30mΩ) NMOS FETs to achieve high efficiency at 4A. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 6V with external chargepump. At the beginning of the next cycle the high-side switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 9V, for VIN=3.3V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.22µF for CVHI is recommended. 390pF 1 20 2 19 3 18 5 16 6 EL7563C 15 7 14 8 13 9 12 10 11 Figure 1. Oscillator Synchronization Junction Temperature Sensor Reference An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135°C and 115°C respectively. A 1.5% temperature compensated bandgap reference is integrated in the EL7563C. The external VREF capaci- The VTJ pin is an accurate indication of the internal silicon junction temperature (see performance curve.) The 10 junction temperature TJ (°C) can be deducted from the following relation: comparator. A logic high on the PG output indicates that the regulated output voltage is within about +10% of the nominal selected output voltage. 1.2 – VTJ T J = 75 + -----------------------0.00384 Power Tracking The power tracking pins STP and STN are the inputs to a comparator, whose HI output forces the PWM controller to skip switching cycle. Where VTJ is the voltage at VTJ pin in volts. Power Good and Power On Reset During power up the output regulator will be disabled until VIN reaches a value of approximately 2.9V. About 300mV hysteresis is present to eliminate noise-induced oscillations. 1. Linear Tracking In this application, it is always the case that the lower voltage supply VC tracks the higher output supply VP. Please see Figure 2 below. Under-voltage and over-voltage conditions on the regulator output are detected through an internal window 1 20 2 19 6 15 7 EL7563C 8 VC 14 13 VP 9 10 + - 12 11 1 20 2 19 6 15 7 EL7563C 8 9 10 VOUT TIME VP 14 13 + - VC 12 11 Figure 2. Linear Power Tracking 11 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator 2. Offset Tracking However, due to the superimpose of VC and VIN, the choice of RA and RB are restricted by the following relationship: The intended start-up sequence is shown in Figure 3a. In this configuration, VC will not start until VP reaches a preset value of: RA RB V P + 0.5 < ------------------- × V IN + -------------------- × V C RA + RB RA + R B RB ------------------- × V IN RA + RB Where 0.5 is for noise immunity. See Figure 3 below. RB 1 20 2 19 6 15 VIN 7 RA 8 9 10 EL7563C VC 14 VP 13 STP STN + - VOUT 12 VC 11 TIME 1 20 2 19 6 15 EL7563C 7 8 9 10 VP 14 13 STP STN + - 12 11 Figure 3. Offset Power Tracking 12 The second way of offset tracking is to use the EN and Power Good pins, as shown in Figure 4. In this configuration, VP does not have to be larger than VC. 1 EN 20 2 19 3 PG 18 5 16 6 EL7563C 15 7 14 8 13 9 12 10 11 VC VP VC 1 EN 20 2 19 3 PG 18 5 16 6 EL7563C 15 7 14 8 13 9 12 10 11 TIME VP Figure 4. Offset Tracking 13 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator 3. External Soft Start An external soft start can be combined with auxilliary supply tracking to provide desired soft start other than internally preset soft start (Figure 5). The appropriate start-up time is: VO t s = R × C × --------V IN 1 20 2 19 6 15 VIN EL7563C 7 R 8 9 10 14 13 STP STN + - 12 11 C Figure 5. External Soft Start 14 VOUT 4. Start-up Delay A capacitor can be added to the EN pin to delay the converter start-up (Figure 6) by utilizing the pull-up current. The delay time is approximately: t d ( ms ) = 1200 × C ( µF ) 1 20 2 19 6 15 C EL7563C 7 VOUT 14 VIN 8 9 10 13 STP STN + - VO 12 td 11 TIME Figure 6. Start-up Delay 15 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator Thermal Management Layout Considerations The EL7563C utilizes “fused lead” packaging technology in conjunction with the system board layout to achieve a lower thermal resistance than typically found in standard SO20 packages. By fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path is created to the outside of the package. This conductive heat path MUST then be connected to a heat sinking area on the PCB in order to dissipate heat out and away from the device. The conductive paths for the EL7563CM package are the fused leads: # 6, 7, 11, 12, and 13. If a sufficient amount of PCB metal area is connected to the fused package leads, a junction-to-ambient resistance of 43°C/W can be achieved (compared to 85°C/W for a standard SO20 package). The general relationship between PCB heat-sinking metal area and the thermal resistance for this package is shown in the Performance Curves section of this data sheet. It can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 43°C/W without any airflow, and 33°C/W with 100 LFPM airflow. Additional information can be found in Application Note #8 (Measuring the Thermal Resistance of Power SurfaceMount Packages). For a thermal shutdown die junction temperature of 135°C, and power dissipation of 1.5W, the ambient temperature can be as high as 70°C without airflow. With 100 LFPM airflow, the ambient temperature can be extended to 85°C. The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground (---) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to the FB pin is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on these principles. Please refer to the EL7563C Application Brief for the layout. The EL7563CRE utilizes the 28-pin HTSSOP package. The majority if heat is dissipated through the heat pad exposed at the bottom of the package. Therefore, the heat pad needs to be soldered to the PCB. The thermal resistance for this package is better than that of the SO20. Actual test results are available from Elantec Applications staff. The actual junction temperature can be measured at VTJ pin. Since the thermal performance of the IC is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the IC will operate under the worst-case environmental conditions. 16 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. For the latest revision, please refer to the Elantec website at http://www.elantec.com/pages/package_outline.html 17 EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator EL7563C EL7563C Monolithic 4 Amp DC:DC Step-down Regulator General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. October 5, 2001 WARNING - Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec Semiconductor, Inc. 675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323 (888) ELANTEC Fax: (408) 945-9305 European Office: +44-118-977-6020 Japan Technical Center: +81-45-682-5820 18 Printed in U.S.A.