LSI for MPEG MN673794 1. Overview This IC is used to process a variety of items including the following ones: NTSC/PAL signal (Y/C and composite video) I/O, 3D Y/C separation, TBC, DD conversion, frame sync, sync/clock generation, Rec 656 I/O. Features ▪ Analog input block Composite video/Component Y input (10 bits at 27.0 MHz) Component C input (10 bits at 27.0 MHz) ▪ Analog control block AGC (Auto Gain Control), clamp control, ACC (Auto Color Control) ▪ Digital I/O block Digital video I/O (ITU-R Rec 656: Y/Cr/Cb multiple, 8 bits at 27 MHz) Digital video input clock must be synchronized with the system clock of 27 MHz. ▪ Signal processing block 3D Y/C separation (image movement adaptive processing: NTSC), 2D Y/C separation (PAL) TBC (Time Base Corrector) processing (velocity error correction/jitter correction) Frame sync processing (See Note.) NR processing (Y/C recursive NR) Y/C separation is performed only in two dimensions (due to memory sharing) when the NR function is in use. ▪ Copyright VBLK detection Macrovision (AGC pulse and color stripe) detection VBID detection Closed caption detection WSS detection Note: This IC uses a 27-MHz fixed clock. Therefore, input signals into the IC are not synchronized with output signals from the IC. Therefore, a frame-skip or frame-hold occurs to standard and nonstandard signals, the frequency of occurrence of which varies with the difference in frame frequency between input signals and the 27-MHz fixed clock. If the user does not want the occurrence of any frame-skip or frame-hold to standard signals, externally generate 27-MHz clock pulses synchronized with the frames of the input signals, and input the clock pulses into the IC. A frame-skip refers to loss of the image in a single frame. A frame-hold refers to the duplicated output of the image in the previous frame. *1 Publication date: January 2003 SDF00032BEM 1 MN673794 2. Specifications 2.1 Electrical Characteristics (1) Processor 0.25-µm, four-layer aluminum DRAM-embedded processor (2) Maximum operating frequency 27.0 MHz (3) Operating supply voltage 3.0 V to 3.6 V (Analog power supply) 3.0 V to 3.6 V (Digital I/O power supply 1) 1.65 V to 1.95 V (Internal digital power supply) 2.3 V to 2.7 V (Internal DRAM power supply) (4) Ambient temperature -20°C to +80°C (5) Package 208-pin QFP with 28-mm square (0.5-mm pitch) (Package code No. LQFP208-P-2828) SDF00032BEM 2 MN673794 2.2 Pin Descriptions Table 2.2 shows the explanation of the pins of the IC. Table 2.2 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Pin name CLK18O2 VDD3 CLK45I VSS VDDI DSF7 DSF6 VSS DSF5 DSF4 VDD2 DSF3 DSF2 VSS DSF1 DSF0 VDD2 CASHD CASVD VSS CLK188 CLK450 VDD2 CLK18O1 VSS AVSS1 TPLL AVDD1 AVSS2 VREFCK IREFCK COMPCK CK45O AVDD2 AVSS3 VREFC IREFC COMPC TESTI AVDD3 AVSS4 VREFY IREFY COMPY TESTK AVDD4 AGCO AVSS5 CLPOS 50 VREFMA 51 AVDD5 52 ACCO I/O O Voltage Type 3.3 V CMOS Power supply 3.3 V Crystal interface I GND Power supply 1.8 V I/O 3.3 V CMOS-100 kΩ PD I/O 3.3 V CMOS-100 kΩ PD GND I/O 3.3 V CMOS-100 kΩ PD I/O 3.3 V CMOS-100 kΩ PD Power supply 3.3 V I/O 3.3 V CMOS-100 kΩ PD I/O 3.3 V CMOS-100 kΩ PD GND I/O 3.3 V CMOS-100 kΩ PD I/O 3.3 V CMOS-100 kΩ PD Power supply 3.3 V O 3.3 V CMOS O 3.3 V CMOS GND O 3.3 V CMOS O 3.3 V CMOS Power supply 3.3 V O 3.3 V CMOS GND GND Analog I/O Power supply 3.3 V GND 3.3 V Analog I Analog I Analog I Analog O Power supply 3.3 V GND 3.3 V Analog I Analog I I Analog Analog O Power supply 3.3 V GND Analog I Analog I Analog I O Analog Power supply 3.3 V Analog O GND O Analog I - Power supply 3.3 V O - Analog Analog Pin Descriptions (1/4) Drive Function 4 mA Test output Digital I/O (3.3 V) use Test input (VSS) Digital use Internal digital use 4 mA Test I/O (open or VSS) 4 mA Test I/O (open or VSS) Digital use 4 mA Test I/O (open or VSS) 4 mA Test I/O (open or VSS) Digital I/O (3.3 V) use 4 mA Test I/O (open or VSS) 4 mA Test I/O (open or VSS) Digital use 4 mA Test I/O (open or VSS) 4 mA Test I/O (open or VSS) Digital I/O (3.3 V) use 2 mA Test output 2 mA Test output Digital use 2 mA Clock 2 mA Clock Digital I/O (3.3 V) use 4 mA Test output Digital use Analog use Test use Analog use Analog use Test use (AVSS) Test use (AVSS) Test use (AVDD) Test output D/A (CLK) use Analog use Test use (AVSS) Test use (AVSS) Test use (AVDD) Test output Analog use Analog use Test use (AVSS) Test use (AVSS) Test use (AVDD) Test output Analog use AGC control output Voltage dividing resistor DAC (ACC, CLAMP, and AGC) use Clamp control output (for sync tip clamp use) Reference voltage input for voltage dividing resistor DAC use (Capacitance coupling to AVSS) Voltage dividing resistor DAC (ACC, CLAMP, and AGC) use ACC control output SDF00032BEM Clock BST - - YES YES - YES YES - YES YES - YES YES - YES YES 1 MHz - - - - - 1 MHz - 1 MHz 3 MN673794 Table 2.2 Pin No. 53 54 55 56 Pin name AVDD6 CIN AVSS6 VREFLC I/O Power supply Type Voltage 3.3 V Analog Drive - I GND I - 57 VREFMLC I - 58 VREFMC I - Analog - 59 VREFHMC I - Analog - I GND - Analog 60 61 62 63 64 65 66 VREFHC AVSS7 AVDD7 AVDD8 VIDEO AVSS8 VREFLY Analog Analog - Analog I GND I - Analog Analog - 67 VREFMLY I - Analog - 68 VREFMY I - Analog - 69 VREFHMY I - Analog - I GND - Analog Power supply 3.3 V GND O - - 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VREFHY AVSS9 AVDD9 VSS ANACLK VDD3 GCP TESTIO9 TESTIO8 VSS TESTIO7 TESTIO6 VDDI TESTIO5 TESTIO4 VSS VDDDRAM0 VSSDRAM0 TESTIO3 TESTIO2 VDD3 TESTIO1 TESTIO0 VSS TCK TDO VDDI TDI TRST TMS VSS TEST5 TEST4 TEST3 TEST2 Power supply Power supply - 3.3 V Analog 3.3 V 3.3 V Power supply 3.3 V O 3.3 V I/O 3.3 V I/O 3.3 V GND I/O 3.3 V I/O 3.3 V Power supply 1.8 V I/O 3.3 V I/O 3.3 V GND Power supply 2.5 V GND I/O 3.3 V I/O 3.3 V Power supply 3.3 V I/O 3.3 V I/O 3.3 V GND I 3.3 V O 3.3 V Power supply 1.8 V I 3.3 V I 3.3 V I 3.3 V GND I 3.3 V I 3.3 V I 3.3 V I 3.3 V - - 2 mA CMOS - - CMOS CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD 3-state CMOS CMOS-100 kΩ PU CMOS-100 kΩ PU CMOS-100 kΩ PU CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD 2 mA 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 2 mA - Pin Descriptions (2/4) Function A/D (C) use C input (analog) A/D (C) use A/D (C) reference voltage low-level input A/D (C) intermediate reference potential input (Capacitance coupling to AVSS) A/D (C) intermediate reference potential input (Capacitance coupling to AVSS) A/D (C) intermediate reference potential input (Capacitance coupling to AVSS) A/D (C) reference voltage high-level input A/D (C) use A/D (C) use A/D (Y and composite) use Composite video input (analog) A/D (Y and composite) use A/D (Y and composite) reference voltage low-level input A/D (Y and composite) intermediate reference potential input (Capacitance coupling to AVSS) A/D (Y and composite) intermediate reference potential input (Capacitance coupling to AVSS) A/D (Y and composite) intermediate reference potential input (Capacitance coupling to AVSS) A/D (Y and composite) reference voltage high-level input A/D (Y and composite) use A/D (Y and composite) use Digital use 6.75-MHz output Digital I/O (3.3 V) use Clamp pulse (sync chip) output Test I/O (MSB) (open or VSS) Test I/O (open or VSS) Digital use Test I/O (open or VSS) Test I/O (open or VSS) Internal digital use Test I/O (open or VSS) Test I/O (open or VSS) Digital use DRAM (5 Mbits) use Digital use Test I/O (open or VSS) Test I/O (open or VSS) Digital I/O (3.3 V) use Test I/O (open or VSS) Test I/O (LSB) (open or VSS) Digital use Boundary scan clock input Boundary scan data output Internal digital use Boundary scan data input Boundary scan reset input (VSS or RST when not used） Boundary scan mode input Digital use Test mode (MSB) (open or VSS) Test mode (open or VSS) Test mode (open or VSS) Test mode (open or VSS) Clock BST - - - - - - - - - - - - - - - - - - 27 MHz 27 MHz 27 MHz - When the boundary scan function is not used, set the TRST pin (pin 98) to reset input or VSS. *2 SDF00032BEM 4 MN673794 Table 2.2 Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Pin name TEST1 TEST0 VDDI VSS MINTC1 MINTIN1 MINTEST VDD3 PDRAM0 PDRAM1 VSSDRAM1 VDDDRAM1 NTDRAM VSS VDDI CLK27I VSS 122 R656IN7 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 R656IN6 VDD3 R656IN5 R656IN4 VSS VDDDRAM2 VSSDRAM2 R656IN3 R656IN2 VDD3 R656IN1 R656IN0 VSS CLK27O VDDI R656OUT7 R656OUT6 VSS R656OUT5 R656OUT4 VDD3 R656OUT3 R656OUT2 VSS R656OUT1 R656OUT0 VDDI VSS HD VD VDD3 APCE VSS CSYNCO I/O I I Voltage Type 3.3 V CMOS-100 kΩ PD 3.3 V CMOS-100 kΩ PD Power supply 1.8 V GND I 3.3 V CMOS I 3.3 V CMOS I 3.3 V CMOS-30 kΩ PD Power supply 3.3 V I 3.3 V CMOS-100 kΩ PD I 3.3 V CMOS-100 kΩ PD GND Power supply 2.5 V I 3.3 V CMOS-100 kΩ PD GND Power supply 1.8 V I 3.3 V CMOS GND Drive - I 3.3 V CMOS-100 kΩ PD - I 3.3 V CMOS-100 kΩ PD 3.3 V 3.3 V CMOS-100 kΩ PD 3.3 V CMOS-100 kΩ PD - Power supply I I GND - Power supply 2.5 V GND I I - 3.3 V 3.3 V Power supply 3.3 V I 3.3 V I 3.3 V GND O 3.3 V Power supply 1.8 V O 3.3 V O 3.3 V GND O 3.3 V O 3.3 V Power supply 3.3 V O 3.3 V O 3.3 V GND O 3.3 V O 3.3 V Power supply 1.8 V GND I/O 3.3 V I/O 3.3 V Power supply 3.3 V O 3.3 V GND O 3.3 V CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS-100 kΩ PD CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS-100 kΩ PU CMOS-100 kΩ PU 3-state CMOS CMOS 4 mA - 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 4 mA 4 mA - 2 mA - 2 mA Pin Descriptions (3/4) Function Test mode (open or VSS) Test mode (LSB) (open or VSS) Internal digital use Digital use Test input （VSS) Test input （VSS) Test input （open or VSS) Digital I/O (3.3 V) use DRAM test input (open or VSS) DRAM test input (open or VSS) Digital use DRAM (5 Mbits) use DRAM test input (open or VSS) Digital use Internal digital use 27-MHz clock for Rec 656 input (VSS when not used) Digital use Digital video (Rec 656) input (MSB) (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital I/O (3.3 V) use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital use DRAM (7 Mbits) use Digital use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital I/O (3.3 V) use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (LSB) (open or VSS when not used) Digital use 27-MHz clock output Internal digital use Digital video (Rec 656) output (MSB) Digital video (Rec 656) output Digital use Digital video (Rec 656) output Digital video (Rec 656) output Digital I/O (3.3 V) use Digital video (Rec 656) output Digital video (Rec 656) output Digital use Digital video (Rec 656) output Digital video (Rec 656) output (LSB) Internal digital use Digital use Test I/O (open or VDD3) Test I/O (open or VDD3) Digital I/O (3.3 V) use Phase error output Digital use Composite sync detection output SDF00032BEM Clock BST - - 27 MHz YES 27 MHz YES 27 MHz - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES 27 MHz - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES - - 27 MHz 27 MHz YES YES - - 27 MHz YES 27 MHz 5 MN673794 Table 2.2 Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 Pin name MICONRWW VDD3 MICONRWR VSSDRAM3 VDDDRAM3 RST VSS CLK27XI CLK27XO VDDI VSS MAD6 MAD5 MAD4 VDD3 MAD3 MAD2 MAD1 MAD0 VSS MDA15 MDA14 VDDI MDA13 MDA12 VSS MDA11 MDA10 VDD3 MDA9 MDA8 VSS MDA7 MDA6 VDDI MDA5 MDA4 VSS MDA3 MDA2 VDD3 MDA1 MDA0 VSS MCSALE MNRE MNWENBW MICOMSEL 205 NC3 206 VDDI 207 INF 208 FRP I/O O Voltage Pin Descriptions (4/4) Drive Function 2 mA Microcontroller interrupt （write） sync signal output Digital I/O (3.3 V) use 2 mA Microcontroller interrupt （read) sync signal output Digital use DRAM (7 Mbits) use Reset input Digital use 27-MHz clock (crystal) input 27-MHz clock (crystal) output Internal digital use Digital use 4 mA Microcontroller interface data/address input （MSB） 4 mA Microcontroller interface data/address input 4 mA Microcontroller interface data/address input Digital I/O (3.3 V) use 4 mA Microcontroller interface data/address input 4 mA Microcontroller interface data/address input 4 mA Microcontroller interface data/address input 4 mA Microcontroller interface data/address input （LSB） Digital use 8 mA Microcontroller interface data/address I/O （MSB） 8 mA Microcontroller interface data/address I/O Internal digital use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Digital use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Digital I/O (3.3 V) use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Digital use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Internal digital use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Digital use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O Digital I/O (3.3 V) use 8 mA Microcontroller interface data/address I/O 8 mA Microcontroller interface data/address I/O (LSB) Digital use Microcontroller interface chip select input Microcontroller interface read input Microcontroller interface write input Microcontroller interface selection input Microcontroller interface mode selection input (Normal mode: Schmitt CMOS VSS) Internal digital use CMOS-100 kΩ PD Test input (open or VSS) CMOS 4 mA Test output Type 3.3 V CMOS Power supply 3.3 V O 3.3 V CMOS GND Power supply 2.5 V I 3.3 V CMOS-100 kΩ PU GND I Crystal interface O Crystal interface Power supply 1.8 V GND I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS Power supply 3.3 V I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 1.8 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 3.3 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 1.8 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 3.3 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS 3.3 V Schmitt CMOS I/O I/O Power supply I O 3.3 V 1.8 V 3.3 V 3.3 V SDF00032BEM Clock 27 MHz - 27 MHz - 27 MHz 27 MHz - BST YES YES - YES YES YES - YES YES YES YES - YES YES - YES YES - YES YES - YES YES - YES YES - YES YES - YES YES - YES YES - YES YES YES YES - - - YES YES - 6 MN673794 2.3 Pin Assignment M M I N M C W C O V E MS MM M F I D N N N V DD A S R N D C B R S AA L P F I 3 EWE S 0 1 E L 207 205 CLK18O2 VDD3 CLK45I VSS VDDI DSF7 DSF6 VSS DSF5 DSF4 VDD2 DSF3 DSF2 VSS DSF1 DSF0 VDD2 CASHD CASVD VSS CLK188 CLK450 VDD2 CLK18O1 VSS AVSS1 TPLL AVDD1 AVSS1 VREFCK IREFCK COMPCK CK45O AVDD1 AVSS1 VREFC IREFC COMPC TESTI AVDD1 AVSS1 VREFY IREFY COMPY TESTK AVDD1 AGCO AVSS1 CLPOS VREFMA AVDD1 ACCO 208 206 203 204 201 202 199 200 V MM D DD V D AA S 3 23S 197 198 195 196 M MV M M M D DD D D V D A AD A A S A 45 I 6 7S8 193 194 191 192 189 190 187 C L K MM V 2 AA VD 7 DD S D X 56 S I O MM M M M M M V D D D D V D D MM M M V M D D A A V A A DA A V A A A A DA A D 1 1 S 1 1 D 1 1 S DD D D DD 9 3 01 S2 3 I 45 S01 2 3 34 185 188 186 183 184 181 182 179 180 177 178 175 176 173 171 174 172 169 170 167 168 165 166 M M C V VI I L D SC C K D SO O V 2 D DN N 7 V R R R DR R X S S A A DW W I S T M M 3W R 163 164 161 162 159 160 157 158 1 2 156 155 3 154 4 5 153 152 6 151 7 8 150 149 9 148 10 147 11 146 145 12 13 14 144 143 142 15 16 141 140 17 18 139 19 20 138 137 21 136 22 23 135 134 133 24 25 MN673794 26 27 28 132 131 29 130 129 128 30 127 31 32 126 125 33 34 35 124 123 122 36 121 37 38 120 119 39 118 40 117 116 41 115 42 43 44 114 113 45 112 46 111 110 47 109 48 49 108 107 50 106 51 52 105 54 53 55 56 58 57 60 59 A CA V V V V V V I V R R R RR D NS E E E E E D SF FFFF 1 1 L MMH H C L C MC C C 62 61 64 66 63 65 A AA V VV S DD S DD 1 11 VA IV DS ES O1 68 67 70 69 72 71 74 73 76 75 78 77 80 79 82 81 84 83 86 85 88 87 90 89 92 91 94 93 96 95 98 97 100 99 101 V V V VV AA VA V G T T V T T V T T VVV T T V T T V T T V T T T V R R R R R V V S N D C E E S E E D E E S D S E E D E E S CD D D R M S E E E E E S D S A D P S S S S S DS S S DS S S DS S S K O D I S S S F F F F F S D C 3 T T T T I T T DD T T 3 T T I T L M MH H 1 1 L I I I I RR I I I I I I Y L YM Y K OO O O O O A A O O O O Y Y 9 8 7 6 5 4 MM 3 2 1 0 Figure 2.3 102 CSYNCO VSS APCE VDD3 VD HD VSS VDDI R656OUT0 R656OUT1 VSS R656OUT2 R656OUT3 VDD3 R656OUT4 R656OUT5 VSS R656OUT6 R656OUT7 VDDI CLK27O VSS R656IN0 R656IN1 VDD3 R656IN2 R656IN3 VSSDRAM VDDDRAM VSS R656IN4 R656IN5 VDD3 R656IN6 R656IN7 VSS CLK27I VDDI VSS NTDRAM VDDDRAM VSSDRAM PDRAM1 PDRAM0 VDD3 MINTEST MINTIN1 MINTC1 VSS VDDI TEST0 TEST1 104 103 T TTT E EEE S SSS T TTT 5 432 Pin Assignment SDF00032BEM 7 SDF00032BEM CIN 27 MHz 10 bits A/D D/A D/A D/A AGCO ACCO 27 MHz 10 bits A/D 8 CLPOS APCE CSYNCO GCP VIDEO R656IN 7～0 CLK27I 6 MHz LPF 制御 Analogﾞ ｱﾅﾛｸ Control 6 MHz LPF Conversion DD Separation Sync Conversion DD Input processing Rec.656 Copyright Detection YC 分離 Separation 2D/3D ＳＥＬ DRAM (5(5Mbit) Mbits) S Chroma E decode L APC ﾗｲﾝ Line TBC / / DD DD Conversion 変換 DRAM (7(7Mbit) Mbits) Figure 2.4 Block Diagram ACC Microcontroller clamp Digital Analog input processing S Frame E sync L RST S Noise E ReducL tion MICONRWW NC3 MICONRWR MICOMSEL Microcontroller ﾏｲｺﾝ interface I/F S Rec.656 E output L processing CLK27XO Clock generation CLK27XI MDA15～0 MAD6～0 MNWENBW MNRE MCSALE R656OUT 7～0 ANACLK CLK27O MN673794 2.4 Block Diagram 8 MN673794 3. Microcontroller Interface (1) Overview Data is written to and read from the internal registers of the IC through microcontroller interfaces. A microcontroller to be connected to the IC has two types of interfaces in consideration of two cases, where the address, data, and control line are synchronous with the system clock of the IC and where they are not synchronous with the system clock. The two types of interfaces are available in both cases. One of them is an address/data multiple bus interface, which enables the data bus to be overlapped with addresses, and the other is an interface for address/data bus separation. These cases and types are selectable with the external pins of the IC as shown in table 3.1. Table 3.1 Pin setting (Pin number) No. 204 (MICOMSEL) No. 205 (NC3) 0 0 1 1 0 1 0 1 Protocol Settings for Microcontroller Interface Protocol Sync/Async with Separation/Multiple system clock address data bus Async Separation Sync Separation Async Multiple Sync Multiple (2) Microcontroller Interface Signals Table 3.2 shows the respective microcontroller interface signals and corresponding pins that appear in the microcontroller timing chart. Table 3.2 Signal Address Data CS (chip select) WE (write enable) RE (read enable) Interface Signals and Corresponding Pins Interface Interface (separation/multiple) (separation/multiple) signals not synchronous signals synchronous with with system clock system clock MAD MDA MCSALE MNWENBW MNRE SDF00032BEM Adress Data CS WE RE 9 MN673794 (3) Timing [a] System Clock Async/Separation Bus Interface Figure 3.3 (a) is the timing chart of the interface. READ cycle (trdc) WRITE cycle (twrc) tawrs MAD[6:0] Valid tawrh Valid tdwrh tdwrs MDA[15:0] Write Data Read Data trdout twrcs twrw w cs MCSALE trdw MNRE twrw MNWENBW [ns] Timing Min Max 148 – – 30 trdc Read cycle trdout Read data valid twrc Write cycle 148 – trdw Read pulse (MNRE) width 74 – twrw Write pulse (MNWENBW) width 74 – twrcs_w CS enable after WE active 10 – twrw_cs WE negate after CS disable 10 – tdwrs Write data setup twrw – tdwrh tawrs tawrh Write data hold Write address setup Write address hold 0 – twrw – – 10 Figure 3.3 (a) Microcontroller Interface Timing 1 * Note) • When the signal timing changes to the read cycle from the write cycle, data reading must start at least 50 ns after the write cycle completes. • In the case of continuous data writing, a minimum of 148 ns is required between the falling edge of the present write enable (MNWENBW) and that of the next write enable. SDF00032BEM 10 MN673794 [b] System Clock Async/Multiple Bus Interface Figure 3.3 (b) is the timing chart of the interface. READ cycle (trdc) WRITE cycle (twrc) MAD[6:0] twrs trdout MDA[15:0] Read Data Address Address twrh Write Data Valid MCSALE trdw MNRE twrw MNWENBW [ns] Timing trdc trdout twrc trdw twrw twrs twrh Min 148 – 148 74 74 twrw 10 Read cycle Read data valid Write cycle Read pulse (MNRE) width Write pulse (MNWENBW) width Write data setup Write data hold Figure 3-3 (b) Max – 30 – – – – – Microcontroller Interface Timing 2 SDF00032BEM 11 MN673794 [c] System Clock Sync/Separation Bus Interface Figure 3.3 (c) is the timing chart of the interface. CLK (I) t cyc Address (I) Address Valid CS (I) Write timing WE (I) Data Valid Data (I) t WDS t WDH Read timing RE (I) Data (O) Data Valid t RREDT t RCSDT Parameter Symbol Min Typ 27-MHz clock cycle tCYC 37 Write data setup tCYC tWDS （based on rising edge of write enable WE） Write data hold tCYC tWDH (based on rising edge of write enable WE) Read data delay 0 tRREDT (based on falling edge of read enable RE) Read data hold 0 tRCSDT (based on rising edge of chip select CS) Figure 3.3 (c) Microcontroller Interface Timing 3 Max Unit ns ns ns tCYC ns ns • Address, Data, CS, WE, and RE input signals are input, not synchronizing with the CLK clock signal. • The CS must be disabled (i.e., set to high) whenever data is read from or written to any address. SDF00032BEM 12 MN673794 [d] System Clock Async/Multiple Bus Interface Figure 3.4 (d) is the timing chart of the interface. CLK (I) t cyc CS (I) Write timing WE (I) Address (I) /Data (I) Read timing Address Valid t WAS Data Valid t WAH t WDS t WDH RE (I) Address (I) /Data (O) Address Valid t RAS Data Valid t RAH t RREDT Parameter Symbol Min Typ 27-MHz clock cycle tCYC 37 Write address setup tCYC tWAS （based on falling edge of address latch enable ALE） Write address hold tCYC tWAH （based on falling edge of address latch enable ALE） Read address setup tCYC tRAS （based on falling edge of address latch enable ALE） Read address hold tCYC tRAH （based on falling edge of address latch enable ALE） Write data setup tCYC tWDS （based on rising edge of write enable WE） Write data hold tCYC tWDH (based on rising edge of write enable WE) Read data delay 0 tRREDT (based on falling edge of read enable RE) Read data hold 0 tRCSDT (based on rising edge of chip select CS) Figure 3.3 (d) Microcontroller Interface Timing 4 t RCSDT Max Unit ns ns ns ns ns ns ns tCYC ns ns * Address, Data, CS, WE, and RE input signals are input, not synchronizing with the CLK clock signal. SDF00032BEM 13 MN673794 (4) Microcontroller Registers [a] Read/Write Addresses 0040h to 0046h, 0048h, and 004Ah are read-only registers. Data can be written to and read from addresses with register marks if they are not read-only registers. Although data can be written to addresses with no register marks, the accuracy of data read from such addresses is not guaranteed. [b] Special Registers Addresses 0043h and 0044h are registers, the functions of which vary with the signal mode settings for the registers. • NTSC mode: Register for VBID detection • PAL mode: Register for WSS detection (The register table in WSS mode is different.) [c] Video Signal Mode Settings A video signal mode is set with three bits. These bits have the following meanings. Bit Meaning 0 1 [2] Line 525-line mode 625-line mode [1] Processing frequency (4fsc) 14 MHz line 17 MHz line [0] Phase Alt No Yes Make the following settings for the respective signal modes. [2:0] 000 001 010 011 100 101 110 111 System NTSC PAL-M NTSC443 (PAL-60) – PAL-N – PAL Make sigmod 0000h [2:0] settings for the signal modes of the analog input processing block, frame sync processing block, Rec 656 input processing block, and Rec 656 output processing block. SDF00032BEM 14 SDF00032BEM Sync 6 MHz control Analog 10 bits 27 MHz DD conversion separation LPF D/A ACCO LPF 6 MHz A/D D/A AGCO CIN D/A 27 MHz 10 bits A/D 8 CLPOS GCP CSYNCO APCE VIDEO CLK27I 7 ～0 R656IN conversion DD tion detec- right Copy- ration sepa- YC 2D/3D ＳＥＬ DRAM (5 Mbitｓ) Rec.656 L E S decode Chroma ACC Microcontroller clamp Digital APC Frame sync DRAM (7 Mbits) E L S Figure 3.4 Conversion DD / Line TBC Analog input processing input processing RST E reducL tion S Noise Clock processing L Explanations of registers MICONRWR NC3 MICOMSEL interface Microcontroller Rec.656 output S E MICONRWW CLK27XO generation CLK27XI MDA15～0 MAD6～0 MNWENBW MNRE MCSALE R656OUT 7～0 ANACLK CLK27O MN673794 [d] Write Registers Figure 3.4 shows the block diagram for the write registers. 15 MN673794 1. Control system Register name Address Description cpsh 0000h[15] Used to select the mode of the analog input processing block. 0: Component input 1: Composite input Used to select the input of the frame sync block. 00: Analog input 01: Rec656 input 10: Test use 11: Not used Used to select the input of the Rec656 output processing block. 0: Noise reduction output 1: Rec656 input Used to set the signal modes of the analog input processing block, frame sync processing block, Rec656 input processing block, and Rec656 output processing block. 000: NTSC 001: PAL-M 010: NTSC443 011: PAL-60 100: 101: PAL-N 110: 111: PAL Used to set the sync output of the sync separation block 00: Normal sync output mode 01: Prohibited 10: AFCV mode (pseudo V-AFC) 11: AFCV-still detection mode (pseudo V-AFC-still detection) Used to set the mode of the TBC block 00: Normal (DD conversion + jitter correction + velocity error correction) 01: Velocity error correction off (DD conversion + jitter correction) 10: Jitter correction / velocity error correction off (DD conversion only) 11: Prohibited Used to set the hold range of the DCLP (digital clamp) block (8 steps) 000: Thru 001: ±2 010: ±4 011: ±6 110: ±8 101: ±10 110: ±14 111: ±16 Used to set the operation of the DCLP (digital clamp) block 0: Off 1: On Used to set the error output of the clamp control block 00: Center fixed 01:Max. fixed 10:Min. fixed 11: Normal Used to set the error output of the AGC control block 00: Center fixed 01:Max. fixed 10:Min. fixed 11: Normal Used to set the AFCH pseudo lock reset of the sync separation block 0: Not available 1: Available fsinsel 0000h[13:12] r656outsel 0000h[11] sigmod 0000h[2:0] pvs_pll_ sell 0004h[1:0] tbcmod 0012h[1:0] rpclamp[4:2] 0014h[4:2] rpclamp[0] 0014h[0] clpreg[5:4] 0025h[5:4] agcreg1 [11:10] 0022h[11:10] SideLock Sel 0003h[1] paravsep pll 0004h[5:2] AFCV response characteristics parajdet pls 000Fh[13:12] Used to set the TBC sync separation misfmv 0020h[5:0] Used to set the lower limit of MV judgment level of the MV detection block tdir2516 0029h[3:1] Used to set the sync separation block SDF00032BEM Default (Recommended value) 1 00 0 000 11 (00) 00 000 (001) 1 11 11 0 1110 (0100) 11 (00) 100000 (100001) 000 (011) 16 MN673794 2. Y/C separation Default Register name Address Description (Recommended value) HYOZI 0008h[6] F3DSEL 0008h[5:3] F2DSEL 0008h[2:0] The detected movement area is displayed dark (for evaluation). 0: Normal 1: Movement detection display A threshold value to determine movement with two-frame differential movement detected. (Compared with the 9-bit absolute value converted from the 10-bit difference between the 9-bit input signal and 2-frame, 9-bit delay signal.) 000: 3D fixed 001: 4 or more 010: 8 or more 011: 12 or more 100: 16 or more 101: 20 or more 110: 24 or more 111: 28 or more (To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL register to 000. To fix the setting to 2D, set the F3DSEL to any value other than 000 and set the F2DSEL to 000.) A threshold value to determine movement with one-frame differential movement detected. (Compared with the 9-bit absolute value converted from the 10-bit difference between the 9-bit input signal and 1-frame, 9-bit delay signal.) 000: 3D fixed 001: 4 or more 010: 8 or more 011: 12 or more 100: 16 or more 101: 20 or more 110: 24 or more 111: 28 or more (To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL register to 000. To fix the setting to 2D, set the F3DSEL to any value other than 000 and set the F2DSEL to 000.) 0 100 100 3. Y/C delay adjustment Default Register name Address Description (Recommended value) cdly2 0009h[7:6] cdly1 0009h[5] tbccdly 0009h[9:8] cflgdly 0029h[0] Used to adjust the delay of the component C signal (in 4fsc increments). (DD conversion output of C signal of analog input processing block) 00: No delay 01: +1 clock 10: -2 clock 11: -1 clock Used to adjust the delay of the component C signal (in 27 MHz increments). (LPF output of C signal of analog input processing block) 00: No delay 01: +1 clock Used to adjust the delay of the CbCr multiple signal (in 4fsc increments). (Before TBC input into the analog input processing block) 00: No delay 01: +1 clock 10: -2 clock 11: -1 clock Used to reverse the polarity of the CbCr separation flag for the CbCr multiple signal. If the tint is reversed with tbccdly delay adjustments, invert this flag. (Before TBC input into the analog input processing block) 0: No reversion 1: Reversion SDF00032BEM 00 0 00 (11) 0 (1) 17 MN673794 4. Color setting Default Register name Address Description (Recommend -ed value) apcerr2deg 0006h[12:8] sekilmt 0006h[7:5] apcerr1deg 0006h[4:0] raccoff 000Ah[15] racc 000Ah[14:8] sacc 000Bh[15] racc 000Bh[12:8] rapcon 000Ch[6] rphadj 000Ch[5:0] Used to set the gain of the APC frequency pull-in (loop filter first term) (0 to 31) 00001: Large gain 00111: Default 01101: Small gain Used to set the burst lock range of the APC block 000: Narrow 011: Default 100: Wide Used to set the gain of the APC phase pull-in (loop filter zero term) (0 to 31) 11000: Small gain 11100: Default 11110: Large gain Used to set the On/Off of the FFACC (Digital feed forward ACC) block 0: Off 1: On Used to set the gain of the FFACC block 0: Default (72) Other than 0: racc[6:0]X2 Used to set the control DAC output of the FBACC (Analog feedback ACC) block 0: Center fixed 1: Normal (error output) Used to set the saturation (except burst) of the FFACC block 00000: Small 10000: Default 11111: Large Used to set the hue compensation of the APC block 0: Off 1: On Used to set the hue compensation of the APC block 100000: Large (-) 00000: Off 011111: Large (+) 00111 (00101) 011 11100 0 0000000 1 (0) 10000 0 00000 5. Rec656 output Default Register name Address Description (Recommend -ed value) VideoOutsel 002Eh[1:0] Used to switch over the valid pixels of the Rec656 output signal to blue or black background. 0X: Normal 10: Black background 11: Blue background SDF00032BEM 00 18 MN673794 6. Noise Reduction (NR) Figure 3.6-1 shows the block diagram of noise reduction. The input signal will be output with the NR-ROM output signal subtracted. Furthermore, the output signal will be delayed in fields or frames, and the difference from the input signal will be input into the NR-ROM. This is called recursive noise reduction with a variable recursive coefficient. Figure 3.6-2 shows the characteristics of the NR-ROM. The field/frame differential signal contains a movement or noise signal. When the field/frame differential signal is high, the signal is considered a movement signal. When the signal is low, it is considered a noise signal. The strength or gain of the filed/frame differential signal for noise reduction can be changed by register settings. Figure 3.6-3 shows the characteristics of noise reduction. For details, refer to the table of registers. Output ROM Input Frame/Field memory Fig. 3.6-1 NR Block Diagram ROM output yupslp cupslp yupslp cupslp yupslp cupslp NR gain yupslp cupslp yupslp cupslp Frame/Field Differential value yupslp cupslp Fig. 3.6-2 NR-ROM characteristics Fig. 3.6-3 SDF00032BEM Frame/Field Differential value NR characteristics 19 MN673794 Default Register name Address Description (Recommended value) Setnrin 003Ch[15] SetTof 003Ch[14:13] Set3dnr 003Ch[12] SetMdet 003Ch[9:5] 003Ch[4:3] SetMvVi 003Ch[2] Ydnslp 003Dh[12:10] Yupslp 003Dh[9:6] Yudchg 003Dh[5:0] Cdnslp 003Eh[12:10] Cupslp 003Eh[9:6] Cudchg 003Eh[5:0] Used to switch over the input into the noise reduction block. 0: Frame sync output 1: Rec656 input Used to make through/NR setting in the noise reduction block. 0X: NR block through 10: NR OFF 11: NR ON Used to set the recursive 3D control. 0: Frame recursive NR 1: Field recursive NR A threshold value to disable the noise reduction of the C signal by using the Y frame/field differential signal. The color frame/field differential signal has narrow band range. Therefore, higher precision can be obtained in edge portions by using the Y differential signal. If the threshold value is larger, the influence of the differential signal of Y will be less, and the NR of the C will be enabled by the color differential signal. If the threshold value is smaller, the NR of the C will not be enabled when the Y differential signal is high. Threshold value = SetMdet [6:2]×2 Example: If SetMdet is 01000, the threshold value is 16. A width where the noise reduction of C is disabled by the frame/field differential signal of Y. Area to disable the noise reduction of C: Number of clocks. 00: 1 clock (The differential signal of Y is used as it is) 01: -1 to +1 clock (The differential signal of Y is widened left and right for one clock each.) 10: -2 to +2 clock (The differential signal of Y is widened left and right for two clocks each.) 11: -3 to +3 clock (The differential signal of Y is widened left and right for three clocks each.) The detected movement area is displayed dark (for evaluation). 0: Normal 1: Movement detection display Used to make negative slope settings for a high Y frame/field differential signal range. If the differential signal is higher than the Yudchg value, the differential signal is considered a movement signal. Then the amount of noise reduction will be attenuated. Set the attenuation gain in the register. Large value: Quickly attenuated according to the differential signals. Small value: Slowly attenuated according to the differential signals. (For the characteristics, refer to NR-ROM and NR characteristics.) Used to make positive slope setting for a low Y frame/field differential signal range. If the positive slope setting is larger, the gain will be high to enable NR high. If the positive slope setting is smaller, the gain will be less to enable NR low. Gain=yupslp[3:00]/16 (For the characteristics, refer to NR-ROM and NR characteristics.) Used to set the change point between the above ydnslp (negative slope) and the yupslp (positive slope). If the differential signal is higher than the change point, the differential signal is considered a movement signal. Then the amount of NR will be attenuated. (For the characteristics, refer to NR-ROM and NR characteristics.) Used to set the negative slope of the maximum C frame/field differential value. (Same as Y in characteristics.) Used to set the positive slope of the minimum C frame/field differential value. Gain=cupslp[3:0]/16 (Same as Y in characteristics.) Used to set the change point between the above cdnslp (negative slope) and cupslp (positive slope). (Same as Y in characteristics.) SDF00032BEM 0 00 0 01000 01 0 010 10000 010000 010 1110 100000 20 MN673794 7. Frame sync Default Register name Address Description (Recommend -ed value) wr_offset 0017h[4:0] Frame sync, write line start position offset (23 lines + offset value) 00000 8. Analog power down (Possible to reduce the power consumption of the corresponding functions when the functions are not in use.) Default Register name Address Description (Recommend -ed value) yadpdwn 0039h[8] cadpdwn 0039h[7] Test0dapdwn 0039h[6] Test1dapdwn 0039h[5] Test2dapdwn 0039h[4] agcdapdwn 0039h[3] accdapdwn 0039h[2] clpdapdwn 0039h[1] testpllpdwn 0039h[0] Used to power down the component Y/composite Y (analog input) ADC. 0: Normal 1: Power down Used to power down the component C (analog output) ADC. 0: Normal 1: Power down Used to power down the DAC for test use. 0: Normal 1: Power down Used to power down the DAC for test use. 0: Normal 1: Power down Used to power down the DAC for test use. 0: Normal 1: Power down Used to power down the AGC control DAC. 0: Normal 1: Power down Used to power down the ACC control DAC. 0: Normal 1: Power down Used to power down the clamp control DAC. 0: Normal 1: Power down Used to power down the PLL for test use 0: Normal 1: Power down SDF00032BEM 0 0 0 (1) 0 (1) 0 (1) 0 0 0 0 (1) 21 MN673794 [e] Read registers 1. Macrovision Register name immvh Address 0041h[15] spiso 0041h[14:13] spgcnt sppos 0041h[12:8] 0041h[7:6] spcnt 0041h[5:0] agcflg 0042h[9:8] Description Result of AGC pulse detection 0: No 1: Yes Result of color stripe phase detection 00: 0° 01: 90° 10: 180° 11: 270° Result of detection of the number of color stripe groups per field Result of detection of the color stripe split position 00: No 01: Latter half 10: First half 11: Indefinite Result of detection of the number of color stripe lines per field (Implement the spcnt/spgcnt based on the result of spcnt and spgcnt detection. Then determine if the 4- or 2-line mode is set.) Result of detection of sync reduction 00: V=H 01: H>V 11: V>H Default 2. VBID Register name Address imdatavw 0043h[13:0] immidvw1 0044h[13:9] immidvw2 0044h[8:4] imvwlno 0044h[3:2] imvwdet 0044h[0] imvwok 0044h[1] Description Default Detection data First data=0043h[0] Number of data items the intermediate values of which are detected (from the 600 kHz LPF signal) (Number of bits out of the 14 data bits) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) (Number of bits out of the 14 data bits) The number of line where the data is detected 00: Not detected 01: 19(282)H 10: 20(283)H 11: 21(284)H Result of reference pulse detection 0: Not detected 1: Detected Reliability of the detection result 0: Not good 1: OK (The imvwdet bit is set to 1 and all data fixed with CRC added.) Description Default 3. WSS Register name imdatavw Address 0043h[13:0] immidvw1 0044h[13:9] immidvw2 0044h[8:4] imvwlno 0044h[3:2] imvwdet 0044h[0] imvwok 0044h[1] Detection data First data=0043h[0] Number of data items the intermediate values of which are detected (from the 1 MHz LPF signal) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) The number of line where the data is detected 00: Not detected 01: 19(282)H 10: 20(283)H 11: 21(284)H Result of Clock Run-In detection 0: Not detected 1: Detected Reliability of the detection result 0: Not good 1: OK (The imvwdet bit is set to 1 and start code and bi-phase acceptable) SDF00032BEM 22 MN673794 4. Closed caption Register name imdatacc Address 0045h[15:0] immidcc1 0046h[12:9] immidcc2 0046h[7:4] imcclno 0046h[3:2] imccdet 0046h[0] imccok 0046h[1] Description Detection data First data=0045h[0] Number of data items the intermediate values of which are detected (from the 600 kHz LPF signal) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) The number of line where the data is detected 00: Not detected 01: 20(283)H 10: 21(284)H 11: 22(285)H Result of Clock Run-In detection 0: Not detected 1: Detected Reliability of the detection result 0: Not good 1: OK (The imccdet bit is set to 0 and all data fixed) Default Description Color killer use 1/4 of the number of lines with no burst gate generated during a period of 128H. Color killer use The total number (absolute value) of APC errors resulted during a period of 128H. Result of detection of weak electromagnetic field sync noise (The number of pulses in the sliced and binary-coded Csync in a single field) Standard signal discrimination (Discriminated as a standard signal if the number of clocks per 1H period is within a range of 910±7.) 0: Standard 1: Nonstandard Field discrimination 0: Second field (even) 1: First field (odd) Signal detection result 0: Detected 1: Not detected Result of weak electromagnetic field detection The integrated noise value (0 to 255) in a period of 6H V-blanking. Discrimination of frame skipping in the frame sync block 0: No skip 1: Skipped Discrimination of frame hold in the frame sync block 0: No hold 1: Hold Default 5. Others Register name bg32cnt Address 0040h[7:4] ckreg 0040h[3:0] imjack 0042h[7:0] NSTD 0046h[15] odev 0048h[5] ghsfew 0048h[4] lownoise 0049h[15:8] frmchg_skip 004Ah[1] frmchg_hold 004Ah[0] SDF00032BEM 23 MN673794 ［f］ Register map Tables 3.4-1 to 3.4-4 show the register maps. Table 3.4-1 0000h D[15] 0003h 0004h Read Register Map 0006h 0008h 0009h cpsh 000Ah 000Bh raccoff sacc D[14] D[13] D[12] D[11] fsinsel [1:0] r656out sel racc [6:0] rlvl adj [4:0] apcerr 2deg [5:0] D[10] D[9] tbccdly [1:0] D[8] D[7] seki lmt [2:0] D[6] HYOZI cdly1 D[5] D[4] apcerr 1deg [4:0] D[2] D[1] D[0] F3DSEL [2:0] parav seppll [3:0] D[3] sigmod [2:0] sidelo cksel cdly2 [1:0] F2DSEL [2:0] pvs_pll _sell [1:0] SDF00032BEM 24 MN673794 Table 3.4-2 000Ch 000Fh 0014h Read Register Map 0017h 0020h 0022h 0025h 0029h 002Eh D[15] D[14] paraj detpls [1:0] D[13] D[12] D[11] agc reg1 [11:10] D[10] D[9] D[8] D[7] D[6] rapcon D[5] clp reg [5:4] D[4] D[3] D[2] rphadj [5:0] rp clamp [2:0] wr_ offset [4:0] mis fmv [5:0] tdir 2516 [2:0] D[1] D[0] rp clamp [2:0] cflg dly SDF00032BEM video out sel 25 MN673794 Table 3.4-3 0039h Read Register Map 003Ch 003Dh 003Eh ydn slp [2:0] cdn slp [2:0] yup slp [3:0] cup slp [3:0] yud chg [5:0] cud chg [5:0] set nrin D[15] D[14] set tof D[13] set 3dnr D[12] D[11] D[10] D[9] D[8] yad pdwn D[7] cad pdwn D[6] test0da Pdwn D[5] test1da pdwn D[4] test2da pdwn D[3] agcda pdwn D[2] accda pdwn D[1] clpda pdwn D[0] testpll pdwn set mdet [6:0] set mvvi SDF00032BEM 26 MN673794 Table 3.4-4 Write Register Map 0040h D[15] 0041h 0042h 0043h 0044h 0045h immvh D[14] 0046h 0048h 004Ah NSTD spiso [1:0] D[13] D[12] immid vw1 [4:0] D[11] spg cnt [4:0] D[10] D[9] agcflg [1:0] D[8] D[7] D[6] D[5] bg32 cnt [4:0] D[4] D[3] D[2] D[1] D[0] im data vw [13:0] sppos [1:0] sp cnt [5:0] ckreg [3:0] im jack [7:0] immid cc1 [3:0] im data cc [15:0] immid vw2 [4:0] immid cc2 [3:0] odev ghs few imvw lno [1:0] imcc lno [1:0] imvw ok im ccok imvw det im ccdet SDF00032BEM low noise [3:0] frmchg skip frmchg hold 27 01 3URGXFWVWDQGDUGV A. Absolute Maximum Ratings (VSS= 0 V) Parameter Symbol Rating A1 External supply voltage VDD -0.3 to 4.6 A2 Internal supply voltage VDDI -0.3 to 3.6 A3 Input pin voltage VI -0.3 to VDD+0.3 (Upper limit: 4.6) A4 Output pin voltage VO -0.3 to VDD+0.3 (Upper limit: 4.6) IO ±6 IO ±12 IO ±24 A5 A6 A7 Output current (TYPE-HL2) Output current (TYPE-HL4) Output current (TYPE-HL8) Unit V A8 Power dissipation PD 1920 A9 Operating ambient temperature TOPR -20 to +80 TSTG -40 to 125 mA mW ℃ A10 Storage temperature TYPE-HL2 pins： CASHD, CASVD, CLK188, CLK450, ANACLK, GCP, CSYNCO, MICONRWW, MICONRWR, APCE, TDO TYPE-HL4 pins： CLK27O, CLK18O2, CLK18O1, R656OUT7 to R656OUT0, FRP, HD, VD, TESTIO9 to TESTIO0, DSF7 to DSF0, MAD6 to MAD0, MCSALE, MNR, MNWENBW, MICOMSEL, NC3 TYPE-HL8 pins： MDA15 to MDA0 Note) (1) The external supply pins are VDD3, VDD2, and AVDD pins and the internal supply pins are VDDI and VDDDRAM pins. (2) The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. (3) Connect all VDD pins externally and directly to the power supply. Connect all VSS pins externally and directly to ground. (4) Connect one or more bypass capacitors of 0.1 µF or larger between the power supply pin and ground. (5) Connect MINTEST pin to VSS pin. 6')%(0 01 B. Recommended Operating Conditions (VSS= 0 V) Parameter Symbol Limits Conditions Unit Min Typ Max B1 Supply voltage (External 1) VDD３ 3.0 3.3 3.6 V B2 Supply voltage (External 2) VDD2 2.0 2.2 2.4 V B3 Supply voltage (Internal) VDDI 1.65 1.8 1.95 V B4 Supply voltage (Internal DRAM) VDDDRAM 2.3 2.5 2.7 V B5 Supply voltage (Analog) AVDD 3.0 3.3 3.6 V B6 Ambient temperature Ta -20 80 ℃ B7 Oscillator frequency fOSC CLK27XI pin 27 MHz B8 Clock 1 input frequency fIN1 CLK27I 27 MHz B9 Clock 2 input frequency fIN2 CLK45I 4.5 MHz C. Pin Capacitance C1 Input pin C2 Output pin C3 I/O pin CIN COUT CIO VDD=VI=0 V 7 8 pF fin=1 MHz 7 8 pF Ta=25℃ 7 8 pF 6')%(0 01 D. Electrical Characteristics (1) DC Characteristics （VSS=AVSS=VSSDRAM=0 V, Ta=-20℃ to 80℃） Limits Parameter Symbol Conditions Unit Min D1 D2 D3 Operating supply current Operating supply current Operating supply current IDDI IDDDRAM IDDANA Typ Max VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open 300 mA VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open 80 mA VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open 302 mA 6')%(0 01 Limits Parameter Symbol Conditions Unit Min <Input: CMOS level> Typ Max CLK27I D4 High-level input voltage VIH3 VDD3 ×0.7 VDD3 V D5 Low-level input voltage VIL3 0 VDD3 ×0.3 V D6 Input leakage current ILIPD3 ±5 µA VI=VDD3 or VSS <Input: CMOS level with pull-up resistor> RST, TDI, TRST, TMS D7 High-level input voltage VIH4 VDD3 ×0.7 VDD3 V D8 Low-level input voltage VIL4 0 VDD3 ×0.3 V D9 Input leakage current ILIPD4 VI=VDD3 ±10 µA RPU4 VDD3=0.0 V 300 kΩ D10 Pull-up resistor 33 100 <Input: CMOS level with pull-down resistor> TCK, TEST5 to TEST0, PDRAM1, PDRAM0, NTDRAM, R656IN7 to R656IN0, INF D11 High-level input voltage VIH5 VDD3 ×0.7 VDD3 V D12 Low-level input voltage VIL5 0 VDD3 ×0.3 V D13 Input leakage current ILIPD5 VI=VSS ±10 µA D14 Pull-up resistor RPD5 VDD3=3.3 V 300 kΩ <Input: CMOS level with pull-down resistor> 33 100 MINTEST D15 High-level input voltage VIH6 VDD3 ×0.7 VDD3 V D16 Low-level input voltage VIL6 0 VDD3 ×0.3 V D17 Input leakage current ILIPD6 VI=VSS ±10 µA D18 Pull-up resistor RPD6 VDD3=3.3 V 90 kΩ 6')%(0 10 30 01 Limits Parameter Symbol Conditions Unit Min <Input: CMOS level> Typ Max MINTC1, MINTIN1 D19 High-level input voltage VIH7 VDD3 ×0.7 VDD3 V D20 Low-level input voltage VIL7 0 VDD3 ×0.3 V D21 Input leakage current ILIPD7 ±5 µA VI=VDD3 or VSS 6')%(0 01 Limits Parameter Symbol Conditions Unit Min Typ Max <Output: Normal buffer> ANACLK, GCP, CSYNCO, MICONRWW, MICONRWR D22 High-level output voltage VOH9 IOH=-2 mA,VI=VDD3 or VSS D23 Low-level output voltage VOL9 IOL=2 mA,VI=VDD3 or VSS <Output: Normal buffer> V 0.4 V CLK27O, CLK18O2, R656OUT7 to R656OUT0, FRP D24 High-level output voltage VOH10 IOH=-4 mA,VI=VDD3 or VSS D25 Low-level output voltage VOL10 IOL=4 mA,VI=VDD3 or VSS <Output: Tri-state buffer> VDD3 -0.6 VDD3 -0.6 V 0.4 V APCE, TDO VDD3 -0.6 D26 High-level output voltage VOH11 IOH=-2 mA,VI=VDD3 or VSS D27 Low-level output voltage VOL11 IOL=2 mA,VI=VDD3 or VSS 0.4 V D28 Output leakage current IOZ11 VO=Hi-z state ±5 µA V VI=VDD3 or VSS VO=VDD3 or VSS <Output: Normal buffer> CASHD, CASVD, CLK188, CLK450 D29 High-level output voltage VOH12 IOH=-0.5 mA,VI=VDD2 or VSS D30 Low-level output voltage VOL12 IOL=0.5 mA,VI=VDD2 or VSS <Output: Normal buffer> VDD2 -0.4 V 0.4 V CLK18O1 D31 High-level output voltage VOH13 IOH=-1.0 mA,VI=VDD2 or VSS D32 Low-level output voltage VOL13 IOL=1.0 mA,VI=VDD2 or VSS 6')%(0 VDD2 -0.4 V 0.4 V 01 Limits Parameter Symbol Conditions Unit Min <Output: Tri-state buffer / Input: CMOS level> Typ Max MDA15 to MDA0 D33 High-level input voltage VIH14 VDD3 ×0.7 VDD3 V D34 Low-level input voltage VIL14 0 VDD3 ×0.3 V D35 High-level output voltage VOH14 IOH=-8 mA,VI=VDD3 or VSS D36 Low-level output voltage VOL14 IOL=8 mA,VI=VDD3 or VSS 0.4 V D37 Output leakage current IOZ14 VO=Hi-z state ±5 µΑ VDD3 -0.6 V VI=VDD3 or VSS VO=VDD3 or VSS <Output: Tri-state buffer / Input: CMOS level with pull-up resistor> HD, VD D38 High-level input voltage VIH15 VDD3 ×0.7 VDD3 V D39 Low-level input voltage VIL115 0 VDD3 ×0.3 V D40 Input pull-up resistor RPU15 VI=0.0 V 300 kΩ D41 High-level output voltage VOH15 IOH=-4 mA,VI=VDD3 or VSS D42 Low-level output voltage VOL15 IOL=4 mA,VI=VDD3 or VSS 0.4 V D43 Output leakage current IOZ15 VO=pull-up state ±10 µA 33 100 VDD3 -0.6 V VI=VDD3 or VSS VO=VDD3 6')%(0 01 Limits Parameter Symbol Conditions Unit Min Typ Max <Output: Tri-state buffer / Input: CMOS level with pull-down resistor> TESTIO9 to TESTIO0 D44 High-level input voltage VIH16 VDD3 ×0.7 VDD3 V D45 Low-level input voltage VIL116 0 VDD3 ×0.3 V D46 Input pull-down resistor RPD16 VI=VDD3 300 kΩ D47 High-level output voltage VOH16 IOH=-4 mA,VI=VDD3 or VSS D48 Low-level output voltage VOL16 IOL=4 mA,VI=VDD3 or VSS 0.4 V D49 Output leakage current IOZ16 VO=pull-down state ±10 µA 33 100 VDD3 -0.6 V VI=VDD3 or VSS VO=VSS <Output: Tri-state buffer / Input: CMOS level schmitt> MAD6 to MAD0, MCSALE, MNRE, MNWENBW, MICOMSEL, NC3 VDD3 -0.6 D50 High-level output voltage VOH17 IOH=-4 mA,VI=VDD3 or VSS D51 Low-level output voltage VOL17 IOL=4 mA,VI=VDD3 or VSS 0.4 V D52 Output leakage current IOZ17 VO=Hi-z state ±5 µA V VI=VDD3 or VSS VO=VDD3 or VSS 6')%(0 01 Limits Parameter Symbol Conditions Unit Min Typ Max <Output: Tri-state buffer / Input: CMOS level with pull-down resistor> DSF7 to DSF0 D53 High-level input voltage VIH18 VDD2 D54 Low-level input voltage VIL118 0 D55 Input pull-down resistor RPD18 VI=VDD3 D56 High-level output voltage VOH18 IOH=-1.0 mA,VI=VDD2 or VSS D57 Low-level output voltage VOL18 IOL=1.0 mA,VI=VDD2 or VSS 0.4 V D58 Output leakage current IOZ18 VO=pull-down state ±10 µA 3.00 MΩ VDD2 ×0.7 33 VDD2 ×0.3 100 300 VDD2 V V kΩ V -0.4 VI=VDD3 or VSS VO=VDD3 <Oscillator circuit> CLK27XO D59 Internal feedback resistor Rf7 VI=VDD3 or VSS 0.33 1.00 VDD3=3.3 V 6')%(0 01 (2) AC Characteristics (Under the recommended operating conditions) Parameter Symbol Limits Conditions Min <R656 digital video input> D60 Input setup time D61 Input hold time <R656 digital video output> D62 Output delay time <DV video input> D63 Input setup time D64 Input hold time <DV control signal input> D65 Output delay time <DV control signal input> D66 Output delay time Typ Unit Max R656IN7 to R656IN0 tS1 10.0 ns 5.0 ns Fig. 3-1 tH1 R656OUT to R656OUT0 tD2 Fig. 3-1 5.0 27.0 ns DSF7 to DSF0 tS3 10.0 ns 5.0 ns Fig. 3-2 tH3 CASHD, CASVD tD4 Fig. 3-2 5.0 45.0 ns Fig. 3-2 5.0 45.0 ns FRP tD5 6')%(0 01 E. Analog Characteristics (AVDD = 3.3 V, AVSS = 0 V, Ta = 25℃) Parameter <10-bit A/D converter> E1 E2 E3 Symbol Conditions Limits Min Typ AVSS 0.5 Max Unit VIDEO, CIN Low-level reference voltage High-level reference voltage VREFH1 Integral nonlinearity NLE1 VREFL1 fADCK1=27.0 MHz V 2.5 AVDD V ±6.0 ±8.0 LSB ±2.0 ±4.0 LSB 27 MHz VREFH=2.5 V VREFL=0.5 V E4 Differential nonlinearity DNLE1 fADCK1=27.0 MHz VREFH=2.5 V VREFL=0.5 V E5 Clock frequency fADCK1 <10-bit high-speed D/A converter> E6 Zero-scale output voltage VZS2 VREF=1.235 V 0 V[p-p] 1.0 V[p-p] D9 to D0＝ALL "L" E7 Full-scale output voltage VFS2 VREF=1.235 V D9 to D0＝ALL "H" E8 Integral nonlinearity NLE2 fADCK2=27 MHz ±1.5 ±3.0 LSB ±1.0 ±3.0 LSB 27 MHz VREF=1.235 V E9 Differential nonlinearity DNLE2 fADCK2=27 MHz VREF=1.235 V E10 Clock frequency fADCK2 6')%(0 01 (AVDD = 3.3 V, AVSS = 0 V, Ta = 25℃) Parameter Symbol Conditions Limits Min Typ Max Unit <10-bit voltage dividing type D/A converter> E11 Zero-scale output voltage VZS3 D9 to D0＝ALL "L" -0.1 0 0.1 V E12 Full-scale output voltage VFS3 D9 to D0＝ALL "H" 3.1 3.2 3.3 V E13 Integral nonlinearity E14 Differential nonlinearity E15 Clock frequency NLE3 fADCK3=1 MHz ±1.0 ±3.0 LSB DNLE3 fADCK3=1 MHz ±1.0 ±2.0 LSB 1 MHz fADCK3 6')%(0 01 CLK27I R656IN7 to R656IN0 tH1 tS1 CLK27O R656OUT7 to R656OUT0 tD2 Fig. 3-1 I/O signal timing 6')%(0 01 CLK18O1 DSF7 to DSF0 (Input) tH3 tS3 CASHD, CASVD tD4 CLK18O2 FRP tD5 Fig. 3-2 I/O signal timing 6')%(0 01 Package Dimensions (Unit: mm) LQFP208-P-2828 (Lead-free package) 30.00±0.20 28.00±0.10 105 156 104 208 53 30.00±0.20 1.70 max. 52 Seating plane 0.20±0.05 0.08 M 0.10 6')%(0 (1.00) 0.15±0.05 0.50 0.10±0.10 (1.25) 28.00±0.10 1 1.40±0.10 (1.25) 157 0° to 8° 0.50±0.20