FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-23003-1E
ASSP
CMOS
5V Single Power Supply Audio
Interface Unit (AIU)
MB86434
■ DESCRIPTION
The FUJITSU MB86434 is an AIU (audio interface unit) LSI for +5 V single-power source digital telephone devices,
manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards,
and can handle input and output in A-Law, µ-Law and linear conversion modes. The MB86434 also contains the
necessary DTMF, microphone and receiver amps for telephone devices.
■ FEATURES
• +5 V single power supply
• Low power consumption: muting settings for each operating mode
Normal operation : 8.2 mA typ (speaker amp mute)
Tone generation : 1.8 mA typ (speaker amp mute)
Standby mode
: 0.5 mA typ
• On-chip codec filter meets G.712 standards
• Selection of codec conversion methods (A-law, µ-law, linear)
• On-chip low-noise microphone amp (2-channel) (unity gain frequency: 1MHz)
• On-chip receiver speaker amps (32 ΩBTL type: 10 mW MIN)
• On-chip tone speaker amp (32 ΩBTL type: 200 mW MIN)
• On-chip earphone speaker amps (32 Ω single type: 5 mW MIN)
(Continued)
■ PACKAGE
64 pin, Plastic QFP
(FPT-64P-M07)
MB86434
(Continued)
•
•
•
•
•
On-chip electronic volume gain adjustments (sending, receiving, tone)
On-chip accessory output circuits
DTMF generator function
Service tone generation
CMOS compatible input/output
■ PIN ASSIGNMENT
(TOP VIEW)
33
51
32
52
INDEX
20
64
19
1
(FPT-64P-M07)
2
MB86434
■ PIN DESCRIPTION
Pin No.
Symbol
I/O
A/D
Description
1
CAG
G
A
Analog ground pin for codec block. To be set to 0 V.
2
VRH
O
A
Bypass capacitor connector pin for the A/D D/A reference voltage generator
circuit. Place capacitor between VRH and CAG pins.
3
SGC
O
A
Bypass capacitor connector pin for the signal ground potential generator
circuit. Place capacitor between SGC and CAG pins.
4
VDDAC
P
A
Analog power supply pin for codec block. To be set within range 4.75 to
5.25 V.
5
N.C.
—
—
Not connected. To be left open.
6
N.C.
—
—
Not connected. To be left open.
7
SYNC
I
D
PCM codec send/receive synchronization signal input pin. Operating clock
frequencies 8 kHz. CMOS interface. Other frequencies may cause codec
block to power-down.
8
CLK
I
D
Send/receive PCM signal series bit rate setting input pin. Data rate for µ-law,
A-law modes may be set to any level in the range 64 k to 3.152 MHz, and for
linear in the range 256 k to 3.152 MHz. Constant H or L level signal will
cause part of codec block to power-down. CMOS interface.
9
DIN
I
D
PCM signal input pin. This signal is picked up internally at the fall of the CLK
signal. CMOS interface.
10
DOUT
O
D
PCM signal output pin. Data is output in sync with the rise of the CLK signal.
After data output, loses PLL synchronization, and at power-down this signal
is fixed at H level. CMOS interface.
11
VDD
P
D
Digital power supply pin. To be set within range 4.75 to 5.25 V.
12
DG
G
D
Digital ground pin. To be set to 0V.
13
PSC0
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC1,2
pins for power-down settings.
PSC 2 1 0
0 0 0 Full power-down
1 0 0 VREF operating
— 1 0 Tone operating
— — 1 All operations available
(—: value not determined)
14
PSC1
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC0,2
pins for power-down settings.
15
PSC2
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC0,1
pins for power-down settings.
16
SRD
I
D
9-bit serial data input pin. CMOS interface. Data is written at the rise of the
signal from this pin.
17
SRC
I
D
Clock input pin for 9-bit serial data writing. CMOS interface. Data is written
at the rise of this pin.
18
STB
I
D
Serial data latch strobe signal. Data is latched by the L level signal. CMOS
interface. On-chip pull-down resistance.
19
XPRST
I
D
Digital reset signal input pin. CMOS interface. L level: internal latch
initialization H level: normal operation
(Continued)
3
MB86434
Pin No.
Symbol
I/O
A/D
Description
20
LO0
O
D
External control latch output pin. Outputs value D0 of address 1000. CMOS
interface.
21
LO1
O
D
External control latch output pin. Outputs value D1 of address 1000. CMOS
interface.
22
LO2
O
D
External control latch output pin. Outputs value D2 of address 1000. CMOS
interface.
23
LO3
O
D
External control latch output pin. Outputs value D3 of address 1000. CMOS
interface.
24
TCLK
I
D
Tone generator clock input pin. Can be used as a tone CLK signal by using
address 1110 D4D3 to subdivide the internal clock signal by factors of 1/1,
1/2, 1/4. CMOS interface.
25
TONC
I
D
Tone generator cycle control input pin. CMOS interface. Hlevel signal
outputs tone.
26
LED
O
D
Ring LED control output pin. CMOS interface.
27
TENV
I
A
Can be used to generate tone envelope, by placing capacitor between
grounds and turning SW11 on/off.
28
SWO
I/O
A
Analog switch 10 input/output pin. Controls address 0111 D0.
29
SWI
I/O
A
Analog switch 10 input/output pin.
30
DSDT
I
A
Accessory input. Can be connected to RAUD by switching paths.
31
TONEO
O
A
Tone signal output pin.
32
RAUD
O
A
Output pin for external speaker, or audio test signal. Can be connected to
DSDT by switching paths.
33
VDDSP1
P
A
Speaker amp power supply pin. To be set within range 4.75 to 5.25 V.
34
JEAR
O
A
Earphone speaker amp output pin. Capable of 5 mW output at 32 Ω load.
35
XEAR
O
A
Receiver speaker amp output pin. Internally connected to EAR and BTL.
Maximum output of 10 mW can be obtained at 32 W load by connecting
speaker between EAR and XEAR.
36
EAR
O
A
Receiver speaker amp output pin. Connected to XEAR and BTL.
37
SPG1
G
A
Speaker amp ground pin. To be set to 0 V.
38
SPG2
G
A
Speaker amp ground pin. To be set to 0 V.
39
XTONE
O
A
Speaker amp tone output pin. Internally connected to TONE and BLT.
Maximum output of 10 mW can be obtained at 32 Ω load by connecting
speaker between TONE and XTONE.
40
TONE
O
A
Speaker amp tone output pin. When speaker amp is not used for tone,
TONE should be shorted to IMTON.
41
IMTON
I
A
Speaker drive inverted (–) signal input pin. Can be used to adjust gain by
connecting resistance to TONE and IMTON.
42
VDDSP2
P
A
Speaker amp power supply pin. To be set within range 4.75 to 5.25 V.
(Continued)
4
MB86434
(Continued)
Pin No.
Symbol
I/O
A/D
Description
43
BBI
O
A
AMP3 output pin. Should be included in HPF together with IM3, to prevent
DC offset from entering speakers.
44
IM3
I
A
AMP3 inverted (–) signal input pin.
45
BTO
O
A
Receiving volume adjustment circuit output pin.
46
OP2
O
A
AMP2 output pin. If AMP2 is not used, IM2 should be shorted to OP2.
47
IM2
I
A
AMP2 inverted (–) signal input pin. Can form a circuit with OP2 to add
sidetone or tone. Melody circuits, if used, can also be connected here.
48
OP1
O
A
AMP1 output pin. Can form a circuit with IM1 to include LPF or HPF in
receiving block. If AMP1 is not used, IM1 should be shorted to OP1.
49
IM1
I
A
AMP1 inverted (–) signal input pin.
50
PTBO
O
A
PCM receiver output pin.
51
BAG
G
A
Analog ground pin for sending, receiving blocks. To be set to 0 V.
52
VDDAB
P
A
Analog power supply pin for sending, receiving blocks. To be set within
range 4.75 to 5.25 V.
53
XJMIC
I
A
Microphone amp (2) non-inverted (+) signal input pin.
54
JMIC
I
A
Microphone amp (2) inverted (–) signal input pin.
55
JMICO
I
A
Microphone amp (2) output pin.
56
XMIC
I
A
Microphone amp (1) non-inverted (+) signal input pin.
57
MIC
I
A
Microphone amp (1) inverted (–) signal input pin.
58
MICO
O
A
Microphone amp (1) output pin.
59
SGO
O
A
Sending block signal ground potential output pin. Buffers SGC voltage.
60
BBO
O
A
Sending analog signal output pin.
61
N.C.
—
—
Not connected. To be left open.
62
N.C.
—
—
Not connected. To be left open.
63
BTPI
I
A
PCM ENCODE block input OP amp negative input pin.
64
BTPO
O
A
PCM ENCODE block input OP amp output pin.
5
MB86434
■ BLOCK DIAGRAM
SGO (59) SGC (3)
–
VRH (2)
BTPO (64)
VREF
+
BTPI (63)
BBO (60)
–
generator
SYNC
(7)
CLK
(8)
–
+
VREF generator block
DOUT
(10)
SW3
0 dB
0 dB (TYP)
+
EV0
SGC
Microphone amp ➀
–
+
BPF
5bit
SGC
Codec block
A/D
PLL
512K
D/A
DIN
(9)
PTBO
(50)
OP1
(48)
IM1
(49)
SW4
–7.5 to 8dB
0.5dB step
Sending block
0 dB (TYP)
–7.5 to 8dB
EV1
0.5dB step
–
+
Microphone amp ➁
LPF
SW10
5bit
SW11
TONE generator
SW12
0 dB
–
+
SGC
OP2
(46)
IM2
(47)
AMP1
0 dB (TYP)
–16 to 12dB
EV2 4.0dB step
SW8
SWI
(29)
SWO
(28)
TENV
(27)
DSDT
(30)
PD
RAUD
(32)
+
Accessory block
3bit
–
–
MICO
(58)
MIC
(57)
XMIC
(56)
JMICO
(55)
JMIC
(54)
XJMIC
(53)
SGC
+
AMP2
SGC
BTO
(45)
IM3
(44)
0 dB
–
SW14
AMP3
+
SW6
–
SGC
Receiving block
–
XEAR
(35)
SGC
SW2
1/N cycle
TONE ➀
Receiver speaker drive block
0 dB (TYP)
generator
TONC
0 dB
EV3
–6dB
+
1/N cycle
1/4 cycle
TONE ➁
Single-10dB v 5bit
dual -10dB v
–7.5 to 8dB
0.5dB step
generator
TONC
–
+
TONC
SW7
PD
–
+
SGC
SW9
DATA LATCH
P SAVE
PD
–
Control block
: Digital input
: Digital output
: Analog input
: Analog output
PD
SGC
Tone speaker drive block
LED
(26)
: Input/output
: VDD
IMTON
(41)
TONE
(40)
0 dB
+
PSC0 PSC1 PSC2
(13) (14) (15)
JEAR
(34)
Earphone speaker drive block
Tone generator block
SRD SRC STB XPRST LO0 LO1 LO2 LO3
(16) (17) (18) (19)
(20) (21) (22) (23)
6
PD
+
1/2 cycle
TONC
(25)
VDDAB
VDDAC
VDDSP1
VDDSP2
VDD
SPG1
SPG2
CAG
BAG
DG
EAR
(36)
0 dB
+
BBI
(43)
TONEO
(31)
TCLK
(24)
PD
: GND
XTONE
(39)
MB86434
■ FUNCTIONAL DESCRIPTION
1. Register Settings
The MB86434 IC chip controls all electronic volume, switching, tone generator circuits and power-down control
circuits by means of the SRD, STB and SRC data input signals.
The MB86434 uses a 9-bit serial data format consisting of a 4-bit address followed by 5 data bits. Data is picked
up at the rise of the SRC signal, and latched by the STB L-level signal. The 9-bits of serial data preceding the STB
signal are considered valid. These register settings are not reset at power-down. They can be reset when data is
initialized by an XPRST L-level signal.
(1) Mode Settings
Control
segment
Address
Data bit
EV0
0 0 0 1 D4 D3 D2 D1 D0
EV1
0 0 1 0 D4 D3 D2 D1 D0
EV2
0 0 1 1
* * D2 D1 D0
TX-MUTE
0 1 0 0 D4 * * * D0
RX-MUTE
SW4
SW3
0 1 0 1 D4 * D2 D1 D0
SW8
SW6
SW9
0 1 1 0 D4 * D2 D1 D0
SW7
ATT
Setting description
A3 A2 A1 A0 D4 D3 D2 D1 D0
Initial data bit
setting (at reset) Remarks
D4 D3 D2 D1 D0
Sending audio level adjustment.
Adjusts EV0 gain.
Sending audio level adjustment.
Adjusts EV1 gain.
Sending audio level adjustment.
Adjusts EV2 gain.
D0: Sending audio mute SW 3, 4 on/off
control.
Mute: 1, Unmute: 0
D4: Receiving audio mute SW 6, 7, 8, 9
on/off control.
Mute: 1, Unmute: 0
D1: JMIC mute SW 4 on/off control.
Mute: 1, Unmute: 0
D2: MIC mute SW 3 on/off control.
Mute: 1, Unmute: 0
D4: RAUD mute SW 8 on/off control.
Mute: 1, Unmute: 0
D0: EAR, XEAR mute SW 6 on/off control.
Mute: 1, Unmute: 0
D1: TONE, XTONE mute SW 9 on/off
control.
Mute: 1, Unmute: 0
D2: JEAR mute SW 7 on/off control.
Mute: 1, Unmute: 0
D4: JEAR attenuation level switch.
0: 0.0 dB, 1: -6.0 dB.
0 1 1 1 1
0 1 1 1 1
*1
* * 1 0 0
*2, *3
0 * * * 0
*3, *4
*2
0 * 0 0 0
*3, *4, *5
*4
0 * 0 0 0
(Continued)
7
MB86434
(Continued)
Control
segment
SW10
SW12
SW11
SW2
SW14
Serial/
parallel
converter
EV3
TONE control
Frequency
control
Output
control
Master
clock
control
PCM
TEST
Address
Data bit
Setting description
A3 A2 A1 A0 D4 D3 D2 D1 D0
D0: SWI-SWO switch SW 10 on/off
control.
On: 1, Off: 0
D1: DSDT pin selection SW 12 on/off
control.
On: 1, Off: 0
D2: Envelope generator
0 1 1 1 D4 D3 D2 D1 D0
generate envelope (SW11 Off): 1
no envelope (SW11 On): 0
D3: TONEO mute SW 2 on/off control.
Mute: 1, Unmute: 0
D4: TONE sending add SW 14 on/off
control.
On: 1, Off: 0
Parallel output D3 = LO3, D2 = LO2,
* D3 D2 D1 D0 D1 = LO1, D0 = LO0
Initial data bit
setting (at reset) Remarks
D4 D3 D2 D1 D0
*3, *6
*3, *5
0 0 0 0 0
*3, *7
*8
* 0 0 0 0
*9
1 0 0 1 D4 D3 D2 D1 D0 Tone level adjustment. Adjusts EV3 gain.
1 0 1 0 X8 X7 X6 X5 X4 Tone (1) frequency control, set by 8-bit
value X7 to X0.
X
1 0 1 1 * X7 X6 X5 X4 8 = 1 to output trapezoidal wave, X8 = 0 to
output sine wave.
1 1 0 0 Y8 Y7 Y6 Y5 Y4 Tone (2) frequency control, set by 8-bit
value Y7 to Y0.
1 1 0 1 * Y3 Y2 Y1 Y0 Y8 = 1 to output trapezoidal wave, Y8 = 0 to
output sine wave.
Tone generator control
D0: tone (2) on/off control. On: 1, off: 0
D1: tone (1) on/off control. On: 1, off: 0
D2: LED output on/off control. On: 1, off: 0
Tone CLK
1 1 1 0 D4 D3 D2 D1 D0 D4, D3
0
0 : FTCLK1/1 frequency selected
0
1 : FTCLK1/2 frequency selected
1
0 : FTCLK1/4 frequency selected
1
1 : Prohibited
PCM control
D1, D0
0 : µ-law mode selected
1 1 1 1 * * * D1 D0 0
1
0 : A-law mode selected
0
1 : linear mode selected
0 1 1 1 1
*1
0 0 0 0 D4 D3 D2 D1 D0 Do not write in test mode.
0 0 0 0 0
1 0 0 0
0 0 0 0 0
* 0 0 1 0
0 0 0 0 0
*10, *11
* 0 0 1 0
*7, *8,
*12
0 0 1 1 1
*10
* * * 0 0
*13, *14
(Continued)
8
MB86434
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
*14:
See (4) Electronic Volume Controls
See (2) Sending Audio Mute Setting
See 5. Power Saving Modes
See (3) Receiving Audio Mute Settings
See 3. Analog Output (2) Accessory Output
See 2. Analog Input (2) Accessory Input
See (5) Tone Generator Circuit • Tone Output Controls
See (5) Tone Generator Circuit • Tone Generator Control Output Level
See (7) Parallel Output
See (5) Tone Generator Circuit • Tone Frequency Control Registers
See (5) Tone Generator Circuit • Tone Output Waveforms
See (5) Tone Generator Circuit • LED Output Controls
See (6) Codec Input/Output
See (7) The Codec SYNC Pin
9
MB86434
(2) Sending Audio Mute Settings
Switches SW 3 to SW 4 have the following functions. Address 0100 signals have priority.
Setting
Address
A3
A2
A1
A0
A3
A2
A1
A0
0
1
0
0
0
1
0
1
Switching setting
D4 D3 D2 D1 D0 D4 D3 D2 D1 D0
Data bit
: muted,
—
*
*
*
1
—
*
— —
*
—
*
*
*
0
—
*
—
1
*
—
*
*
*
0
—
*
1
—
*
—
*
*
*
0
—
*
—
0
*
—
*
*
*
0
—
*
0
—
*
SW3
Remarks
SW4
—
—
—
—
: unmuted, — : not determined
(3) Receiving Audio Mute Settings
Switches SW 6 to SW 9 have the following functions. Address 0100 signals have priority.
Setting
Address
A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0
0
1
0
0
0
1
0
1
0
1
1
0
D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0
Data bit
: muted,
10
Switching setting
SW8
SW7
SW9
—
1 *
*
* —
— * —— —
— * —— —
0 *
*
* —
— * —— —
— * —— 1
—
—
0 *
*
* —
— * —— —
— * — 1 —
—
—
0 *
*
* —
— * —— —
— * 1 — —
—
0 *
*
* —
1 * —— —
— * —— —
0 *
*
* —
— * —— —
— * —— 0
0 *
*
* —
— * —— —
0 *
*
* —
0 *
*
* —
SW6
—
—
—
—
—
—
—
—
—
— * — 0 —
—
—
— * —— —
— * 0 — —
—
0 * —— —
— * —— —
: unmuted, — : not determined
—
—
—
—
—
—
MB86434
(4) Electronic Volume Controls
There are four different electronic volume controls, EV0 through EV3, with the following specifications. Electronic
volume control settings are made by the SRD, SRC and STB signals, and setting values are reset by the XPRST
signal. However, settings are not reset by PSC0, PSC1, PSC2 power-down mode operations.
Table 1
Data bit value
EV0
sending gain
adjustment
D4 D3 D2 D1 D0
Typ.
Typ.
Typ.
Typ.
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
–16
–12
–8
–4
0
4
8
12
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Step
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Relation of Volume Control Data bit Values to Gain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EV1
EV2
receiving gain receiver volume
adjustment
adjustment
EV3
tone gain
adjustment
Unit
dB
Note: Each setting value is determined in relation to the initial setting value.
Returns to initial value at reset (
parts)
EV2 data bits D4, D3 are *.
Table 2
Volume control No.
EV0
EV1
EV3
EV2
Volume Gain Deviation
Condition
Min.
Typ.
Max.
Gain deviation, with respect to
reference value shown in Table1
Reference
value
– 0.5 dB
Reference
value
Reference
value
+ 0.5 dB
Input frequency = 1020 Hz
Input level = – 20 dBv
Reference
value
– 1.0 dB
Reference
value
Reference
value
+ 1.0 dB
Unit
dB
11
MB86434
(5) Tone Generator Circuit
• Tone Frequency Control Registers
The tone generator uses a clock signal obtained by subdividing the TCLK clock signal input by 1/1, 1/2 or 1/4
according to the data bit in address 1110.
Table 3
Tone Clock Frequency Register Control
Address 1110
Tone generator clock signal (fIN)
D4
D3
0
0
TCLK input clock signal
0
1
TCLK input clock signal subdivided by 1/2
1
0
TCLK input clock signal subdivided by 1/4
1
1
Prohibited
Frequency settings available through the tone frequency control register are determined by the following formula.
Frequency setting f = fIN/(12*(1+n)), n = 1, 2, 3, ..., 255. (where fIN: tone generator clock signal frequency).
Therefore the available frequency setting range when fIN = 512 kHz is between fmin = 167 Hz and fmax = 21333 Hz.
Frequency settings corresponding to each DTMF rated reference frequency are shown in the following table.
Table 4
Tone Frequency Register Control
(Condition: 512 kHz)
Tone type
Service tone
(single tone)
Low tone
D
T
M
F
High tone
Addres
1010/1100
Address
1011/1101
D4
Data bit
D3 D2 D1 D0
D4
Data bit
D3 D2 D1 D0
261.7 Hz
—
1
0
1
0
*
0
0
1
384 Hz
384.4 Hz
—
0
1
1
0
*
1
1
400 Hz
398.7 Hz
—
0
1
1
0
*
1
2000 Hz
2031.7 Hz
—
0
0
0
1
*
2600 Hz
2666.7 Hz
—
0
0
0
0
697 Hz
699.4 Hz
—
0
0
1
770 Hz
775.7 Hz
—
0
0
852 Hz
853.3 Hz
—
0
941 Hz
948.1 Hz
—
1209 Hz
1219.0 Hz
1336 Hz
Rated
reference
frequency
(generator
frequency)
Frequency
setting
262 Hz
n
Error
0
162
–0.11%
1
0
110
0.10%
0
1
0
106
–0.32%
0
1
0
0
20
1.56%
*
1
1
1
1
15
2.50%
1
*
1
1
0
0
60
0.34%
1
1
*
0
1
1
0
54
0.74%
0
1
1
*
0
0
0
1
49
0.15%
0
0
1
0
*
1
1
0
0
44
0.75%
—
0
0
1
0
*
0
0
1
0
34
0.82%
1333.3 Hz
—
0
0
0
1
*
1
1
1
1
31
–0.20%
1477 Hz
1471.3 Hz
—
0
0
0
1
*
1
1
0
0
28
–0.38%
1633 Hz
1641.0 Hz
—
0
0
0
1
*
1
0
0
1
25
0.48%
Note: • Setting values are BIN display values
• Error represents frequency setting error with respect to rated reference frequency.
12
MB86434
• Tone Output Waveform
The D4 data bit at address 1010, 1100 may be used to select either sine-wave or trapezoidal waveforms for tone
output.
VH
D4=0
Sine wave
output
VL
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
VH
D4= 1
Trapezoidal wave
output
VL
• Tone Output Control
Tone output may be controlled by address and through the external tone control input pin TONC. In addition, the
tone control offers a choice of sine or trapezoidal waveforms.
~
~
~
Address
1110
DATA — — — D 1—
(Tone ➀ control)
~
~
~
Address
1110
DATA — — — — D 0
(Tone ➁ control)
~
~
Dual tone
~
Single tone
~
SGC
~
TONEO
~
TONC
Single tone
: Disable
13
MB86434
Also, by connecting a capacitor between the TENV pin and the ground, it is possible to generate an envelope for
the tone waveform. Set address 0111 data bit D2 to 1 to generate. If an envelope is generated, silencing must be
applied by an L-level signal from the TONC pin. The type of envelope that can be generated can be calculated
approximately from the following formula.
Time t required for V0/V1 = 2.7 (in ms) = 15 * C (in µF)
V0
TENV
C
V1
TONEO
T
TONC
(inside IC)
Address0111
D2
• LED Output Controls
Output from the LED output pins can be controlled by the TONC signal and the address 1110 data bit D2. When
the TONC signal is H-level, and the address 1110 data bit D2 value is L-level, the output level will be high. Output
levels are CMOS levels.
Address 1110
DATA — — D 2 —
TONC
LED
: Disable
14
MB86434
• Tone Generator Control Output Level
(Condition: EV3 = 0 dB)
Address Address Tone generator
1110
0111
circuit operating
data bits data bits
mode
External pins
PSC2 PSC1 PSC0 TONC D2 D1 D0 D3 (SW2)
Tone
(1)
Tone
(2)
Output pin
mode
LED
TONEO
0
0
0
—
— — —
—
L
H-Z
1
0
0
—
— — —
—
L
H-Z
—
1 or 1
0
— — —
0
SGC
SGC
L
SGC
—
1 or 1
0
— — —
1
SGC
SGC
L
H-Z
—
1 or 1
1
1 — —
—
—
—
L
—
—
1 or 1
1
0 — —
—
—
—
—
1 or 1
1
— 1
1
0
SGC
SGC
—
1 or 1
1
— 1
0
0
SGC
—
1 or 1
1
— 0
1
0
—
1 or 1
1
— 0
0
0
: Operational,
SGC
Remarks
—
—
SGC
—
–10 dBv Single tone output
—
–10 dBv Single tone output
—
–10 dBv Dual tone output
: Power down, H-Z : High-impedance, L: L-level fixed, SGC: SGC fixed
Note: When the TONC pin signal is L-level, the tone generator circuit counters will be reset. When a dual tone is
generated at the time of reset, the initial phase settings for tone ➀ and tone ➁ will be in phase.
• Example: When Tone (1), Tone (2) are at the same frequency:
TONE
H
L
Tone (1)
SGC
Tone (2)
SGC
15
MB86434
(6) Codec
• Input/output
Both the µ-law and A-law coding/decoding conversion processes used by the MB86434 codec are compatible with
CCITT Recommendation G.711. In addition, linear coding in the form of 14-bit two’s complement code can be output
starting with MSB values.
SYNC
Din, Dout
MSB
MSB
Code
0 1 1 1 1 1 1 1 1
to
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
to
1 0 0 0 0 0 0 0 0
12
11
LSB
1 1 1 1 1 1 1
0 0 0 0 0 0 1
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 1
10
1
LSB
PTBO reference voltage (V)
1.1766
to
2.3986
2.4000
2.4014
to
3.6235
• The codec SYNC pin
The codec block requires the input of an 8 kHz sampling clock signal at the SYNC pin, as well as a data transfer
clock at the CLK pin. In order to conserve power consumption, whenever the SYNC pin or CLK pin signal is inactive,
the system goes into SYNC power-down mode and stops code conversion.
Also, if either the SYNC or CLK pins encounters jitter of 5 µs or greater, the system may go into power-down
mode.Table shows the status of output pins in SYNC power-down mode.
Pin symbol
SGC
SGO
VRH
DOUT
PTBO
BTPO
16
Operation
Normal operation (2.4 V)
Normal operation (2.4 V)
Normal operation (4.0 V)
H-level fixed
SGC
High impedance
MB86434
(7) Parallel Output
The LO0 to 3 pins carry latched output for external controls. The data written to address 1000 can be output through
these pins. Output is CMOS output.
D3
D2
D1
D0
Address 1000
LO0
LO1
LO2
LO3
(inside IC)
2. Analog Input
Analog input signals in the MB86434 include the two microphone inputs and the general-purpose analog switch.
(1) Microphone Amps
The microphone amps take the incoming signal from the microphones and amplify it to any desired level of gain.
The microphone lines are low-noise types for use with piezoelectric-ceramic or capacitor microphones, and are
capable of a wide range of amplification. All microphones and amps must be coupled with capacitors to prevent
amplification of offset signals.
Piezoelectric-ceramic type
MICO
–
+
MIC
Mic
XMIC
(inside IC)
AG
SGC
Capacitor type
V DD
MICO
–
+
MIC
Mic
XMIC
(inside IC)
SGC
AG
17
MB86434
Parameter
Characteristics (typ)
Unity gain frequency
1 MHz
Input conversion noise (BW = 300 - 3400 Hz)
3.1 mV
Maximum output level
1.25 - 3.75 VOP
Minimum load level
50 kΩ
(2) Analog Switches
The analog switches include on-chip general-purpose switches with 1 kΩ in-resistance. Switches are controlled by
writing to register address 0111 data bit D0, using H-level to make connections.
• Sidetone addition using analog switches
BBO
BTPI
BTPO
–
+
SWI
SGC
SW10
SWO
PTBO
IM1
OP1
–
+
IM2
SGC
OP2
–
(inside IC)
+
SGC
• SW10 = on
18
Address
A3 A2 A1 A0
Data bit
D4 D3 D2 D1 D0
0
— — — —
1
1
1
1
MB86434
3. Analog Output
The MB86434 has a total of four analog output circuits, including the three speaker drive circuits (receiver, earphone
and tone) and the accessory output.
(1) Speaker Drive Amp
The speaker drive amps include two circuits (receiver and tone) with BTL output and one system (earphone) with
single output. Because the speaker amp requires relatively high levels of power, it is connected to speaker selection
switches (sw6-sw9) for power-down mode selection.
Two systems (receiver and earphone) have fixed gain levels, while the other system (tone) allows gain adjustment
by means of external resistors.
In addition, the tone speaker amp is able to use the 200 mW large-current power circuit
Table
Parameter
Output type
Load resistance *1
Load resistance *2
Load capacity *2
Final stage gain
Maximum output power
*1:
*2:
Speaker Drive Amp Output Standards
Receiver speaker amps
(EAR, XEAR)
Earphone speaker amp
(JEAR)
Tone speaker amps
(TONE, XTONE)
BTL
32 Ω (typ)
2.8 kΩ (typ)
70 nF
6.0 dB
(between EAR-XEAR)
10 mW (min)
Single
32 Ω (typ)
2.8 kΩ (typ)
70 nF
0.0 dB/–6.0 dB
(JEAR)
5 mW (min)
BTL
32 Ω (typ)
2.8 kW (typ)
70 nF
–5 to 20 dB
(between TONE-XTONE)
200 mW (min)
Dynamic-type speaker
Piezoelectric-ceramic type speaker
19
MB86434
• Analog Output Connection Example
EAR
–
+
SGC
6.0
dB
Receiver speaker
Dynamic type: 32 Ω (typ)
Piezoelectric-ceramic type: 70 nF, 2.8 kΩ (typ)
R3
C3
R5
–
BBI
+
XEAR
SGC
0.0dB
R3
C3
JEAR
–6.0dB
Earphone speaker
Dynamic type: 32 Ω (typ)
Piezoelectric-ceramic type: 70 nF, 2.8 kΩ (typ)
–
+
R6
SGC
IMTON
R1
BBI
R2
TONE
–
Tone speaker
Dynamic type: 32 Ω (typ)
Piezoelectric-ceramic type: 70 nF, 2.8 kΩ (typ)
G = 20 LOG (2*R2/R1) [dB]
+
R4
C4
SGC
GdB
0dB
R5
–
+
XTONE
SGC
R4
C4
(inside IC)
Note: • R3, C3, R4, C4 should be given the respective values 80Ω, 0.01 µF in order to prevent unwanted oscillation.
• If a piezoelectric-ceramic type microphone is used, R5, R6 should be given the respective values 20 Ω, 10 Ω in order to
prevent unwanted oscillation.
• Tone Speaker Amp Not Used
IMTON
TONE
+
SGC
0dB
+
XTONE
SGC
(inside IC)
Note: When no tone speaker amp is used, the amp input IMTON and output TONE should be shorted together.
20
MB86434
(2) Accessory Output
The accessory output (RAUD pin) can carry either digital or analog output signals, and is controlled by address
0101 data bit D4 (SW 8), and address 0111 data bit D1 (SW 12).
When both SW 8 and SW 12 are in off position, the accessory outputline is in H-Z (high impedance) state. Caution:
never place both SW 8 and SW 12 in on position at the same time. This may cause the MB86434 to function
improperly.
• SW12 in On Position
DSDT
Digital signal input
SW 12
RAUD
Digital signal output
(digital signal not buffered)
(inside IC)
A4
0
Address
A3
A2
1
1
A1
D4
D3
1
—
—
Data bit
D2
D1
—
1
D0
—
• SW8 in On Position
SW 8
Analog input
BBI
RAUD
–
+
Analog output
5 kΩ
(inside IC)
SGC
A4
0
0
Address
A3
A2
1
1
0
0
Can be driven with load resistance
of 5 kΩ or greater
A1
D4
D3
0
1
0
0
*
*
Data bit
D2
D1
*
—
*
—
D0
—
—
21
MB86434
4. Receiver Connections
It is possible to add tones and adjust sidetones by using amp 1,2 and 3 and the electronic volume control. When
using amp 3, however, it is necessary to include HPF to avoid interference from the speaker amp DC.
• Tone and Sidetone Addition by Inclusion of Secondary LPF and Primary HPF.
R1
R2
IM1
C1
C2 C3
OP1
R3
R4 R5
–
+
PTBO
(receiving)
Secondary LPF
A = –R 2/R 3
ω/Q = 1/C 2* (1/R 1 +1/R 2 +1/R 3)
ω 2 = 1/ (R 1 R 3 C 1 C 2)
SGC
AMP1
SGC
OP1
C3
Signal addition
R 4 = R 5 = R 6 = R 7 = 100 kΩ
C 3 = C 4 = 0.1 µF
TONEO (tone)
BBO (sidetone)
IM2 R6
OP2
–
+
R7
C4
AMP2
SGC
EV2
–
+
BTO
C5
R8
IM3
BBI
R9
Primary HPF
A = –R 9/R 8
f c = 1/(2πC 5 R 8)
C 6 = 0.1 µF
C6
The following settings are
necessary to comply with CCITT
Recommendation
R 8 = R 9 = 100 kΩ
C 5 = 0.039 µF
IMTON
AMP3
SGC
(inside IC)
• Amp1, Amp2 not used
IM2
+
AMP2
IM1
OP2
SGC
+
AMP1
OP1
open
EV2
SGC
(inside IC)
BTO
(inside IC)
Note: When amps are not used, the amp input and output should be shorted together.
22
MB86434
• Tone and Sidetone Addition by Inclusion of Third-Order HPF
R 10
C8
C7
R11
IM1
PTBO
(receiving)
–
SGC
+
AMP1
OP1
C9
R 12 R 13
SGC
C 10
TONEO (tone)
BBO (sidetone)
IM2
OP2
Secondary HPF
A = –C 8/C 9
ω/Q = 1/ (R 10 C 9 C 7)* (C 7+C 8+C 9
ω 2 = 1/ (R 10 R 11 C 9 C 7)
R 14 R 15
C 11
Signal addition
R 12 = R 13 = R 14 = R 15 = 100 kΩ
C 10 = C 11 = 0.1 µF
–
+
AMP2
SGC
EV2
BTO
C 16
R 16
IM3
BBI
R 17
–
Primary HPF
A = –R 17/R 16
f c = 1/(2πC 16 R 16)
C 17 = 0.1 µF
C 17
IMTON
+
AMP3
SGC
(Inside IC)
23
MB86434
5. Power Saving Modes
(1) Mode Selection
The MB86434 power saving modes can be controlled by using the external control signal lines (3 lines). It is also
possible to apply power saving modes to the speaker amps with high power consumption levels by writing changes
to register settings. Whenever the MB86434 changes directly from a power-down mode to normal operating mode,
there is a possibility that speaker tones may be produced. The recommended sequence of coding changes to go
into normal mode is (VREF mode) → (Tone mode) → (Normal mode).
Power Saving Modes
Accessory
Tone
Earphone
Receiving
Sending
Receiving
TONE generator
BBI
CODEC
OP1
VREF generator
SW8 SW7 SW9 SW6 SW6 SW7 SW9 SW8
Operating circuit status
MICO BBO
JMICO VRH
D
SGC
SGO
OP2
BTO
PTBO
BTPO
D
DOUT
D
RAUD
D
TONE
XTONE
PS PSPS
C2 C1 C0 D4 D0
Output pin status
JEAR
Mode
Address
0110
EAR
XEAR
AdExternal Adpins
dress dress
Power
supply
current
(mA)
(typ)
SW6 SW7 SW9 SW8
All
Power- 0 0 0 — —
down
—
—
—
— ZA H-Z ZB H-Z H H-Z ZC H-Z H-Z H-Z
*
0.0005
VREF 1 0 0 — —
—
—
—
—
ZA H-Z ZB H-Z H
ZC H-Z H-Z H-Z
*
0.48
Tone
— 1 0 1
1
—
—
—
—
ZA H-Z ZB H-Z H
H-Z H-Z H-Z
1.8
— 1 0 0
1
0
1
1
1
ZA H-Z ZB
H
H-Z H-Z H-Z
2.4
ZB H-Z H
H-Z H-Z H-Z
4.5
H-Z H
H-Z H-Z H-Z
6.8
H-Z ZB H-Z H
H-Z H-Z H-Z
6.8
— 1 0 0
1
1
0
1
1
ZA
— 1 0 0
1
1
1
0
1
ZA H-Z
— 1 0 0
1
1
1
1
0
— — 1 0
0
0
1
1
1
ZA H-Z ZB
— — 1 0
0
1
0
1
1
ZA
Normal — — 1 0
0
1
1
0
1
ZA H-Z
— — 1 0
0
1
1
1
0
— — 1 0
0
0
0
0
0
8.2
ZB H-Z
10.3
H-Z
12.6
H-Z ZB H-Z
12.6
20.9
: Operational, ×: Power-down, H-Z: High impedance, H: H-level fixed
*
: High impedance may not be applied, depending on status of SW6, SW7, SW8.
ZA : EAR and XEAR are floating, however high resistance connection between EAR and XEAR.
ZB : TONE and XTONE are floating, however, high resistance connection between TONE and XTONE, and
between SGO and XTONE.
ZC : Floating, however high resistance connection between OP2 and BTO. Codec in [Normal] mode
operates with SYNC = 8 kHz, CLK = 2048 kHz.
• When RAUD is operating, address 0111 data bit D1 value should be “0” (SW12 off).
• In tone mode, address 0111 data bit D3 should be "0" (SW2 on), and address 0111 data bit D4 should be
“0” (SW14 off).
• When the SYNC and CLK pin signals are fixed at either L-level or H-level, part of the codec unit will go into
power-down mode. At this time the PTBO signal will be SGC level, BTPO will be H-Z, and VRH output will
be approximately 4.0 V.
Note: •
24
MB86434
■ TIMING CHART
• Codec-Related Signals
(1)
(2)
(3)
(4)
(5)
(7)
(6)
(8)
CLK
fC
f s *1
SYNC
i
ii
iii
iv
v
vi
1
2
3
4
5
6
vii
viii
DOUT
7
8
DIN
(1)
(2)
(3)
[Enlarged view]
(1)
(1)
(2)
CLK
t XS
t SX
SYNC
t WSH
i
ii
DOUT
t CO
(2)
(5)
t ZD
(6)
CLK
tF
tR
t DR
5
t RD
6
DIN
(3)
(7)
(8)
CLK
tWCH
t WCL
t DZ
t CO
vii
viii
DOUT
t DF
*1 From first CLK Down to second CLK Down, SYNC = H.
25
MB86434
• Microcomputer Data-Related Signals
XPRST
t WRE
A3
A2
A1
A0
D4
D3
D2
D1
D0
SRD
SRC
f SCLK
STB
LO 0 to 3
➃
[Enlarged view]
➃
SRD
t SSC
t HSC
D1
D0
t HCB
SRC
t WL
t SCB
STB
t DS
LO 0 to 3
t LD
26
t WH
MB86434
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Rating
Symbol
Min.
Max.
Unit
Power supply voltage
VS
–0.3
7.0
V
Analog input voltage
VAIN
–0.3
+VS + 0.3
V
Digital input voltage
VDIN
–0.3
+VS + 0.3
V
Storage temperature
Vstg
–55
+125
°C
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Pin name
Operating temperature
Ta
—
Power supply voltage
VS
Digital input voltage
Analog output load resistance
Analog output load capacity
Analog output load resistance*
Typ.
Max.
–20
+25
+80
°C
VDD, VDDAB, VDDAC,
VDDSP1 , VDDSP2
4.75
5.0
5.25
V
VL
All digital input pins
0.0
—
VS
V
RLB
BBO, PTBO, TONEO,
BTO, BTPO
75
—
—
kΩ
—
—
20
pF
—
32
—
Ω
—
—
70
nF
—
32
—
Ω
—
—
70
nF
—
32
—
Ω
—
—
70
nF
RLE
Analog output load capacity*2
CLE
Analog output load resistance*1
RLJ
Analog output load capacity*
2
Unit
Min.
CLB
1
Value
CLJ
Analog output load resistance*1
RLT
Analog output load capacity*2
CLT
Between EAR-XEAR
JEAR
Between TONE-XTONE
RLM1
MICO, JMICO
10
—
—
kΩ
RLM2
SGO, BBI, OP1, OP2
50
—
—
kΩ
Analog output load capacity
CLM
MICO, JMICO, SGO,
BBI, OP1, OP2
—
—
20
pF
Analog output load resistance*3
RLM
5
—
—
kΩ
Analog output load capacity*3
CLM
—
—
20
pF
All analog output pins
1.25
—
3.75
V
All analog input pins
1.25
—
3.75
V
Analog output load resistance
Analog output voltage
Analog input voltage
*1:
*2:
*3:
VAOUT
VAIN
RAUD
Dynamic typ speakers
Piezoelectric type speakers
When SW8 = on, SW12 = off
27
MB86434
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Pin
Conditions
Value
Min.
Typ.
Max.
Unit
Power supply current at
full power-down mode
IVSST1
PSC0 = 0 : PSC1 = 0 :
PSC2 = 0, Ain = AG,
Din = L
—
0.5
50
µA
Power supply current with
VREF operating
IVSST2
PSC0 = 0 : PSC1 = 0 :
PSC2 = 1, Ain = SGC,
Din = L
—
480
800
µA
Power supply current with
TONE operating
lVSST3
PSC0 = 0 : PSC1 = 1,
Ain = SGC, Din = ICN
SW6 = SW7 = SW8 =
SW9 = off
—
1.8
3.0
mA
Power supply current for
normal operation
(only speaker ampmute)
IVSST4
PSC0 = 1, Ain = SGC,
Din = ICN
SW6 = SW7 = SW9 = off
—
8.2
12.0
mA
lVSST5
PSC0 = 0, PSC1 = 1,
Ain = SGC, Din = ICN,
Power supply current
differential when SW6 is on/
off.
—
5.0
7.0
mA
lVSST6
PSC0 = 0, PSC1 = 1,
Ain = SGC, Din = ICN,
Power supply current
differential when SW7 is on/
off.
—
2.7
4.0
mA
lVSST8
PSC0 = 0, PSC1 = 1,
Ain = SGC, Din = ICN,
Power supply current
differential when SW9 is on/
off.
—
5.0
7.0
mA
VIH
—
VS×0.7
—
VS
V
—
0
—
VS×0.3
V
—
—
—
10
µA
—
—
—
10
µA
—
–10
—
10
mA
All VDD pins
Receiver amps
EAR, XEAR
Speaker
amp
Earphone amp
power
JEAR
supply
voltage
Tone amps
TONE, XTONE
Digital input voltage
Digital input current
Input offset voltage
VIL
IIH
All digital input
pins
IIL
VFM
Between
MIC-XMIC,
between
JMIC-XJMIC
(Continued)
28
MB86434
(Continued)
Parameter
Symbol
Pin
Conditions
Value
Min.
Typ.
Max.
Unit
VFR
RAUD
BBI = SGC
SW8 = on, SW6 = SW7 =
SW9 = SW12 = off
–15
—
15
mV
VFE
Between
EAR-XEAR
BBI = SGC
SW6 = on, SW7 = SW8 =
SW9 = SW12 = off
–20
—
20
mV
VFT
IMTON = SGC
Between
SW9 = on, SW6 = SW7 =
TONE-XTONE
SW8 = SW12 = off
–20
—
20
mV
VFP
PTBO
Din = ICN, EV2 = 0 dB
–100
—
100
mV
VOH
Between
MIC0-BBO
Between
JMIC0-BBO
EV0 = 0 dB
–100
—
100
mV
VOL
SGC output voltage
VSGC
SGC
—
2.30
2.40
2.50
V
SGO output voltage
VSGO
SGO
—
2.25
2.40
2.55
V
VRH output voltage
lVRH
VRH
—
—
4.0
—
V
Digital output voltage
VOH
All digital
output pins
IOH = – 0.5 mA
VS×0.8
—
VS
V
Digital output voltage
VOL
All digital
output pins
IOL = 0.5 mA
0.0
—
VS×0.2
V
Resistance between pins
SWI and SWO
RSW
Between
SWI-SWO
SW10
—
—
1
kΩ
Output offset voltage
Note: Measurement conditions: ■ Standard Test Circuit
29
MB86434
2. AC Characteristics
(1) Codec-Related Signals
Parameter
Symbol
Digital input rise time
tR
Digital input fall time
tF
Shift clock frequency
fC
Conditions
Value
Unit
Min.
Typ.
Max.
—
—
50
ns
—
—
50
ns
µ-law , A-law
64
—
3152
kHz
Linear
256
—
3152
kHz
VS×0.3→VS×0.7
Shift clock pulse width (H)
tWCH
VIH = VS×0.7
1/fC×0.3
—
1/fC×0.7
ns
Shift clock pulse width (L)
tWCL
VIL =VS× 0.3
1/fC×0.3
—
1/fC×0.3
ns
Sync frequency
fS
—
—
8
—
kHz
Sync pulse width
tWSH
—
1/fC
—
62
µs
SYNC to CLK setup time
tSX
—
100
—
—
ns
CLK to SYNC hold time
tXS
—
50
—
—
ns
CLK to DIN hold time
tRD
—
50
—
—
ns
DIN to CLK setup time
tDR
—
50
—
—
ns
SYNC to DOUT delay time
tZD
BIT 1
—
—
200
ns
CLK to DOUT delay time
tCO
BIT 2 to 8
—
—
200
ns
CLK to DOUT disable time
tDZ
“H”
—
—
200
ns
DOUT fall time
tDF
10
—
100
ns
—
(2) Microcomputer Data-Related Signals
Parameter
30
Symbol
Pin
Value
Unit
Min.
Typ.
Max.
50
—
—
ns
50
—
—
ns
50
—
—
ns
200
—
—
ns
200
—
—
ns
SRC to SRD data setup time
tSSC
SRC to SRD data hold time
tHSC
SRC to STB setup time
tSCB
SRC pulse width (H)
tWH
SRC pulse width (L)
tWL
STB pulse width
tDS
STB
50
—
—
ns
STB to SRC hold time
tHCB
STB, SRC
50
—
—
ns
LO0 to 3 delay time
tLD
LO0 to 3
—
—
200
ns
Shift clock frequency
fSCLK
SRC
—
—
2048
kHz
Reset pulse width
tWRE
XPRST
1
—
—
µs
SRD, SRC
SRC, STB
SRC
MB86434
3. Transmission Characteristics
(1) Microphone Amp System
Parameter
Symbol
Conditions
Gain
(between MIC0 and BBO)
GMB
Gain
(between JMIC0 and BBO)
Value
Unit
Min.
Typ.
Max.
MICO = –20 dBV, 1020 Hz
SW3 = on, CSW4 = SW5 = SW14 = off
EV 0 = 0 dB
–1.5
—
1.5
dB
GJB
JMICO = –20 dBV, 1020 Hz
SW4 = on, SW3 = SW5 = SW14 = off
EV 0 = 0 dB
–1.5
—
1.5
dB
Signal to noise ratio
(between MIC and BBO)
(between XMIC and BBO)
SMB
Ain1 = –40 dBV ( +20 dBgain)
SW3 = on, SW4 = SW5 = SW14 = off
EV0 = 0 dB, 1020 Hz C message
40
—
—
dB
Signal to noise ratio
(between JMIC and BBO)
(between XJMIC and BBO)
SJB
Ain2 = –40 dBV ( +20 dBgain)
SW4 = on, SW3 = SW5 = SW14 = off
EV0 = 0 dB, 1020 Hz C message
40
—
—
dB
Note: Measurement conditions: ■ Standard Test Circuit
(2) Speaker Amp System
Parameter
Symbol
Gain
(between EAR and XEAR)
GBE
Gain
(between BBI and JEAR)
Gain
(between BBI and RAUD)
Output power
Conditions
Value
Unit
Min.
Typ.
Max.
BBI = –20 dBV, 1020 Hz
—
6.0
—
dB
GBJ
BBI = –20 dBV, 1020 Hz, ATT = 0 dB
—
0.0
—
dB
GBJ6
BBI = –20 dBV, 1020 Hz, ATT = – 6 dB
—
–6.0
—
dB
GBR
BBI = –20 dBV, 1020 Hz
SW8 = on, SW6 = SW7 = SW12 = off
—
0.0
—
dB
WE
R = 32 Ω, between EAR-XEAR
THD = 10%
10.0
—
—
mW
WT
R = 25 Ω, between TONE-XTONE
gain = 0 dB, THD = 10%
200.0
—
—
mW
WJ
R = 32 Ω, JEAR, ATT = –2.5 dB
THD = 10%
5.0
—
—
mW
Note: Measurement conditions: ■ Standard Test Circuit
(3) TONE System
Parameter
TONE output level
(TONE0)
Symbol
Conditions
Value
Min.
Typ.
Max.
Unit
GT1
1 tone generated, SW2 = on
f1 = 948.1 kHz
—
–10.0
—
dBV
GT2
2 tone generated, SW2 = on
f1 = 948.1 kHz, f2 = 1219.1 kHz
—
–10.0
—
dBV
Note: Measurement conditions: ■ Standard Test Circuit
31
MB86434
(4) Electric Volume System
Parameter
Symbol
Conditions
Value
Min.
Typ.
Max.
Unit
Volume gain error
EV0
(between MICO-BBO)
GE0
SW3 = on, SW4 = SW14 = off
TAUD = –20 dBV, 1020 Hz
–0.7
—
0.7
dB
Volume gain error
EV1
(between DIN-PTBO)
GE1
DIN = –20 dBm0, 1020 Hz
–0.8
—
0.8
dB
Volume gain error
EV2
(between IM 2-BTO)
GE2
IM2 = –20 dBV, 1020 Hz
–1.0
—
1.0
dB
Volume gain error
EV3
(TONEO)
GE3
SW2 = on
1 tone generated
f1 = 948.1 kHz
–0.5
—
0.5
dB
Note: Measurement conditions: ■ Standard test circuit
(5) Sending/Receiving System (Codec, Analog Block)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Crosstalk
(send → receive)
CTX
Ain1 = 1020 Hz, – 40 dBV (20 dBgain)
DIN = ICN
Measured at RAUD pin
—
—
–50
dB
Crosstalk
(send → receive)
CTR
DIN = 1020 Hz, 0 dBm0
AIN = SGC
Measured at DOUT pin
—
—
–50
dB
Note: Measurement conditions: ■ Standard test circuit
32
Value
MB86434
(6) Codec
Parameter
Gain tracking
(A to D)
BTPO → DOUT
Gain tracking
(D to A)
DIN → PTBO
Gain tracking
(A to D) (Linear)
BTPO → DOUT
Gain tracking
(D to A) (Linear)
DIN → PTBO
Sending frequency
characteristics
(A to D)
BTPO → DOUT
Symbol
GTX
GTR
GTXL
GTRL
FRX
Value
Conditions
Typ.
Max.
+3 to –40 dBm0
–0.2
—
0.2
dB
–40 to –50 dBm0
–0.4
—
0.4
dB
–50 to –55 dBm0
–0.8
—
0.8
dB
+3 to –40 dBm0
–0.4
—
0.4
dB
–40 to –50 dBm0
–0.6
—
0.6
dB
–50 to –55 dBm0
–1.0
—
1.0
dB
AFST to AFST–43 dB
–0.2
—
0.2
dB
AFST–43 to AFST–53 dB
–0.4
—
0.4
dB
AFST–53 to AFST–53 dB
–0.8
—
0.8
dB
AFSR to AFSR–43 dB
–0.4
—
0.4
dB
AFSR–43 to AFSR–53 dB
–0.6
—
0.6
dB
AFSR–53 to AFSR–53 dB
–1.0
—
1.0
dB
0 to 60 Hz
24.0
—
—
dB
60 to 300 Hz –0.20
—
—
dB
300 to 3000 Hz –0.20
—
0.20
dB
3000 to 3400 Hz –0.20
—
0.8
dB
3400 to 4600 Hz
*
—
—
dB
32.0
—
—
dB
0 to 300 Hz –0.30
—
—
dB
300 to 3000 Hz –0.30
—
0.30
dB
3000 to 3400 Hz –0.30
—
1.10
dB
3400 to 4600 Hz
*
—
—
dB
32.0
—
—
dB
–2.0
0
–2.0
dB
Power supply variation
—
±0.02
—
dB
Temperature variation
—
±0.001
—
dB/°C
–2.50
0
2.50
dB
Power supply variation
—
±0.04
—
dB
Temperature variation
—
±0.002
—
dB/°C
Over load level µ-Law = 3.17 dB
A-Law = 3.14 dB
—
1.2081
—
VOP
1020 Hz, –10 dBm0
Reference value
1020 Hz, –10 dBm0
Reference value
EV1 = 0 dB
1020 Hz, AFST–3 dB
Reference value
1020 Hz, AFST–3 dB
Reference value
EV1 = 0 dB
0 dBm0
(Linear : AFST–3 dB)
1020 Hz
Reference value
4600 to 12 kHz
Receiving frequency
characteristics
(D to A)
DIN → PTBO
FRR
0 dBm0
(Linear : AFSR–3 dB)
1020 Hz
Reference value
EV1 = 0 dB
4600 to 12 kHz
Sending absolute
gain
(A to D)
BTPO → DOUT
Receiving absolute
gain (D to A)
DIN → PTBO
Absolute level
1020 Hz, 0 dBm0 (Linear : AFST–3 dB)
EV1 = 0 dB, VS = 3.0 V, Ta = +25°C
GAX
1020 Hz , 0 dBm0 (Linear : AFSR–3 dB)
VS = 3.0 V, Ta = +25°C
GAR
VABS
Unit
Min.
(Continued)
33
MB86434
(Continued)
Parameter
Symbol
Sending signal to
noise ratio
BTPO → DOUT
Receiving signal to
noise ratio
DIN → DOUT
Sending signal to
noise ratio
BTPO → DOUT
(Linear)
Max.
0 to –30 dBm0
34.0
—
—
dB
–40 dBm0
28.0
—
—
dB
–45 dBm0
23.0
—
—
dB
0 to –30 dBm0
33.0
—
—
dB
–40 dBm0
27.0
—
—
dB
–45 dBm0
22.0
—
—
dB
AFST–3 to AFST–33 dB
34.0
—
—
dB
AFST–43 dB
28.0
—
—
dB
AFST–45 dB
23.0
—
—
dB
1020 Hz
C message
(D to A)
AFSR–3 to AFSR–33 dB
34.0
—
—
dB
SDRL
AFSR–43 dB
28.0
—
—
dB
AFSR–45 dB
23.0
—
—
dB
Sending no-talk noise
ICNX
BTPO → DOUT
C message (A to D)
—
–72
–68
dBm0C
Receiving no-talk
noise
DIN → PTBO
ICNR
C message (D to A)
—
–72
–68
dBm0C
Analog input level
BTPO
AILU
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
µ-law
0.4692 0.5907 0.7437 Vrms
Analog output level
PTBO
AOLU
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
µ-law
0.4692 0.5907 0.7437 Vrms
Analog input level
BTPO
AILA
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
A-law
0.4728 0.5952 0.7493 Vrms
Analog output level
PTBO
AOLA
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
A-law
0.4728 0.5927 0.7493 Vrms
Analog input fullscale
level
AFST
BTPO
VS = 3.0 V, Ta = +25°C
Linear
0.9596 1.2081 1.5211
VOP
Analog output
fullscale level
PTBO
VS = 3.0 V, Ta = +25°C
Linear
0.9596 1.2081 1.5211
VOP
*: 14.5 × {1 – SIN
34
1020 Hz
C message
(A to D)
SDXL
Recieving signal to
noise ratio
BTPO → DOUT
(Linear)
Typ.
1020 Hz
C message
(D to A)
SDR
Unit
Min.
1020 Hz
C message
(A to D)
SDX
Value
Conditions
AFSR
π (4000 – f)
1200
}
MB86434
■ STANDARD TEST CIRCUIT
0.1 µF
100 kΩ
0.1 µF
100 kΩ
100 kΩ
0.1 µF
BTPO
VRH
BTPI
BBO
MICO
0.1 µF
100 kΩ
SGC
–
0.1 µF
EV0
+
SGO
Dout
DOUT
8 kHz
SYNC
2MHz
CLK
MIC
Ain1
10 kΩ
XMIC
SGC
JMICO
CODEC
100 kΩ
–
EV1
10 kΩ
+
DIN
Din
Ain2
JMIC
XJMIC
SGC
PTBO
100 kΩ
SWI
100 kΩ
0.1 µF
100 kΩ
IM1
AMP1
OP1
AMP2
SWO
TENV
EV2
100 kΩ
100 kΩ
1 µF
IM2
OP2
0.039 µF
DSDT
BTO
AMP3
100 kΩ
RAUD
IM3
EAR
100 kΩ
BBI
0.1 µF
XEAR
32 Ω
TONEO
22 µF
TCLK
32 Ω
JEAR
EV3
TONE
TONC
IMTON
100 k Ω
100 k Ω
TONE
DATA LATCH
P SAVE
0.1 µF
SRD SRC STB XPRST
: Digital input
: Digital output
LO0 LO1 LO2 LO3 PSC0 PSC1 PSC2 LED
: Analog input
: Analog output
XTONE
: Input/output
32 Ω
: V DD
: GND
Note: Sufficient path capacitance must be placed between VDDAB–BAG, VDDAC–CAG, VDDSP1–SPG1, VDDSP2–SPG2,
VDD–AG.
35
MB86434
■ ORDERING INFORMATION
Part number
MB86434PF
36
Package
64 pins, Plastic QFP
(FPT-64P-M07)
Remarks
MB86434
■ PACKAGE DIMENSION
64 pin Plastic QFP
(FPT-64P-M07)
25.70 ± 0.40 (1.012 ± .016)
3.35 (.132) MAX
(Mounting height)
33
0.05 (.002) MIN
(STAND OFF)
20.00 ± 0.20 (.787 ± .008)
51
52
32
19.70 ± 0.40
(.776 ± .016)
16.30 ± 0.40
(.642 ± .016)
14.00 ± 0.20
(.551 ± .008)
12.00 (.472)
REF
20
"A"
64
LEAD No.
1
19
1.00 (.0394)
TYP
0.40 ± 0.10
(.016 ± .004)
0.15 ± 0.05
(.006 ± .002)
0.20 (.008) M
Details of "A" part
Details of "B" part
0.25 (.010)
"B"
0.30 (.012)
0~10°
0.15 (.006)
18.00 (.709) REF
22.30 ± 0.40 (.878 ± .016)
C
1994 FUJITSU LIMITED F64014S-3C-2
0.18 (.007)
MAX
0.63 (.025)
MAX
1.70 ± 0.20
(.067 ± .008)
Dimensions in mm (inches).
37
MB86434
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9702
FUJITSU LIMITED Printed in Japan
38