Ordering number : ENA2000 CMOS IC LC74900 Silicon gate LCD PROCESSOR LSI for small size display Overview LC74900 is a highly integrated multi-purpose LCD Panel (up to WVGA) controller processing analog and digital video signal. It contains A/D converter, video decorder, De-interlacer/Scaler, and picture improvement. Features (1) Video Input/Output • Analog input: 4ch CVBS (NTSC, PAL, and SECAM) with 1ch 10bit A/D converter • Digital input: 24bit RGB and YCbCr, 16bit YCbCr (4:2:2), and 8bit YC (BT.656) • Digital output: 8bit video decoder output (BT.656) (2) YC separation video decoder • Adaptive 3line comb filter, automatic gain and chrominance control (3) De-interlacer and Scaler • Horizontal and vertical programmable scaler separately, and supports panels up to WVGA resolutions (4) Picture Improvements • CDEX (Color Depth Expander): high quality expansion for low-resolution graphics • Dynamic gamma correction: picture adapted automatic luminance control • Sharpness control, LTI and CTI: peaking enhancement without glares • Color exciter: 6 phases RGBYMC gain control separately (5) Panel interface • 24bit RGB output and 18bit RGB output with dithering process • Pulse Width Modulation for automatic LED backlight control • Timing conroller for LCD driver with horizontal or vertical reversing signals • Pin swapping : replace output pin assignment of the RGB channel or bit Continued on next page. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. 30712HKPC 20120113-S00002,S00003 No.A2000-1/14 LC74900 Continued from preceding page. (6) On Screen Display • Built-in OSD controller with integrated font ROM, which contains 501 fonts, and fomt RAM, which contains 8 fonts • Character Numbers displayed on the screen: 24 characters by 8 rows, 24 characters by 10 rows, or 32 characters by 8 rows • Character Size: 16 pixels wide by 20 pixels high • Character Colors: 8 font colors for each character, 8 back colors for each character, and 8 font border colors for each row • Inverting font colors and back colors each character, Blinking fonts each character, and Fringing each row • Pin assignment for an optional external OSD controller: 24bit, 18bit, 12bit, and 6bit RGB (7) EEPROM booting • Quick boot from an external EEPROM in power on sequence before starting a system controller • Waiting timer between data transfers • Verifying boot datas • EEPROM Size: Up to 512K bits with I2C or SPI interface (8) Parallel data outputs, panel interface and video decorder output • Reentering video decoder outputs, which are processed by an external graphic engine as digital inputs (9) System Controller Interface • SPI (Max 1Mbit/s) or I2C bus (100Kbit/s or 400Kbit/s) LSI Specification • Supply voltage: 1.5V (core), 3.3V (IO) • Maximum operation frequency: 60MHz (video processing) • Package: 120pin TQFP Applications • For mediam or small size LCD Panel • Automobile use: car TV, portable navigation, etc. • Home use: Photo Frame, Portable DVD, Door Phone, etc. No.A2000-2/14 LC74900 Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, ADC0AVSS = 0V, ADC1AVSS = 0V, PLLAVSS = 0V, XVSS = 0V Parameter Maximum supply voltage (I/O) Symbol Conditions Ratings XVDD33 DVDD3318 Maximum supply voltage (Analog) unit DVDD33 ADC0AVDD33 ADC1AVDD33 -0.3 to +3.96 V -0.3 to +3.96 V -0.3 to +1.8 V PLLAVDD33 Maximum supply voltage (Core) DVDD15 Digital input voltage VI -0.3 to DVDD33+0.3 -0.3 to DVDD3318+0.3 VI (5V Tolerant) Digital output voltage V -0.3 to +5.6 VO -0.3 to DVDD33+0.3 -0.3 to DVDD3318+0.3 Ta = 85°C, With evaluation board* V Maximum allowable loss Pd max 0.7 W Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C *: Board size: 150mm × 150mm × 1.6mm, FR-4, 6layers Allowable Operation Ranges at Ta = -40 to +85°C, DVSS = 0V, ADC0AVSS = 0V, ADC1AVSS = 0V, PLLAVSS = 0V, XVSS = 0V Parameter Supply voltage (I/O) Supply voltage (Analog) Symbol min typ max unit 3.15 3.3 3.45 V DVDD3318 3.15 3.3 3.45 V 1.7 1.8 1.9 V 3.15 3.3 3.45 V 1.4 1.5 ADC0AVDD33 ADC1AVDD33 PLLAVDD33 Supply voltage (Core) DVDD15 Input voltage range VIN Input voltage range VIN5 (5V Tolerant) Conditions DVDD33 XVDD33 1.6 V 0 DVDD33 DVDD3318 V 0 5.5 V No.A2000-3/14 LC74900 DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, ADC0AVSS = 0V, ADC1AVSS = 0V, PLLAVSS = 0V, XVSS = 0V, DVDD33 = 3.15V to 3.45V, DVDD3318 = 3.15V to 3.45V or 1.7V to 1.9V, DVDD15 = 1.42V to 1.58V, XVDD33 = 3.15V to 3.45V, ADC0AVDD = 3.15V to 3.45V, ADC1AVDD = 3.15V to 3.45V, PLLAVDD = 3.15V to 3.45V Parameter Input high-level voltage Symbol VIH Conditions CMOS level inputs CMOS level Schmitt inputs Input low-level voltage VIL CMOS level inputs CMOS level Schmitt inputs Input high-level current IIH min typ max unit 0.7DVDD33 0.7DVDD3318 V 0.7DVDD33 V 0 0.3DVDD33 0.3DVDD3318 V 0 0.3DVDD33 V VI = DVDD33 μA VI = DVDD3318 μA μA Input low-level current IIL VI = DVSS Output high-level voltage VOH Type B: IOH = -4mA Type G: IOH = -6mA DVDD33-0.6 V DVDD3318-0.6 V DVDD3318-0.4 V DVDD3318 = 3.15V to 3.45V Type J: IOH = -4mA Type K: IOH = -6mA DVDD3318 = 1.7V to 1.9V Type J: IOH = -3mA Type K: IOH = -5mA Output low-level voltage VOL CMOS Output leakage current IOZ When in high-impedance output mode Operating current drain IDDOP Output open, tck = 9MHz, 10steps -10 0.4 V 10 μA Ta = 25°C, DVDD33 = 3.3V, DVDD3318 = 3.3V, XVDD = 3.3V, DVDD15 = 1.5V, ADC0AVDD = 3.3V, ADC1AVDD = 3.3V, PLLAVDD = 3.3V 95 mA 139 mA 34 μA Output open, tck = 33MHz, 10steps Ta = 25°C, DVDD33 = 3.3V, DVDD3318 = 3.3V, XVDD = 3.3V, DVDD15 = 1.5V, ADC0AVDD = 3.3V, ADC1AVDD = 3.3V, PLLAVDD = 3.3V Static current drain IDDST Output open, tck: stop VI = DVSS, Ta = 25°C, DVDD33 = 3.3V, DVDD3318 = 1.8V, XVDD = 3.3V, DVDD15 = 1.5V, ADC0AVDD = 3.3V, ADC1AVDD = 3.3V, PLLAVDD = 3.3V No.A2000-4/14 LC74900 Package Dimensions unit : mm (typ) 3257A 14.0 16.0 0.5 16.0 14.0 120 1 0.4 0.15 0.125 0.1 1.2MAX (1.0) (1.2) SANYO : TQFP120(14X14) No.A2000-5/14 LC74900 95 100 105 110 90 5 85 10 80 Top View 15 LC74900 75 20 70 25 65 60 55 50 45 40 35 30 DGOUT3 DGOUT2 DGOUT1 DGOUT0 DBOUT7 DBOUT6 DVDD33 DBOUT5 DBOUT4 DBOUT3 DBOUT2 DBOUT1 DVDD15 DBOUT0 DROUT7 DROUT6 DROUT5 DROUT4 DVSS DCKO1 DVDD33 DROUT3 DROUT2 DROUT1 DROUT0 DVSS DYGIN7 DYGIN6 DYGIN5 DYGIN4 PLLAVDD33 PDO PLLAVSS33 XVDD33 XTALI XTALO XVSS DVDD15 MODE0 DCKI MODE1 XMUTE INTO DDEI DVSI DHSI DVDD33 DCBIN0 DCBIN1 DCBIN2 DCBIN3 DCBIN4 DCBIN5 DVSS DCBIN6 DCBIN7 DYGIN0 DYGIN1 DYGIN2 DYGIN3 DVDD15 XRST XPDWN GP0 GP1 GP2 DVDD33 DVSS SCK_SCL SRXD_SDA STXD SCS_I2SEL SIOSEL MODE2 MODE3 TEST REFPKV VRT REFNKV VRB ADC0AVDD33 AIN4 ADC0AVSS33 AIN3 ADC1AVDD33 AIN2 ADC1AVSS33 AIN1 SVO LPFO 115 120 DCRIN7 DCRIN6 DCRIN5 DCRIN4 DVSS DCKO2 DVDD3318 DCRIN3 DCRIN2 DCRIN1 DCRIN0 DVDD15 GRST FLM OE CPV STRB SP DVDD33 POL PWM DEXR DDEO DVSO DVSS DHSO DGOUT7 DGOUT6 DGOUT5 DGOUT4 Pin Assignment No.A2000-6/14 LC74900 Block Diagram LC74900 AIN1 DYGIN[7:0] DROUT[7:0] DHSO/SP2 DVSO/FLM2 DDEO DCKO OSD DCBIN[7:0] DBOUT[7:0] OSD Mix Picture Quality Improvement De-Interlacer & Scaler Video Decoder 1ch 10bit ADCs & AFE AIN3 AIN4 DGOUT[7:0] MUX AIN2 TCON DCRIN[7:0] SP MPU POL PWM XMUTE INTO STXD SCS_I2SEL SPI/ 2 IC SCK_SCL SRXD_SDA XTALI XTALO DEXR PWM XRST PLL OE STRB LCD Back Light Controler DDEI DCKI FLM CPV PANEL Protection Timing Controler DVSI MUX DHSI GRST EEPROM No.A2000-7/14 LC74900 Pin Functions Pin No. Digital I/O format Pin symbol Connected to I/O Format Remarks IO power supply 1 DVDD15 P - Core voltage Digital 2 XRST I A CMOS Digital DVDD33 Reset pin (active at a low voltage level) Power supply for core (1.5V) 3 XPDWN I A CMOS Digital DVDD33 Fixed at a high voltage level 4 GP0 I/O B CMOS Digital DVDD33 5 GP1 I/O B CMOS Digital DVDD33 6 GP2 I/O B CMOS Digital DVDD33 7 DVDD33 P - IO voltage Digital Input: Digital input/OSD enable (pull down if not used) Output: Global port/Video decoder Vsync Input: Digital input/OSD halftone (pull down if not used) Output: Global Port/Video DecoderHsync Global port output Power supply for IO (3.3V) 8 DVSS P - GND Digital 9 SCK_SCL I/O C CMOS Digital DVDD33 I2C: I2C Clock inout, SPI: Clock input 10 SRXD_SDA I/O C CMOS Digital DVDD33 I2C: data inout, SPI: data input 11 STXD I/O B CMOS Digital DVDD33 SPI: data output 12 SCS_I2SEL I A CMOS Digital DVDD33 I2C: Select I2C slave address, SPI: Chip select 13 SIOSEL I D CMOS Digital DVDD33 Select CPU I/F, ”L”: I2C, ”H”: SPI 14 MODE2 I D CMOS Digital DVDD33 Operation mode control 15 MODE3 I D CMOS Digital DVDD33 Operation mode control 16 TEST I D CMOS Digital DVDD33 For production test (Fixed at a low voltage level) 17 REFPKV I E Analog Top reference level Buffer-AMP input for ADC 18 VRT I E Analog Top reference level for ADC 19 REFNKV I E Analog Bottom reference level Buffer-AMP input for ADC 20 VRB I E Analog Bottom reference level for ADC 21 ADC0AVDD33 P - 22 AIN4 I E 23 ADC0AVSS33 P - Analog voltage GND GND for digital Analog Power supply for ADC (3.3V) Analog CVBS input 4 Analog GND for ADC Analog CVBS input 3 24 AIN3 I E 25 ADC1AVDD33 P - 26 AIN2 I E 27 ADC1AVSS33 P - 28 AIN1 I E 29 SVO O E Analog AFE output 30 LPFO O E 31 PLLAVDD33 P - 32 PDO O - 33 PLLAVSS33 P - 34 XVDD33 P - 35 XTALI I F CMOS Digital XVDD33 36 XTALO O F CMOS Digital XVDD33 37 XVSS P - GND Digital GND for 27MHz X’tal 38 DVDD15 P - Core voltage Digital Power supply for core (1.5V) 39 MODE0 I D CMOS Digital DVDD33 Operation mode control 40 DCKI I D CMOS Digital DVDD33 Digital video clock 41 MODE1 I D CMOS Digital DVDD33 Operation mode control 42 XMUTE I A CMOS Digital DVDD33 Mute control (active at a low voltage level) 43 INTO I/O B CMOS Digital DVDD33 Interrupt output 44 DDEI I D CMOS Digital DVDD33 Digital video enable/OSD enable 45 DVSI I D CMOS Digital DVDD33 Digital video Vsync/OSD half tone DVDD33 Digital video Hsync Analog voltage GND Analog Power supply for ADC (3.3V) Analog CVBS input 2 Analog GND for ADC Analog CVBS input 1 Analog External AGC control level Analog Power supply for PLL (3.3V) Analog Test port for PLL (Open) GND Analog GND for PLL IO voltage Digital Analog voltage Power supply for 27MHz X’tal (3.3V) 27MHz X’tal input 27MHz X’tal output 46 DHSI I D CMOS Digital 47 DVDD33 P - IO voltage Digital 48 DCBIN0 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 49 DCBIN1 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 50 DCBIN2 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) Power supply for IO (3.3V) Continued on next page. No.A2000-8/14 LC74900 Continued from preceding page. Pin No. Digital I/O format Pin symbol Connected to I/O Format Remarks IO power supply 51 DCBIN3 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 52 DCBIN4 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 53 DCBIN5 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 54 DVSS P GND Digital 55 DCBIN6 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 56 DCBIN7 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 57 DYGIN0 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 58 DYGIN1 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 59 DYGIN2 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 60 DYGIN3 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 61 DYGIN4 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 62 DYGIN5 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used)) 63 DYGIN6 I D CMOS Digital DVDD33 Digital video input/OSD input (pull down if not used) 64 DYGIN7 I D CMOS Digital DVDD33 65 DVSS P GND Digital 66 DROUT0 I/O B CMOS Digital DVDD33 Panel R output (LSB) (input port in test mode) 67 DROUT1 I/O B CMOS Digital DVDD33 Panel R output (input port in test mode) 68 DROUT2 I/O B CMOS Digital DVDD33 Panel R output (input port in test mode) 69 DROUT3 I/O B CMOS Digital DVDD33 Panel R output (input port in test mode) 70 DVDD33 P 71 DCKO1 O DVDD33 Panel clock output IO voltage Digital G CMOS Digital GND for digital Digital video input/OSD input (pull down if not used) GND for digital Power supply for IO (3.3V) 72 DVSS P GND Digital 73 DROUT4 I/O B CMOS Digital DVDD33 GND for digital Panel R output (input port in test mode) 74 DROUT5 I/O B CMOS Digital DVDD33 Panel R output (input port in test mode) 75 DROUT6 I/O B CMOS Digital DVDD33 Panel R output (input port in test mode) 76 DROUT7 I/O B CMOS Digital DVDD33 Panel R output (MSB) (input port in test mode) 77 DBOUT0 I/O B CMOS Digital DVDD33 Panel B output (LSB) (input port in test mode) 78 DVDD15 P Core voltage Digital 79 DBOUT1 I/O B CMOS Digital DVDD33 Panel B output (input port in test mode) 80 DBOUT2 I/O B CMOS Digital DVDD33 Panel B output (input port in test mode) 81 DBOUT3 I/O B CMOS Digital DVDD33 Panel B output (input port in test mode) 82 DBOUT4 I/O B CMOS Digital DVDD33 Panel B output (input port in test mode) 83 DBOUT5 I/O B DVDD33 Panel B output (input port in test mode) 84 DVDD33 P 85 DBOUT6 I/O 86 DBOUT7 I/O 87 DGOUT0 88 Power supply for core (1.5V) CMOS Digital IO voltage Digital B CMOS Digital DVDD33 Panel B output (input port in test mode) B CMOS Digital DVDD33 Panel B output (MSB) (input port in test mode) I/O B CMOS Digital DVDD33 Panel G output (LSB) (input port in test mode) DGOUT1 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 89 DGOUT2 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 90 DGOUT3 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 91 DGOUT4 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 92 DGOUT5 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 93 DGOUT6 I/O B CMOS Digital DVDD33 Panel G output (input port in test mode) 94 DGOUT7 I/O B CMOS Digital DVDD33 Panel G output (MSB) (input port in test mode) 95 DHSO I/O B CMOS Digital DVDD33 96 DVSS P GND Digital 97 DVSO I/O B CMOS Digital DVDD33 98 DDEO I/O B CMOS Digital DVDD33 99 DEXR I/O B CMOS Digital Power supply for IO (3.3V) Panel Hsync/Start pulse for source driver/ Video decoder Vsync output (input port in test mode) GND for digital DVDD33 Panel Vsync/Start pulse for gate driver/ Video decoder Vsync output (input port in test mode) Panel enable output (input port in test mode) Invert control signal for DTR/ Video decorer output 1[7](BT.656) (input port in test mode) Continued on next page. No.A2000-9/14 LC74900 Continued from preceding page. Pin No. 100 Digital I/O format Pin symbol PWM Connected to I/O Format I/O B 101 POL I/O 102 DVDD33 P B supply CMOS Digital CMOS Digital IO voltage Digital DVDD33 DVDD33 SP I/O B CMOS Digital DVDD33 104 STRB I/O B CMOS Digital DVDD33 105 CPV I/O B CMOS Digital DVDD33 106 OE I/O B CMOS Digital DVDD33 107 FLM I/O B CMOS Digital DVDD33 108 GRST I/O B CMOS Digital DVDD33 109 DVDD15 P Core voltage Digital DCRIN0 I/O H CMOS Digital DVDD3318 111 DCRIN1 I/O H CMOS Digital DVDD3318 I/O H CMOS Digital Video decoder output 1[6] (BT.656) (input port in test mode) Start pulse for source driver/ Video decoder output 1[5] (BT.656) (input port in test mode) Data stroboscope for source driver/ Video decoder output 1[4] (BT.656) (input port in test mode) Clock for gate driver/ Video decoder output 1[3] (BT.656) (input port in test mode) Output enable for gate driver/ Video decoder output 1[2] (BT.656) (input port in test mode) Start pulse for gate driver/ Video decoder output 1[1] (BT.656) (input port in test mode) Reset for gate driver/ Video decoder output1[0] (BT.656) (input port in test mode) Power supply for core (1.5V) 110 DCRIN2 Pulse width modulation (input port in test mode) Polarity control for source driver/ Power supply for IO (3.3V) 103 112 Remarks IO power DVDD3318 113 DCRIN3 I/O H CMOS Digital DVDD3318 114 DVDD3318 P - IO voltage Digital 115 DCKO2 O J CMOS Digital 116 DVSS P - GND Digital 117 DCRIN4 I/O H CMOS Digital DVDD3318 118 DCRIN5 I/O H CMOS Digital DVDD3318 119 DCRIN6 I/O H CMOS Digital DVDD3318 120 DCRIN7 I/O H CMOS Digital DVDD3318 Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[0] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[1] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[2] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[3] (BT.656) Power supply for IO (3.3V/1.8V) DVDD3318 Video decoder clock output GND for digital Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[4] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[5] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[6] (BT.656) Input: Digital video input/OSD input (pull down if not used) Output: Video decoder output 2[7] (BT.656) No.A2000-10/14 LC74900 Pin Type I/O type A Function Schmitt trigger Equivalent circuit Applicable pins XRST,XPDWN,SCS_I2SEL,XMUTE CMOS input B 8mA GP0,GP1,GP2,STXD,INTO, 3-STATE drive DROUT0,DROUT1,DROUT2,DROUT3, CMOS I/O DROUT4,DROUT5,DROUT6,DROUT7, DBOUT0,DBOUT1,DBOUT2,DBOUT3, DBOUT4,DBOUT5,DBOUT6,DBOUT7, DGOUT0,DGOUT1,DGOUT2,DGOUT3, DGOUT4,DGOUT5,DGOUT6,DGOUT7 DVSO,DHSO,DDEO,DEXR, PWM,POL,SP,STRB, CPV,OE,FLM,GRST C 8mA SCK_SCL,SRXD_SDA OpenDrain output CMOS input* D CMOS input SIOSEL,MODE2,MODE3,TEST,MODE0, DCKI,MODE1,DDEI,DVSI,DHSI, DCBIN0,DCBIN1,DCBIN2,DCBIN3, DCBIN4,DCBIN5,DCBIN6,DCBIN7, DYGIN0,DYGIN1,DYGIN2,DYGIN3, DYGIN4,DYGIN5,DYGIN6,DYGIN7 E Analog I/O REFPKV,VRT,REFNKV,VRB,AIN4, AIN3,AIN2,AIN1,SVO,LPFO F Oscillator circuit I/O XTALI,XTALO G 12mA DCKO1 3-STATE drive CMOS output H 3.3V: 8mA DCRIN0,DCRIN1,DCRIN2,DCRIN3, 1.8V: 3mA DCRIN4,DCRIN5,DCRIN6,DCRIN7 3-STATE drive CMOS I/O J 3.3V: 12mA DCKO2 1.8V: 5mA 3-STATE drive CMOS output No.A2000-11/14 LC74900 I/O Data Timing (1) Input data timing tCK tHI DVDD33/2 DCKI tSU tLI tHD DVDD33/2 Input data Pin name Parameter Clock cycle DCKI Symbol tCK min typ max unit 16.7 ns Duty 50 % Input data setup time DCRIN*, DYGIN*, DCBIN*, DVSI, DHSI, DDEI (DVDD33 = 3.15V to 3.45V) (DVDD3318 = 3.15V to 3.45V) tSU 3 ns tHD 2 ns Input data hold time (DVDD33 = 3.15V to 3.45V) (DVDD3318 = 3.15V to 3.45V) * The recommended duty ratio of input clock is 50% (2) Output data timing tHO tCK DVDD33/2 DCKO1 tAC tLO DVDD33/2 Output data Pin name Parameter Clock cycle DCKO1 Symbol tCK min typ max unit 16.7 ns Duty 50 DROUT*, DGOUT*, DBOUT* Output data delay time DVSO, DHSO, DDEO, DEXR, POL, DVDD33 = 3.15V to 3.45V tAC % -3 3 ns SP, STRB, CPV, OE, FLM, GRST * DCKO1 output is not inverted. Output capacitance: 15pF tHO tCK DVDD3318/2 DCKO2 tAC tLO DVDD3318/2 Output data Pin name Parameter Clock cycle DCKO2 Output data delay time STRB, CPV, OE, FLM, GRST, DVDD3318 = 3.15V to 3.45V DVDD33 = 3.15V to 3.45V DCRIN* tCK min typ Output data delay time DVDD3318 = 1.7V to 1.9V max unit 37 Duty DCRIN*, DEXR, POL, SP GP0, GP1, DVSO, DHSO Symbol ns 50 % tAC -3 3 ns tAC -6 6 ns * DCKO1 output is not inverted. Output capacitance: 15pF No.A2000-12/14 LC74900 Connection Example of Parallel Output Mode (Panel/Video Decoder) * For details, see Application Note. CVBS AIN1 AIN2 AIN3 AIN4 0.1μF A3.3V Ferrite AGND ADC connection (Power supply, Filter, etc.) open INTO Interrupt output PWM LCD backlight control CVBS input (4 to 1 select) SVO ADC0AVDD33 ADC1AVDD33 ADC0AVSS33 ADC1AVSS33 LPFO 0.1μF AGND GRST FML OE CPV STRB SP POL DEXR TCON 10μF REFPKV VRT VRB REFNKV 0.1μF 10μF AGND Video decoder output ITU-R BT.656 8bit 8 8 8 Digital video RGB 18bit input DCKO2 DCRIN0-7 DCBIN0-7 DYGIN0-7 GP0 GP1 DCKI DDEI DVSI DHSI TEST DGND MODE3 MODE2 MODE1 MODE0 SIOSEL GP2 SCS_I2SEL STXD SRXD_SDA SCK_SCL Operation mode control D3.3V I2C bus interface DCKO1 DDEO DVSO DHSO DROUT0 DROUT1 DROUT2 DROUT3 DROUT4 DROUT5 DROUT6 DROUT7 Panel output (R) (*)if 6bit outputs, DROUT1-0 is opened DBOUT0 DBOUT1 DBOUT2 DBOUT3 DBOUT4 DBOUT5 DBOUT6 DBOUT7 Panel output (B) (*)if 6bit outputs, DROUT1-0 is opened DGOUT0 DGOUT1 DGOUT2 DGOUT3 DGOUT4 DGOUT5 DGOUT6 DGOUT7 Panel output (G) (*)if 6bit outputs, DROUT1-0 is opened A3.3V Mute control (Active low level) XMUTE Reset (Active low level) XRST Ferrite PLL connection (Power supply, etc.) PLLAVDD33 open PDO PLLAVSS33 D3.3V AGND XPDWN CL1 XTALI DVDD3318 DVDD33 DVDD15 CL2 XTALO Rd DGND 27MHz fundamental Crystal Oscillator Sync clock output D3.3V or 1.8V D3.3V D1.5V Ferrite Ferrite Ferrite Digital power supply DVSS33 DGND No.A2000-13/14 LC74900 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2012. Specifications and information herein are subject to change without notice. PS No.A2000-14/14