an1179

Using the ISL6420A PWM Controller
Evaluation Board
®
Application Note
Advanced Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6420A simplifies the implementation of a complete
control and protection scheme for a high-performance
DC/DC buck converter. It is designed to drive N-channel
MOSFETs in a synchronous rectified buck topology. The
control, output adjustment, monitoring and protection
functions into a single package.
The ISL6420A provides simple, single feedback loop,
voltage mode control with fast transient response. The
output voltage of the converter can be precisely regulated to
as low as 0.6V, with a maximum tolerance of ±1.0% over
temperature and line voltage variations.
The operating frequency is fully adjustable from 100kHz to
1.4MHz. High frequency operation offers cost and space
savings.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate that enables high converter
bandwidth for fast transient response. The resulting PWM
duty cycle ranges from 0% to 100%. The capacitor value
from the ENSS pin to ground sets the time duration for the
PWM soft-start. Pulling the ENSS pin LOW disables the
controller.
The ISL6420A monitors the output voltage and generates a
PGOOD (power good) signal when soft-start is complete and
the output is within regulation. A built-in overvoltage
protection circuit prevents the output voltage from going
above typically 115% of the set point. Protection from
overcurrent conditions is provided by monitoring the rDS(ON)
of the upper MOSFET to inhibit the PWM operation
appropriately. This approach simplifies the implementation
and improves efficiency by eliminating the need for a current
sensing resistor. The IC also features voltage margining for
networking DC/DC converter applications.
ISL6420A Reference Design
The ISL6420A evaluation boards illustrates the operation of
the IC in an embedded application. Two versions of the
evaluation board, based on the package type, are listed in
Table 1. Both are configured for an output voltage of 3.3V
and 10A maximum load.
TABLE 1.
BOARD NAME
IC
PACKAGE
ISL6420AEVAL1Z
ISL6420AIAZ
20 Ld QSSOP
ISL6420AEVAL3Z
ISL6420AIRZ
20 Ld QFN
1
September 15, 2006
AN1179.1
Quick Start Evaluation
The evaluation board is shipped “ready to use” right from the
box. Both boards have been optimized for a 12V input from a
standard power supply but can accept a range from 4.5V to
5.5V or 5.5V to 28V as desired. Standoff terminals have
been provided in order to connect the input source and the
load.
Recommended Test Equipment
To test the functionality of the ISL6420A, the following
equipment is recommended:
•
•
•
•
An adjustable 30V, 8A capable bench power supply
An electronic load
Four channel oscilloscope with probes
Precision digital multimeter
Power and Load Connections
JUMPER SETTING FOR ISL6420AEVAL1Z
Connect JP1 pin 1 to pin 2 for 5.5V to 28V operation and
JP1 pin 2 to pin 3 for a 4.5V to 5.5V operation. JP2 and JP3,
when shorted with a jumper, pull the GPIO2 and GPIO1 pins
to GND. With the jumpers removed, GPIO2 and GPIO1 will
be floating.
CAUTION: When JP1 pin 2 to pin 3 are connected,
applying voltages >6V can damage the IC.
JUMPER SETTING FOR ISL6420AEVAL3Z
Connect power supply to the VIN terminal for a 5.5V to 28V
operation and source to both VIN and +5V terminals for a
4.5V to 5.5V operation. JP2 and JP3, when shorted with a
jumper, pull the GPIO2 and GPIO1 pins to GND. With the
jumpers removed, GPIO2 and GPIO1 will be floating.
CAUTION: Ensure that the +5V terminal is not connected
to when applying voltages >6V. This can damage the IC.
Input Voltage - The evaluation board is optimized for an
input supply of 12V, however, the input supply based on the
connection can range from 4.5V to 5.5V or 5.5V to 28V. In
the use of the 5.5V to 28V range, an additional 5V source is
not required.
If using an input supply ranging from 5.5V to 28V, the VIN
post (P1) is connected to the drain of the upper MOSFET
and the VIN pin of the IC. The chip is biased by the 5V
output (VCC5, post P5) of the internal LDO.
When using a 5V ±10% input supply, connect the power
supply to the VIN (P1) post and the VCC5 (P5) post. This will
disable the internal LDO and the chip will be powered by the
input power supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1179
For quick start evaluation, adjust the power supply to the
desired VIN. With the power supply turned off, connect the
positive lead to the VIN post (P1) and the ground lead to the
GND post (P2).
Output Voltage Loading and Monitoring - Connect the
positive lead of the electronic load and the positive lead of a
digital multimeter to the VOUT post (P3) and the ground lead
to the GND post (P4). You can use the scope probe terminal
(SC1) to monitor VOUT with an oscilloscope.
Shutdown
If the ENSS pin is pulled down and held below 1V, the
regulator will be turned off. Figure 2 shows the shutdown
profile of the regulator with the ENSS pin pulled low. Figure 3
shows the shutdown of the regulator when powering down
the input supply.
VIN
Start-up
The Power On Reset (POR) function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor connected to the ENSS (P9) pin from 0V
to 3.3V. When the ENSS pin reaches 1V, the error amplifier
reference voltage ramps from 0V to 0.6V following the slope
of the ENSS pin voltage.
There are two distinct start-up methods for the ISL6420A.
The first method is invoked through the application of power
to the IC. The soft-start feature allows for a controlled
turn-on of the output once the POR threshold of the input
voltage has been reached. Figure 1 shows the start-up
profile of the regulator in relation to the start-up of the input
supply.
ENSS
IOUT
VOUT
FIGURE 2. SHUTDOWN USING ENSS
VIN = 28V, VOUT = 3.3V, IOUT = 10A
VIN
VIN
ENSS
ENSS
IOUT
IOUT
VOUT
VOUT
FIGURE 3. POWER-DOWN OF VIN
FIGURE 1. SOFT-START
The second method of start-up is through the use of the
enable feature. Holding the ENSS (P9) pin on the ISL6420A
below 1V will disable the regulator by forcing both the upper
and lower MOSFETs off. Releasing the pin allows the
regulator to start-up.
2
AN1179.1
September 15, 2006
Application Note 1179
Output Performance
finished charging. The status of PGOOD can be monitored
at the PGOOD test point (TP1).
Switching Frequency
The evaluation board has a 0Ω resistor R9 connecting RT to
VCC5 setting the free-running switching frequency to
300kHz. The frequency can be programmed to a different
value by removing R9 and populating the R4 location with a
resistor value based on the desired frequency.
VOUT
Output Ripple
CDEL
Figure 4 shows the ripple voltage on the output of the
regulator at the free running 300kHz frequency.
PGOOD
VOUT
FIGURE 6. PGOOD
Overcurrent Protection
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. Figure 7 shows the
overcurrent hiccup mode.
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s rDS(ON) to monitor the
current. This method enhances the converter’s efficiency and
reduces cost by eliminating a current sensing resistor.
FIGURE 4. OUTPUT RIPPLE
Efficiency
ISL6420A-based regulators enable the design of highly
efficient systems. The efficiency of the evaluation board
using a 12V and a 28V input supply is shown in Figure 5.
VOUT
IOUT
ENSS
95
90
PGOOD
EFFICIENCY (%)
VIN = 12V
85
80
VIN = 28V
75
70
FIGURE 7. OVERCURRENT HICCUP MODE
65
60
1.0
3.0
5.0
IOUT (A)
7.0
9.0
FIGURE 5. EVALUATION BOARD EFFICIENCY (VOUT = 3.3V)
Power Good
PGOOD will be true (open drain) when the FB pin voltage is
within ±10% of the reference voltage and the soft-start
sequence is complete, i.e., once the soft-start capacitor is
3
A resistor, ROCSET (R8), programs the overcurrent trip level.
The PHASE node voltage is compared to the voltage on the
OCSET pin while the upper FET is on. A current (100µA
typically) is pulled from the OCSET pin to establish this
voltage across an external resistor. If PHASE is lower than
OCSET, while the upper FET is on, then an overcurrent
condition is detected for that clock cycle. The pulse is
immediately terminated, and a counter is incremented. If an
overcurrent condition is detected for 8 consecutive clock
cycles, and the circuit is not in soft-start, the ISL6420A
enters into hiccup mode. During hiccup, the external
AN1179.1
September 15, 2006
Application Note 1179
capacitor on the ENSS pin is discharged and soft-start is
initiated. During soft-start, pulse termination limiting is
enabled, but the 8-cycle hiccup counter is held in reset until
soft-start is completed.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by,
I OCSET • R OCSET
I PEAK = -------------------------------------------------R DS ( ON )
The GPIO1 (P8) and GPIO2 (P7) pins control the current
switching as per Table 2. The power supply output increases
when GPIO2 is HIGH and decreases when GPIO1 is HIGH.
Using a jumper to short the pins of JP2 and JP3 will pull
GPIO2 and GPIO1 LOW, respectively. Remove one of the
jumpers to pull GPIO1 or GPIO2 HIGH for voltage
margining. The amount that the output voltage of the power
supply changes with voltage margining will be equal to
2.468V times the ratio of the external feedback resistor (R2)
and the external resistor tied to VMSET (R6).
where IOCSET is the internal OCSET current source.
TABLE 2.
The OC trip point varies mainly due to the MOSFET’s
rDS(ON) variations. To avoid overcurrent tripping in the
normal operating load range, calculate the ROCSET resistor
from the equation above using:
GPIO1
GPIO2
VOUT
L
L
No Change
L
H
+ Delta VOUT
H
L
- Delta VOUT
H
H
Ignored
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum IOCSET from the specification table
Determine I PEAK for I PEAK > I OUT ( MAX ) + ( ∆I ) ⁄ 2
,
The evaluation board has a 330kΩ VMSET resistor (R6)
setting a current:
where ∆I is the output inductor ripple current. A small
ceramic capacitor should be placed in parallel with ROCSET
to smooth the voltage across ROCSET in the presence of
switching noise on the input voltage.
The overcurrent trip point on the evaluation board has been
set to 16A. Figure 7 shows the overcurrent hiccup mode.
IVM = 2.468V/330kΩ = 7.48µA
and
V(delta) = 7.48µA*20.5kΩ = 0.153V
Figure 9 shows the output voltage in voltage margining
mode for various VMSET resistor values.
Transient Performance
Figure 8 shows the response of the output when subjected
to transient loading from 10mA to 10A.
3.7
3.6
3.5
VOUT
VOUT (V)
3.4
3.3
3.2
V = 3.25V NOMINAL
3.1
3
2.9
2.8
150
175
200
225
250
275
300
325
350
375
400
RVMSET (kΩ)
IOUT
FIGURE 9. CHANGE IN OUTPUT VOLTAGE FOR VARIOUS
RESISTORS
FIGURE 8. TRANSIENT RESPONSE
Voltage Margining
Voltage margining mode is enabled by connecting a
margining set resistor (R6) from the VMSET pin to ground.
This resistor to ground will set a current, which is switched to
the FB pin. The current will be equal to 2.468V divided by the
value of the external resistor tied to the VMSET pin.
4
The slew time of the current is set by an external capacitor
(C13) on the CDEL pin, which is charged and discharged
with a 100µA current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is also used to set the
PGOOD rise delay. When PGOOD is low, the internal
PGOOD circuitry uses the capacitor and when PGOOD is
high the voltage margining circuit uses the capacitor. The
slew time for voltage margining can be in the range of 300µs
to 2.5ms. The CDEL capacitor on the evaluation board is
0.1µF leading to a voltage margining slew rate of 2.5ms.
AN1179.1
September 15, 2006
Application Note 1179
Figures 10 and 11 show negative and positive voltage
margining with a CDEL capacitor of 0.1µF.
VIN = 12V, VOUT = 3.3V, NO LOAD
VOUT
GPIO1
GPIO2
FIGURE 10. NEGATIVE VOLTAGE MARGINING SLEW TIME
VIN = 12V, VOUT = 3.3V, NO LOAD
Layout Guidelines
DC to DC converter layout is extremely important to obtain
the desired attenuation to the EMI frequencies. Poor layout
practice can cause conducted emissions to actually couple
around the filter components directly into the input
conductors or cause radiated emissions. The copper traces
of power input and output and high current paths must be
sized according to the RMS current passing through them.
Keep the high current loops small and the path defined. Use
single point grounding. Capacitor lead length must be
minimized as much as possible to reduce ESL. This includes
the traces on the PC board leading up to the capacitor pads.
Based on the layout, voltage transients may reduce the level
of the acceptable max VIN when operating close to 28V. In
this case, one can consider the use of snubbers or reduce
the max VIN. Use of a GND plane in a multilayered board is
preferred.
Conclusion
The ISL6420A is a versatile PWM controller. The small
footprint and the numerous features enables the
implementation of compact and highly efficient regulators,
delivering low voltage power solutions.
References
For Intersil documents available on the web, see
http://www.intersil.com/
VOUT
[1] ISL6420A Data Sheet, Intersil Corporation, File No.
FN9073.
GP101
GP102
FIGURE 11. POSITIVE VOLTAGE MARGINING SLEW TIME
5
AN1179.1
September 15, 2006
ISL6420AEVAL1Z Schematic
VIN
P1
6
VCC5
C1A
220UF
50V
OUT
JP1
R7
10K
PGOOD
ENSS
VIN
VCC5
C2
C3
1UF
1UF
10UF
C6
C5
1000PF
0.1UF
R8
VCC5
P5
P9
P7
C10
0.1UF
14
VIN
20
E
8
P8
9
11
12
JP3
1
BYPASS
VCC5
OCSET
BOOT
UGATE
PHASE
LGATE
PGND
COMP
FB
CDEL
16
E
PVCC
PGOOD
ENSS
GPIO2
GPIO1
BYPASS
VMSET
19
E
GPI01
RT
SGND
15
TP2
4
13
10
7
6
R11
5
0
C12
1UF
Q1
1
2
3
4
C11
0.1UF
3
2
0
Q2
1
2
3
4
18
17
C16
E
C17
0.027UF
R9
P6
VCC5
C14A
470UF
C13
0.1UF
E
E
R4
DNP
0.6V
E
R3
4.53K
H3
E
R2
R10
20.5K
0
R5
C18
232
3300PF
C14B
470UF
C14C
470UF
C14D
470UF
C15
0.1UF
P4
0
R6
330K
P3
4.7UH
8
7
6
5
TP3
26.7K
IN
+3.3V
VOUT
10A
L1
R1
E
SC1
C8
10UF
H1
IRF7842PBF
680PF
+5V
C9
0.1UF
8
7
6
5
IRF7842PBF
R12
ISL6420AIA
VMSET
C7
1UF
U1
JP2
GND
GND
Application Note 1179
750
H2
GPIO2
P2
D1
BAT54WT1
C4
TP1
C1B
220UF
50V
+24V
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL1Z Rev. A Bill of Materials
ID
REFERENCE
QTY
PART NUMBER
PART TYPE
DESCRIPTION
PACKAGE
VENDOR
1
U1
1
ISL6420AIAZ
IC, Linear
IC, Single PWM Controller 20 Ld QSOP Intersil
2
Q1, Q2
2
IRF7842PBF
MOSFET, Single
N-channel, 40V, 18A
SO-8
International
Rectifier
3
D1
1
BAT54WT-7-F
Diode, Schottky
30V, 200mA
SOT-323
Diode Inc.
4
L1
1
IHLP-5050CEEB4R7M01 Inductor
4.7µH, 20%, 24A
SMD
Vishay
220µF, 20%, 50V, 1150mA 12.5 X 15
CAPACITORS
5
C1A, C1B
2
EEUFC1H221S
Capacitor, Alum. Elec.
6
C2, C7
2
C3216X7R1H105K
Capacitor, Ceramic, X7R 1.0µF, 10%, 50V
SM_1206
TDK/Generic
7
C3, C12
2
C2012X7R1E105K
Capacitor, Ceramic, X7R 1.0µF, 10%, 25V
SM_0805
TDK/Generic
8
C4
1
C3225X7R1E106M
Capacitor, Ceramic, X7R 10µF, 20%, 25V
SM_1210
TDK/Generic
9
C5, C9, C10, C11,
C13, C15
6
C1608X7R1E104K
Capacitor, Ceramic, X7R 0.1µF, 10%, 25V
SM_0603
TDK/Generic
10 C6
1
C1608X7R1H102K
Capacitor, Ceramic, X7R 1000pF, 10%, 50V
SM_0603
TDK/Generic
11 C8
1
C5750X7R1H106M
Capacitor, Ceramic, X7R 10µF, 20%, 50V
SM_2220
TDK/Generic
12 C14A, C14B,
C14C, C14D
4
6TPB470M
Capacitor, POSCAP
13 C16
1
C1608COG1H681JT
Capacitor, Ceramic, X7R 680pF, 10%, 25V
SM_0603
TDK/Generic
14 C17
1
C1608X7R1E273K
Capacitor, Ceramic, X7R 0.027µF, 10%, 25V
SM_0603
TDK/Generic
15 C18
1
C1608X7R1E332K
Capacitor, Ceramic, X7R 3300pF, 10%, 25V
SM_0603
TDK/Generic
470µF, 20%, 6.3V, 0.035Ω Case D4
Panasonic
SANYO
RESISTORS
16 R1
1
Resistor, Film
26.7kΩ, 1%, 1/16W
SM_0603
Panasonic/Generic
17 R2
1
Resistor, Film
20.5kΩ, 1%, 1/16W
SM_0603
Panasonic/Generic
18 R3
1
Resistor, Film
4.53kΩ, 1%, 1/16W
SM_0603
Panasonic/Generic
19 R4
1
SM_0603
Panasonic/Generic
20 R5
1
Resistor, Film
232Ω, 1%, 1/16W
SM_0603
Panasonic/Generic
21 R6
1
Resistor, Film
330kΩ, 1%, 1/16W
SM_0603
Panasonic/Generic
22 R7
1
Resistor, Film
10kΩ,1%,1/16W
SM_0603
Panasonic/Generic
23 R8
1
Resistor, Film
750Ω, 1%, 1/16W
SM_0603
Panasonic/Generic
24 R9, R10, R11, R12
4
Resistor, Film
0Ω, 1%, 1/16W
SM_0603
Panasonic/Generic
Do Not Populate
Resistor, Film
OTHERS
25 SC1
1
Do Not Populate
Terminal, Scope Probe
Terminal, Scope Probe
26 P1 - P9
9
1514-2
Turrett Post
Terminal post, through
hole, 1/4 inch
PTH
Johnson
27 TP1, TP2, TP3
3
5002
TEST POINT vertical,
white
PC test jack
PTH
Keystone
28 JP1
1
68000-236-1X3
Header
1X3 Break Strip GOLD
29 JP2, JP3
2
68000-236-1X2
Header
1X2 Break Strip GOLD
30 JP1, JP2, JP3
3
S9001-ND
Jumper
2 pin jumper
31
Tektronix
Digikey
Bumpers
7
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL1Z Printed Circuit Board Layers
ISL6420AEVAL1Z - TOP LAYER (SILKSCREEN)
ISL6420AEVAL1Z - TOP LAYER (COMPONENT SIDE)
8
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL1Z Printed Circuit Board Layers (Continued)
ISL6420AEVAL1Z - LAYER 2
ISL6420AEVAL1Z - LAYER 3
9
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL1Z Printed Circuit Board Layers (Continued)
ISL6420AEVAL1Z - BOTTOM LAYER (SOLDER SIDE)
ISL6420AEVAL1Z - BOTTOM LAYER (SILKSCREEN)
10
AN1179.1
September 15, 2006
ISL6420AEVAL3Z Schematic
VCC5
+5V
F1
VIN
R10
P1
P5
419_SMQ
250MA
C1A
220UF
11
VCC5
+24V
10
C1B
220UF
OUT
P2
R7
10K
PGOOD
D2
1SMA5.0AT3
TP1
C2
1UF
5.0
C3
1UF
C4
C6
10UF
1000PF
C5
ENSS
E
C7
1UF
C10
0.1UF
12 13
2
P8
4
5
JP2
14
C13
0.1UF
E
21
GPIO2
GPIO1
BYPASS
VMSET
CDEL ISL6420AIR
EP
3
20
19
9
R9
1
2
3
4
8 10 11 15
H2
0
Q2
+3.3V
P3
4.7UH
8
7
6
5
TP4
R11
680PF
R1
C17
26.7K
0.027UF
E
R2
E
0.6V
20.5K
R3
4.53K
E
R5
C18
232
3300PF
C14B
470UF
C14C
470UF
C14C
470UF
C15
0.1UF
P4
TP3
VOUT
10A
C14A
470UF
0
R6
330K
C9
0.1UF
L1
C16
R4
DNP
P6
SP1
H3
IRF7842PBF
E
IN
E
8
7
6
5
IRF7842PBF
EGND
VCC5
Q1
18
16
E
C12
1UF
VMSET
1
2
3
4
C11
0.1UF
OCSET
BOOT
UGATE
PHASE
LGATE
U1
TP2
C8
10UF
6
RT
SGND
FB
COMP
PGND
1
E
7 17
ENSS
PGOOD
VIN
PVCC
VCC5
E
BYPASS
H1
P7
JP1
GPI01
750
GND
Application Note 1179
GPIO2
R8
D1
BAT54WT1
0.1UF
P9
GND
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL3Z Rev. B Bill of Materials
ID
REFERENCE
QTY
PART NUMBER
PART TYPE
DESCRIPTION
PACKAGE
VENDOR
1
U1
1
ISL6420AIRZ
IC, Linear
IC, Single PWM Controller 20 Ld QFN Intersil
2
Q1, Q2
2
IRF7842PBF
MOSFET, Single
N-channel, 40V, 18A
SO-8
International
Rectifier
3
D1
1
BAT54WT-7-F-T
Diode, Schottky
30V, 200mA
SOT-323
Diode Inc.
4
D2
1
1SMA5.0AT3G
Diode, Voltage
Suppressor
6.4V, 400mA
SMA
On Semi
5
L1
1
IHLP-5050CEEB4R7M01 Inductor
4.7µH, 20%, 24A
SMD
Vishay
220µF, 20%, 50V, 1150mA Radial
CAPACITORS
6
C1A, C1B
2
EEUFC1H221S
Capacitor, Alum. Elec.
7
C2, C7
2
C3216X7R1H105K
Capacitor, Ceramic, X7R 1.0µF, 10%, 50V
SM_1206
TDK/Generic
8
C3, C12
2
C2012X7R1E105K
Capacitor, Ceramic, X7R 1.0µF, 10%, 25V
SM_0805
TDK/Generic
9
C4
1
C3225X7R1E106M
Capacitor, Ceramic, X7R 10µF, 20%, 25V
SM_1210
TDK/Generic
10 C5, C9, C10, C11,
C13, C15
6
C1608X7R1E104K
Capacitor, Ceramic, X7R 0.1µF, 10%, 25V
SM_0603
TDK/Generic
11 C6
1
C1608X7R1H102K
Capacitor, Ceramic, X7R 1000pF, 10%, 50V
SM_0603
TDK/Generic
12 C8
1
C5750X7R1H106M
Capacitor, Ceramic, X7R 10µF, 20%, 50V
SM_2220
TDK/Generic
13 C14A, C14B, C14C,
C14D
4
6TPB470M
Capacitor, POSCAP
14 C16
1
C1608X7R1E681K
Capacitor, Ceramic, X7R 680pF, 10%, 25V
SM_0603
TDK/Generic
15 C17
1
C1608X7R1E273K
Capacitor, Ceramic, X7R 0.027µF, 10%, 25V
SM_0603
TDK/Generic
16 C18
1
C1608X7R1E332K
Capacitor, Ceramic, X7R 3300pF, 10%, 25V
SM_0603
TDK/Generic
470µF, 20%, 6.3V, 0.035Ω Case D4
Panasonic
SANYO
RESISTORS
17 R1
1
Resistor, Film
26.7kΩ, 1%, 1/16W
SM_0603
TDK/Generic
18 R2
1
Resistor, Film
20.5kΩ, 1%, 1/16W
SM_0603
TDK/Generic
19 R3
1
Resistor, Film
4.53kΩ, 1%, 1/16W
SM_0603
TDK/Generic
20 R4 (DNP)
1
SM_0603
TDK/Generic
21 R5
1
Resistor, Film
232Ω, 1%, 1/16W
SM_0603
TDK/Generic
22 R6
1
Resistor, Film
330kΩ, 1%, 1/16W
SM_0603
TDK/Generic
23 R7
1
Resistor, Film
10kΩ, 1%,1/16W
SM_0603
TDK/Generic
24 R8
1
Resistor, Film
750Ω, 1%, 1/16W
SM_0603
TDK/Generic
25 R9, R11
2
Resistor, Film
0Ω, 1%, 1/16W
SM_0603
TDK/Generic
26 R10
1
Resistor, Film
10Ω, 5%, 1/4W
SM_1210
TDK/Generic
SMT
Wickmann
Do Not Populate
Resistor, Film
OTHERS
27 F1
1
419-0250-000
Fuse
Fuse, 250mA
28 SP1
1
Do Not Populate
Terminal, Scope Probe
Terminal, Scope Probe
29 P1 - P9
9
1514-2
Turrett Post
Terminal post, through
hole, 1/4 inch
PTH
Johnson
30 TP1, TP2, TP3, TP4
4
5002
TEST POINT vertical,
white
PC test jack
PTH
Keystone
31 JP1, JP2
2
69190-202
Header
1X2 Break Strip GOLD
BERG/FCI
32 JP1, JP2
2
SPC02SYAN
Jumper
2 pin jumper
SULLINSSULLINS
33
Tektronix
Bumpers
12
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL3Z Printed Circuit Board Layers
ISL6420AEVAL3Z - TOP LAYER (SILKSCREEN)
ISL6420AEVAL3Z - TOP LAYER (COMPONENT SIDE)
13
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL3Z Printed Circuit Board Layers (Continued)
ISL6420AEVAL3Z - LAYER 2
ISL6420AEVAL3Z - LAYER 3
14
AN1179.1
September 15, 2006
Application Note 1179
ISL6420AEVAL3Z Printed Circuit Board Layers (Continued)
ISL6420AEVAL3Z - BOTTOM LAYER (SOLDER SIDE)
ISL6420AEVAL3Z - BOTTOM LAYER (SILKSCREEN)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
AN1179.1
September 15, 2006