APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9420
Single Digitally Controlled (XDCP) Potentiometer
FEATURES
DESCRIPTION
• Solid-State Potentiometer
• SPI serial interface
• Register oriented format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
• High reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of nonvolatile EEPROM memory
• 10KΩ or 2.5KΩ resistor arrays
• Resolution: 64 taps each pot
• 14-lead TSSOP, 16-lead SOIC, and 16-pin plastic
DIP packages
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of
the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
HOLD
CS
SCK
S0
SI
A0
Interface
and
Control
Circuitry
R0 R1
8
Data
R2 R3
Wiper
Counter
Register
(WCR)
VH/RH
VL/RL
VW/RW
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Characteristics subject to change without notice.
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X9420
PIN DESCRIPTIONS
Potentiometer Pins
Host Interface Pins
VH/RH, VL/RL
The VH/RH and VL/RL input are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched by
the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.
Chip Select (CS)
When CS is HIGH, the X9420 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
VW/RW
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
System/Digital Supply (VCC)
VCC is the supply voltage for the system/digital section.
VSS is the system ground.
PIN CONFIGURATION
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
DIP/SOIC
VCC
1
16
V+
CS
2
15
NC
RL/VL
3
14
A0
RH/VH
4
13
SO
RW/VW
5
12
HOLD
SI
6
11
SCK
WP
7
10
NC
VSS
8
9
X9420
V-
TSSOP
Device Address (A0)
The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.
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CS
1
14
VCC
RL/VL
2
13
V+
RH/VH
3
12
A0
RW/VW
4
X9420 11
SO
SI
5
10
WP
6
9
SCK
VSS
7
8
V-
HOLD
Characteristics subject to change without notice.
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X9420
PIN NAMES
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0
Device Address
VH/RH,
VL/RL
Potentiometer Pins (terminal equivalent)
VW/RW
Potentiometer Pins (wiper equivalent)
WP
Hardware Write Protection
HOLD
Serial Communication Pause
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
PRINCIPLES OF OPERATION
The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches. The
block diagram of the potentiometer is shown in Figure 1.
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Wiper Counter Register (WCR)
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
0
D5
D4
D3
D2
D1
(MSB)
D0
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvolatile data storage or for storage of up to four different
wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
0
0
WP5 WP4 WP3 WP2 WP1 WP0
(MSB)
(LSB)
– {WP5~WP0}: These bits specify the wiper position of
the potentiometer.
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X9420
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
VH
Serial
Bus
Input
From Interface
Circuitry
Register 0
8
REGISTER 2
C
O
U
N
T
E
R
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
REGISTER 3
D
E
C
O
D
E
INC/DEC
Logic
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
UP/DN
Modified SCK
UP/DN
VL
CLK
VW
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
Figure 2. Address/Identification Byte Format
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9420 from the host, following
a CS going HIGH to LOW, is called the Address or
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9420 this is fixed as 0101[B] (refer to Figure 2).
Instruction Byte
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address is
defined by the state of the A0 input pin. The X9420
compares the serial data stream with the address input
state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A0 input can be actively
driven by a CMOS input signal or tied to VCC or VSS.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
0
Instructions
The remaining three bits in the ID byte must be set to
110.
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X9420
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9420; either between the host and one
of the Data Registers or directly between the host and
the WCR. These instructions are:
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current wiper
position of the pot,
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
– Read Data Register—read the contents of the
selected data register;
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its associated
registers.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
VL/RL terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
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1
0
1
1
1
0
A0
I3
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I2
I1
I0
R1 R0
0
0
Characteristics subject to change without notice.
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X9420
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0 0
0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3
I2
I1
I0
0
0
0
0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW
INC/DEC CMD Issued
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X9420
Table 3. Instruction Set
I3
I2
Instruction Set
I1 I0 R1 R0
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
1
0
0
1
0
0
0
0
Read the contents of the Wiper Counter Register
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter Register
1
0
1
1
R1
R0
0
0
Write Data Register
1
1
0
0
R1
R0
0
0
XFR Data Register to
Wiper Counter
Register
XFR Wiper Counter
Register to Data
Register
Increment/Decrement
Wiper Counter
Register
Read Status (WIP bit)
1
1
0
1
R1
R0
0
0
Read the contents of the Data Register pointed to
by R1–R0
Write new value to the Data Register pointed to by
R1–R0
Transfer the contents of the Data Register pointed
to by R1–R0 to the Wiper Counter Register
1
1
1
0
R1
R0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R1–R0
0
0
1
0
0
0
0
0
Enable Increment/decrement of the Wiper Counter
Register
0
1
0
1
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
Instruction
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Operation
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X9420
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
device
instruction
wiper position
identifier
addresses
opcode
(sent by X9420 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 0 1 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 0 1 0 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by R1-R0.
device type
device
instruction
register
Data Byte
identifier
addresses
opcode
addresses
(sent by X9420 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 1 1 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
Write Data Register (DR)
Write a new value to the Register pointed to by R1-R0.
device type
device
identifier
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 0 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1-R0 to the WCR.
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 1 R R 0 0 Edge
0
1 0
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X9420
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 1 0 R R 0 0 Edge
0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
increment/decrement
CS
CS
identifier
addresses
opcode
(sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 1 1 0 A 0 0 1 0 0 0 0 0 I/D I/D . . . . I/D I/D Edge
0
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9420 on SO)
CS
CS
Falling
W Rising
Edge 0 1 0 1 1 1 0 A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
0
P
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X9420
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCK, SCL or any
address input with respect to VSS........... –1V to +7V
Voltage on V+ (referenced to VSS) .........................10V
Voltage on V- (referenced to VSS) ........................ -10V
(V+) – (V-) ..............................................................12V
Any VH/RH, VL/RL, VW/RW ..............................V- to V+
Lead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds) ..................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Device
Supply Voltage (VCC) Limits
Commercial
0°C
+70°C
X9420
5V ±10%
Industrial
–40°C
+85°C
X9420-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
RTOTAL
IW
RW
Vv+
Parameter
Min.
End to End Resistance
Power Rating
Wiper Current
Wiper Resistance
Voltage on V+ Pin
X9420
X9420-2.7
VvVoltage on V- Pin
X9420
X9420-2.7
Voltage on any VH/RH, VL/RL, VW/RW
VTERM
Noise
Resolution(4)
Absolute Linearity(1)
Relative Linearity(2)
Temperature Coefficient of RTOTAL
Ratiometric Temperature Coefficient
CH/CL/CW Potentiometer Capacitances
Rh, RI, Rw leakage current
IAL
Limits
Typ.
Max.
Units
150
±20
50
±3
250
%
mW
mA
Ω
40
100
Ω
+5.5
+5.5
-4.5
-2.7
V+
V
+4.5
+2.7
-5.5
-5.5
V-140
1.6
±1
±0.2
±300
±20
10/10/25
0.1
10
Test Conditions
25°C, each pot
Wiper Current = ± 1mA,
V+/V– = ±3V
Wiper Current = ± 1mA,
V+/V– = ±5V
V
V
dBV
%
MI(3)
MI(3)
ppm/°C
ppm/°C
pF
µA
Ref: 1kHz
See Note 5
Vw(n)(actual) – Vw(n)(expected)
Vw(n + 1) – [Vw(n) + MI]
See Note 5
See Note 5
See Circuit #3
Vin = V- to V+. Device is in
stand-by mode.
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH–VL)/63, single pot
(4) Typical = Individual array resolution.
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Characteristics subject to change without notice.
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X9420
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
ICC1
VCC Supply Current (Active)
ICC2
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
VCC Supply Current
(Non-volatile Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC Current (Standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW Voltage
–0.5
VCC x 0.1
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data Changes per Bit per Register
Data Retention
100
Years
CAPACITANCE
Symbol
Test
Max.
Units
Test Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (A0, SI, and SCK)
6
pF
VIN = 0V
(5)
COUT
(5)
CIN
POWER-UP TIMING
Symbol
Parameter
Max.
Max.
Units
(6)
tPUR
Power-up to Initiation of Read Operation
1
1
ms
tPUW(6)
Power-up to Initiation of Write Operation
5
5
ms
tRVCC
VCC Power up Ramp
0.2
50
V/msec
POWER UP REQUIREMENTS (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V–, and then the potentiometer pins, RH,
RL, and RW. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in
order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until VCC, V+ and V– reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
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X9420
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
5V
1533Ω
SDA Output
100pF
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.0
MHz
fSCK
SSI/SPI Clock Frequency
tCYC
SSI/SPI Clock Cycle Time
500
ns
tWH
SSI/SPI Clock High Time
200
ns
tWL
SSI/SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
2
µs
tFI
SI, SCK, HOLD and CS Input Fall Time
2
µs
500
ns
100
ns
tDIS
SO Output Disable Time
0
tV
SO Output Valid Time
tHO
SO Output Hold Time
tRO
SO Output Rise Time
50
ns
tFO
SO Output Fall Time
50
ns
0
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
ns
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
20
ns
CS Deselect Time
2
µs
tWPASU
WP, A0 and A1 Setup Time
0
ns
tWPAH
WP, A0 and A1 Hold Time
0
ns
tCS
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
12 of 20
X9420
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
tWR
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
10
µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
10
µs
tWRID
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
450
ns
SYMBOL TABLE
WAVEFORM
REV 1.1.6 7/30/02
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
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Characteristics subject to change without notice.
13 of 20
X9420
TIMING DIAGRAMS
Input Timing
tCS
CS
tLAG
tCYC
tLEAD
SCK
...
tSU
tH
tWL
...
MSB
SI
tRI
tFI
tWH
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
14 of 20
X9420
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
...
MSB
SI
LSB
VW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VW
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
15 of 20
X9420
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solidstate potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile
memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW
VL
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Basic Circuits
Buffered Reference Voltage
Noninverting Amplifier
Cascading Techniques
R1
+V
+5V
+V
+V
VS
+5V
VW
VW
X
+
VO
–
OP-07
–5V
VOUT = VW
–
LM308A
+
VW
R2
+V
–5V
R1
VW
(a)
Offset Voltage Adjustment
Voltage Regulator
VIN
VO (REG)
317
R1
R2
VS
–
+
VO
100KΩ
–
VO
+
}
TL072
R2
}
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Comparator with Hysterisis
VS
R1
R1
R2
10KΩ
10KΩ
+12V
REV 1.1.6 7/30/02
VO = (1+R2/R1)VS
(b)
10KΩ
VUL = {R1/CR1+R2} VO(max)
VLL = {R1/CR1+R2} VO(min)
-12V
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Characteristics subject to change without notice.
16 of 20
X9420
PACKAGING INFORMATION
16-Lead Hermetic Dual In-Line Package Type D
0.735 (18.67)
0.775 (19.69)
0.310 (7.87)
0.220 (5.59)
Pin 1
0.005 (0.13) Min.
0.700 (17.78)
Ref.
0.098 (2.49)
––
Seating
Plane
0.200 (5.08)
––
0.070 (1.78)
0.015 (0.38)
0.150 (3.81) Min. 0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
0.065 (1.65)
0.038 (0.97)
Typ. 0.060 (1.52)
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.320 (8.13)
0.290 (7.37)
Typ. 0.311 (7.90)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
17 of 20
X9420
PACKAGING INFORMATION
16-Lead Plastic SOIC (300 Mil Body) Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" Typical
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.050"
Typical
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
18 of 20
X9420
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
19 of 20
X9420
Ordering Information
X9420
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 16-Lead Plastic DIP
S = 16-Lead SOIC
V = 14-Lead TSSOP
Potentiometer Organization
W = 10K
Y = 2.5K
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
REV 1.1.6 7/30/02
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Characteristics subject to change without notice.
20 of 20