5 4 3 2 1 [4] LP_D0_P_RX [2] R1 50 [4] DPHY_D0_P_RX D HS_D0_P_RX [2] D [4] DPHY_D0_N_RX HS_D0_N_RX R2 50 [4] LP_D0_N_RX [4] LP_D1_P_RX [4] LP_CLK0_P_RX [2] R4 50 [2] [4] DPHY_D1_N_RX HS_D1_N_RX [4] DPHY_CLK0_N_RX R5 50 HS_CLK0_N_RX R6 50 C HS_D1_P_RX [2] HS_CLK0_P_RX [2] [4] DPHY_D1_P_RX [4] DPHY_CLK0_P_RX R3 50 [4] [4] LP_CLK0_N_RX LP_D2_P_RX [4] LP_CLK1_P_RX [2] R8 50 [2] [4] HS_D2_P_RX [2] HS_CLK1_P_RX [2] [4] DPHY_D2_N_RX HS_D2_N_RX [4] DPHY_CLK1_N_RX R7 50 DPHY_D2_P_RX [4] DPHY_CLK1_P_RX C LP_D1_N_RX [4] R9 50 HS_CLK1_N_RX R10 50 [4] LP_D2_N_RX [4] [4] LP_CLK1_N_RX LP_D3_P_RX [2] R11 50 [4] DPHY_D3_P_RX B B HS_D3_P_RX [2] [4] DPHY_D3_N_RX HS_D3_N_RX R12 50 [4] LP_D3_N_RX Place resistor networks as close to Bank 0 pins as possible and trace match all diff signals between P and N as well as between pairs A LP_* Signals are only needed if you intend on monitoring LP signals from within the FPGA. If monitoring LP signals from within the FPGA is not needed 100 ohm parallel termination can be used in place of the resistor network for those pairs. It is recommended to use the 50 ohm resistor network on at least the clock lanes and data lane 0 for DSI. For CSI-2 100ohm termination is sufficient for all data and clock lanes in most cases. Title XO2 DPHY RX Resistor Networks MIPI XO2 Schematic Example Size B Date: 5 4 3 A 2 Document Number <Doc> Friday, September 20, 2013 Rev 1 Sheet 1 1 of 5 5 4 3 2 1 [5] LP_D0_P_TX R13 50 [5] HS_D0_P_TX D HS_D0_N_TX R14 320 R15 320 DPHY_D0_P_TX [7] DPHY_D0_N_TX [7] DPHY_D1_P_TX [7] DPHY_D1_N_TX [7] [5] D R16 50 [5] LP_D0_N_TX [5] [5] LP_CLK0_P_TX LP_D1_P_TX R17 50 [5] HS_CLK0_P_TX R19 320 R21 320 DPHY_CLK0_P_TX [7] DPHY_CLK0_N_TX [7] [5] HS_CLK0_N_TX HS_D1_N_TX R23 50 R22 320 R24 50 C LP_D1_N_TX [5] [5] LP_CLK1_P_TX LP_D2_P_TX R25 50 [5] R27 320 R29 320 R26 50 [5] DPHY_CLK1_P_TX [7] DPHY_CLK1_N_TX [7] HS_D2_P_TX [5] HS_CLK1_N_TX 320 [5] LP_CLK0_N_TX HS_CLK1_P_TX R20 [5] [5] C R18 50 [5] HS_D1_P_TX R28 320 R30 320 DPHY_D2_P_TX [7] DPHY_D2_N_TX [7] [5] HS_D2_N_TX R31 50 [5] LP_CLK1_N_TX R32 50 [5] LP_D2_N_TX [5] LP_D3_P_TX R33 50 B [5] HS_D3_P_TX R34 320 R35 320 B DPHY_D3_P_TX [7] DPHY_D3_N_TX [7] [5] HS_D3_N_TX [5] R36 50 LP_D3_N_TX Place resistor networks as close to Bank 0 pins as possible and trace match all diff signals between P and N as well as between pairs If LP mode is not needed the LP_* signals can be removed with the 50ohm resistors connected to ground A A Title XO2 DSI TX Resistor Networks MIPI XO2 Schematic Example Size B Date: 5 4 3 2 Document Number <Doc> Friday, September 20, 2013 Rev 1 Sheet 1 2 of 5 5 4 3 2 1 V2P5 V2P5 100NF 10V 10V 10V 10V CSSPIN_PB4A_T PB4B_C N3 P4 PB7A_T PB7B_C MCLK_CCLK_PB9A_T SO_SPISO_PB9B_C MACHX02-4000 [3] HS_CLK1_P_RX [3] HS_CLK1_N_RX M7 N8 [3] HS_D1_P_RX [3] HS_D1_N_RX P8 M8 [6] HS_D1_P_TX [6] HS_D1_N_TX A2 B3 [6] HS_CLK1_P_TX [6] HS_CLK1_N_TX A3 C4 [6] HS_D0_P_TX [6] HS_D0_N_TX B5 C6 [6] HS_CLK0_P_TX [6] HS_CLK0_N_TX A7 B7 C9 A9 PB10A_T PB10B_C N6 P6 A10 C11 [6] HS_D2_P_TX [6] HS_D2_N_TX PB13A_PCLKT2_0_T PB13B_PCLKC2_0_C P7 N7 A11 B12 PB15A_T PB15B_C M9 N10 M10 P11 C12 A12 [6] HS_D3_P_TX [6] HS_D3_N_TX PB20A_PCLKT2_1_T PB20B_PCLKC2_1_C P9 N9 [3] HS_D0_P_RX [3] HS_D0_N_RX V2P5 A8 B10 C5 GND PB3A_T PB3B_C N5 M5 [3] HS_CLK0_P_RX [3] HS_CLK0_N_RX 100NF 1UF P2 N2 M4 N4 C D BANK 2 VCCIO2_1 VCCIO2_2 VCCIO2_3 P3 M3 [3] HS_D3_P_RX [3] HS_D3_N_RX C8 U1A MACHX02-4000 M6 N11 P1 [3] HS_D2_P_RX [3] HS_D2_N_RX C7 U1C V2P5 GND B C6 100NF C5 100NF 100NF C4 10V 10V D 10V 100NF C3 10V C2 1UF C1 PB21A_T PB21B_C B9 C10 PB23A_T PB23B_C B13 A13 PB24A_T PB24B_C C8 B8 BANK 0 VCCIO0_1 VCCIO0_2 VCCIO0_3 PT9A_T_LVDS PT9B_C_LVDS PT11A_T_LVDS PT11B_C_LVDS PT14A_T_LVDS PT14B_C_LVDS PT18A_PCLKT0_1_T_LVDS PT18B_PCLKC0_1_C_LVDS C PT21A_T_LVDS PT21B_C_LVDS PT24A_T_LVDS PT24B_C_LVDS PT25A_T_LVDS PT25B_C_LVDS PT27A_T_LVDS PT27B_C_LVDS JTAGENB_PT23C_T PROGRAMN_PT23D_C INITN_PT28C_T DONE_PT28D_C SCL_PCLKT0_0_PT20C_T SDA_PCLKC0_0_PT20D_C PB27A_T PB27B_C M11 P12 MachXO2-4000 HE 132csbga PB29A_T PB29B_C N12 P13 SN_PB30A_T SI_SISPI_PB30B_C B HS_* signals must be trace length matched MachXO2-4000 HE 132csbga between P and N of a pair as well as between the individual pairs HS_* signals must be trace length matched between P and N of a pair as well as between the individual pairs XO2 MIPI HS TX Signals A A XO2 MIPI HS RX Signals Title MIPI XO2 Schematic Example Size B Date: 5 4 3 2 Document Number <Doc> Friday, September 20, 2013 Rev 1 Sheet 1 3 of 5 5 4 3 1 V1P2 U1D V1P8 2 D D MACHX02-4000 L3 GND M1 M2 V1P8 PL20A_T PL20B_C 100NF MACHX02-4000 V1P8 BANK 4 G1 F1 F3 10V 10V 10V 10V C G3 H2 GND H1 H3 V1P8 J1 J2 C24 100NF 100NF C23 100NF C22 1UF C21 VCCIO4 PL9A_T PL9B_C PL10C_PCLKT4_0_T PL10D_PCLKC4_0_C PL13A_T PL13B_C PL14A_T PL14B_C MachXO2-4000 HE 132csbga 10V 10V 10V 10V U1F MACHX02-4000 V1P8 BANK 5 D3 GND B1 B2 B C1 C3 C2 D1 E1 E2 E3 F2 100NF 100NF B14 C13 GND PL19B_C VCCIO5 PL3A_L_GPLLT_FB_T PL3B_L_GPLLC_FB_C MACHX02-4000 D14 H14 L12 10V PL17A_PCLKT3_0_T PL17B_PCLKC3_0_C U1E C20 100NF C19 100NF 1UF C18 U1B V1P2 PL16A_T PL16B_C MachXO2-4000 HE 132csbga C17 C16 10V 10V K1 K3 C15 10V J3 K2 VCCIO3 10V 100NF L1 C14 1UF BANK 3 C12 10V 10V 10V 100NF C11 100NF C10 1UF C9 C13 100NF V1P8 [6] LP_CLK1_P_TX [6] LP_CLK1_N_TX C14 D12 [6] LP_CLK0_P_TX [6] LP_CLK0_N_TX E12 E14 [6] LP_D0_P_TX [6] LP_D0_N_TX E13 F12 [6] LP_D1_P_TX [6] LP_D1_N_TX F13 F14 [6] LP_D2_P_TX [6] LP_D2_N_TX G12 G14 [6] LP_D3_P_TX [6] LP_D3_N_TX G13 H12 [3] LP_CLK1_P_RX [3] LP_CLK1_N_RX J12 J14 [3] LP_CLK0_P_RX [3] LP_CLK0_N_RX J13 K12 [3] LP_D0_P_RX [3] LP_D0_N_RX K13 K14 [3] LP_D1_P_RX [3] LP_D1_N_RX L14 M13 [3] LP_D2_P_RX [3] LP_D2_N_RX M12 M14 [3] LP_D3_P_RX [3] LP_D3_N_RX N13 N14 BANK 1 VCCIO1_1 VCCIO1_2 VCCIO1_3 PR2A_R_GPLLT_FB_DQ0_T PR2B_R_GPLLC_FB_DQ0_C PR3A_R_GPLLT_IN_DQ0_T PR3B_R_GPLLC_IN_DQ0_C PR5A_DQ0_T PR5B_DQ0_C PR6A_DQ0_T PR6B_DQ0_C C PR8A_DQ0_T PR8B_DQ0_C PR9A_DQS0_T PR9B_DQS0N_C PR10A_PCLKT1_0_DQ0_T PR10B_PCLKC1_0_DQ0_C PR13A_DQS1_T PR13B_DQS1N_C PR14A_DQ1_T PR14B_DQ1_C PR15A_DQ1_T PR15B_DQ1_C PR16A_DQ1_T PR16B_DQ1_C PR18A_DQ1_T PR18B_DQ1_C B PR19A_DQ1_T PR19B_DQ1_C PL4A_L_GPLLT_IN_T PL4B_L_GPLLC_IN_C MachXO2-4000 HE 132csbga PL6A_PCLKT5_0_T PL6B_PCLKC5_0_C PL7A_T PL7B_C PL8A_T PL8B_C MachXO2-4000 HE 132csbga For XO2-1200 compatibility, VCCIO3 = VCCIO4 = VCCIO5 XO2 MIPI LP RX and TX Signals A A Extra Banks Title MIPI XO2 Schematic Example Size B Date: 5 4 3 2 Document Number <Doc> Friday, September 20, 2013 Rev 1 Sheet 1 4 of 5 4 3 2 V2P5 TP1 V2P5 LED1 LED2 PART_NUMBER = HSMG-C190 PART_NUMBER = HSMH-C190 LED Manufacturer = AVAGO LED Manufacturer = AVAGO TP_LOOP_RED 1R V1P8 2 V1P2 1 R37 1 2 5 5 R40 180 R0603 1% R41 180 R0603 1% GND GND GND R43 10_0K R0402 1ms RC 0.01uF GND V1P2 GND U1G Vout = 0.4*(1+R44/R46) = 1.200V MACHX02-4000 V1P2 Power C GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 A1 A14 N1 P14 VCC1 VCC2 VCC3 VCC4 C29 C30 C31 C32 C 10V A5 B11 D2 D13 G2 H13 L2 L13 P5 P10 100NF GND DNI 10V C28 R39 10uF/6V3/X7R GND 2 7 ADJ C27 100NF EN 100K R38 20K R0402 10V 6 R42 V1P8 1 4 GND GND PWP GND OUT 100NF IN 10uF/6V3/X7R V1P2 10V 3 100nF LTC3025 1UF U2 LTC3025 BIAS C26 1 D C25 1 D GND C7 NC GND MachXO2-4000 HE 132csbga Core Voltage U1H V1P8 B B MACHX02-4000 R44 4.7k R45 4.7k R46 4.7k JTAG B6 J1 V1P8 1 VCC TDO TDI ispEN_N NC C33 100nF TMS TCK 7 DONE GND INITN 2 3 4 5 6 8 9 10 B4 A4 A6 TCK_TEST_CLK_PT15C_T TDI_PT13D_C TDO_PT13C_T TMS_PT15D_C DNI GND MachXO2-4000 HE 132csbga JTAG Header R47 1k GND A A JTAG Title MIPI XO2 Schematic Example Size B Date: 5 4 3 2 Document Number <Doc> Friday, September 20, 2013 Rev 1 Sheet 1 5 of 5