CSI2 to Parallel Bridge Board User’s Guide February 2013 Revision: EB81_01.1 CSI2 to Parallel Bridge Board User’s Guide Introduction The CSI2 to Parallel Bridge Board comprises a compact, low cost, MIPI CSI2 (Camera Serial Interface) image sensor, lens and lens housing with adjustable focus, that can bolt directly onto the Lattice HDR-60 Base Board or the MachXO2™ Dual Sensor Interface Board. Both the CSI2 to Parallel Bridge Board and the MachXO2 Dual Sensor Interface Board are designed to work together. These boards plug into the HDR-60 Base Board to allow for a demonstration. The CSI2 to Parallel Bridge Board is designed to use the Sony IMX169 CMOS Digital Image Sensors which feature: • Up to 13 megapixels • HD video (1080p30 mode configurable) • Selectable video or single frame modes • MIPI CSI2 output, either two or four data lanes Read more about the image sensor specifications in the Sony IMX169 data sheet. Features Key features of the CSI2 to Parallel Bridge Board include: • Sony IMX169 CMOS Digital Image Sensor • Lens: F/1.59, <7% distortion, with minimized flare, halo, and ghosting • Lens holder with adjustable focus • CSI2 or parallel signal connections to the MachXO2 Dual Sensor Interface Board or HDR-60 Base Board • Selectable on-board 27.000 MHz MEMs oscillator, or HDR-60 Base Board oscillator • Power status LEDs with one user-defined LED General Description The CSI2 to Parallel Bridge Board has been designed for use on the MachXO2 Dual Interface Sensor Board and the HDR-60 Base Board. The CSI2 to Parallel Bridge Board contains the camera sensor portion, while the MachXO2 Dual Sensor Interface Board performs the CSI2 to parallel conversion. The HDR-60 Base Board allows the user to see an image on a HDMI monitor. See RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge, for more information concerning a related demo. Initial Setup and Handling The following is recommended reading prior to removing the CSI2 to Parallel Bridge Board from the static shielding bag and may or may not apply to your particular use of the board. CAUTION: The devices on the boards can be damaged by improper handling. The devices on the evaluation boards contain fairly robust ESD (Electro Static Discharge) protection structures within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example of ESD characterization requirements). Even so, the devices are static-sensitive to conditions that exceed their designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance or larger capacitance than the respective ESD specifications require can potentially damage or degrade the devices on the evaluation board. As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation boards when they are removed from the static shielding bag. If you will not be using the boards for a while, it is best to put them back in the static shielding bag. Please save the static shielding bag and packing box for future storage of the boards when they are not in use. 2 CSI2 to Parallel Bridge Board User’s Guide When reaching for the boards, it is recommended that you first touch the outside shield portion of the J11 BNC connector on the HDR-60 Base Board. If the CSI2 to Parallel Bridge Board is not installed on the HDR-60 Base Board, then when reaching for the CSI2 to Parallel Bridge Board, it is recommended that you first touch the outside edge of the mounting holes on the CSI2 to Parallel Bridge Board. This will neutralize any static voltage difference between your body and the board prior to any contact with signal I/O. CAUTION: To minimize the possibility of ESD damage, the first and last electrical connection to the board, should be from test equipment chassis ground to the J11 BNC shield GND on the HDR-60 Base Board. Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment to the J11 BNC shield GND on the HDR-60 Base Board. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged should be the chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board. If you are holding or carrying the board while it is not in a static shielding bag, please keep one finger on the J11 BNC shield GND on the HDR-60 Base Board. If carrying the CSI2 to Parallel Bridge Board alone, keep one finger one of the mounting holes. This will keep the board at the same voltage potential as your body until you can pick up the static shielding bag and put the board back in it. Electrical, Mechanical, and Environmental Specifications The nominal board dimensions are 42mm x 42mm (1.654” x 1.654”). Additional mechanical board dimension information is included on the mechanical drawing shown in Appendix A, Figure . On the physical board itself, connectors include pin 1 indictors as either an arrow, or triangle point near pin 1 on the outer layer silk screen. The environmental specifications are as follows: • Operating temperature: 0°C to 55°C • Storage temperature: -40°C to 75°C • Humidity: <95% without condensation 3 CSI2 to Parallel Bridge Board User’s Guide Functional Description Figure 1. CSI2 to Parallel Bridge Board Revision B Voltage Regulators The CSI2 to Parallel Bridge Board power is supplied by the 5V DC power applied at connectors J7 and J8, pins 1, 2, 39 and 40. The on-board linear voltage regulators then provide the necessary supply voltages to power the sensor: 2.7V, VDDIO, 1.2V, 1.8V, 2.5V and 3.3V. The regulator in location U10 can be configured as shown in Table 1. Table 1. CSI2 to Parallel Bridge Board Regulator Voltages Supply V1P8_V3P3 Voltage Regulator On HDR-60 Base Board Resistor Ratio R45/R50 1.8V R58/R50 2.5V R59/R50 3.3V Comment Jumper J253 short: 1.8V: 1 and 2 2.5V: 3 and 4 (default configuration) 3.3V: 5 and 6 Each of the LT3025 regulators are the linear low dropout voltage type that incorporate an external resistor divider voltage feedback to divide down the regulator output voltage and compare it against an internal reference voltage. The regulator then adjusts the output voltage higher or lower such that the resistor divided voltage matches the internal reference. By doing this, each regulator output voltage remains at a constant voltage value independent of the load it drives. Each regulator output voltage follows this equation: VOUT = (1 + resistor ratio) x (regulator internal reference voltage) See the LT3025 device data sheet for additional details about this device. The default configuration for J253 is for 2.5V via shorting pins 3 and 4 as shown in Figure 2. 4 CSI2 to Parallel Bridge Board User’s Guide Figure 2. CSI2 to Parallel Bridge Board with Sony IMX169 CSI2 Sensor J253: • Short Pins 3 to 4 MEMS Oscillator (Y2) As shown in Figure 2, J5 is set such that the IMX169 sensor will receive a clock input signal from the internal 27.000 MHz MEMS oscillator (Y2). The alternate position of J5 will select the HDR-60 Base Board oscillator for the sensor clock input. High-Speed CSI2 Connector (J8) The Sony IMX169 (U12) will produce high-speed CSI2 differential signals after proper configuration via SCLK and SADDR pins. There is a CSI2 differential clock and up to four CSI2 differential data lanes. The J8 connector can plug into the MachXO2 Dual Sensor Interface Board or into the HDR-60 Base Board. The signals are identified in Table 2. Table 2. CSI2 to Parallel Bridge Board (J8) J8 Pin IMX169 I/O Pin Signal Polarity 13 K4 CSI2 data0 P Differential CSI2 data 11 J4 CSI2 data0 N Differential CSI2 data 29 K6 CSI2 data1 P Differential CSI2 data 27 J6 CSI2 data1 N Differential CSI2 data 21 K3 CSI2 data2 P Differential CSI2 data 19 J3 CSI2 data2 N Differential CSI2 data 26 K7 CSI2 data3 P Differential CSI2 data 24 J7 CSI2 data3 N Differential CSI2 data 18 K5 CSI2 clock P Differential CSI2 clock 16 J5 CSI2 clock N Differential CSI2 clock 12 J4 CSI2 low speed data bit 0 — Single-ended CSI2 data 0 N side 5 Description CSI2 to Parallel Bridge Board User’s Guide Parallel Connector (J7) Connector J7 is primarily reserved for future use. When used with the MachXO2 Dual Sensor Interface Board, only a few pins are used as shown in Table 3. Table 3. CSI2 to Parallel Bridge Board (J7) J7 Pins IMX169 I/O Pin Signal Polarity 30 K4 CSI2 low speed data bit 0 — Single-ended CSI2 data 0 P side 28 C5 I2C SCLK — Serial clock to program IMX169 — Serial address to program IMX169 — Reserved for future use via iCE40 26 B5 2 I C SADDR 9-25, 27, 29, 31 Description References • RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge • HDR-60 Video Camera Development Kit web page • DS1021, LatticeECP3 Family Data Sheet • HB1009, LatticeECP3 Family Handbook • EB59, HDR-60 Base Board User’s Guide • EB69, MachXO2 Dual Sensor Interface Board User’s Guide • QS010, LatticeECP3 Video Camera Development Kit QuickSTART Guide Ordering Information The CSI2 to Parallel Bridge Board is designed solely for use with the MachXO2 Dual Sensor Interface Board and/or the HDR-60 Video Camera Development Kit. Description Ordering Part Number CSI2 to Parallel Bridge Board LF-C2P-EVN MachXO2 Dual Sensor Interface Board LCMXO2-4000HE-DSIB-EVN HDR-60 Video Camera Development Kit (Contains: HDR-60 Base Board with LatticeECP3 FPGA pre-loaded with Image Signal Processing (ISP) LFE3-70EAHDR60-DKN Demo, two USB cables, HDMI cable with HDMI-to-DVI adapter, 12V AC adapter power supply, QuickSTART Guide) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 6 China RoHS Environment Friendly CSI2 to Parallel Bridge Board User’s Guide Revision History Date Version December 2012 01.0 Initial release. Change Summary February 2013 01.1 Clarify that CSI-2 is for use with MachXO2. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 7 8 A B C D 5 5 3 2 4 3 9. POWER AND DECAPS 2 8. LEVEL TRANSLATOR CONNECTION 7. REGULATOR CONNECTION 6. BANK0 & BANK1 5. BANK2 & BANK3 4. I2C BYPASS CONNECTION 3. BOTTOM CONN CONNECTION 2. BLOCK DIAGRAM 1. INDEX MIPI IMX NANOVESTA REV 2 4 Title Date: Size B MIPI_IMX_NANOVESTRA_REV_2 Thursday, October 25, 2012 Document Number <Doc> 1 Sheet 1 1 of 9 Rev 2 A B C D CSI2 to Parallel Bridge Board User’s Guide Appendix A. Schematic Index A B C D 5 3 2 1 LVDS(0,1,2,3,CLK) 4 LEVEL TRANSLATOR (Sheet 8) 4 DPHY(0) BOTTOM HIGH SPI CONNECTOR (Sheet 3) REGULATORS (Sheet 7) BANK 3 (Sheet 5) SADDR/SCLK FLASH (M25P80) (Sheet 4) BANK 2 (Sheet 5) CM81 CM 1 iCE40 iCE 40 BANK 0 (Sheet 6) 3 BANK 1 (Sheet 6) SPI (Sheet 4) BLOCK DIAGRAM MIPI 9 SONY SENSOR DNI 2 1 Title Date: Size B Sunday, October 28, 2012 Document Number <Doc> MIPI_IMX_NANOVESTRA_REV_2 1 2 3 1 Sheet 2 of 9 BOTTOM PARALLEL CONNECTOR (Sheet 3) SADDR/SCLK 2 TI CONNECTOR (Sheet 4) 3 OSCILLATOR (Sheet 8) 4 NOT USED (Sheet 4) 5 Re v 2 A B C D CSI2 to Parallel Bridge Board User’s Guide Block Diagram 10 A B C D 5 GND FITTING2 PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 FITTING1 BOSS2 PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 BOSS1 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 BOSS1 PART_NUMBER = DF12(4.0)-40DP-0.5V Manufacturer = HIROSE FITTING2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 FITTING1 J8 DF12(4.0)-40DP-0.5V_HEADER GND 0 TP1 SLVS_3N_CSI_3N_HISPI SLVS_3P_CSI_3P_HISPI SLVS_CLKN_CSI_CKN_HISPI SLVS_CLKP_CSI_CKP_HISPI LED_CMOS_CSI0N_HISPI R101 V5P0_OR 3 SLVS_3N_CSI_3N_HISPI SLVS_3P_CSI_3P_HISPI FITTING2 PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 FITTING1 BOSS2 PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 BOSS1 BOSS1 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PART_NUMBER = DF12(4.0)-40DS-0.5V Manufacturer = HIROSE FITTING2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 FITTING1 J7 DF12_40DS-0.5V_RECEPTACLE GND R11 10.0K 1% V1P8 TP5 PIXCLK FRAME_VALID D04 D00 D05 D01 D08 D09 ECP3_PRL_SADDR ECP3_PRL_SCLK ICE40_SS_CSI_0_CMOS_LT V5P0_OR PIXCLK [4,6] FRAME_VALID [4,6] D04 [4,6] D00 [4,6] D05 [4,6] D01 [4,6] D08 [4,6] D09 [4,6] ECP3_PRL_SADDR [4,8] ECP3_PRL_SCLK [4,8] ICE40_SS_CSI_0_CMOS_LT 4 3 Fitting & Boss have no electrical function, can be used as vias GND V5P0_OR BOTTOM - PARALLEL to ECP3 2 1 [4] [5] [5] [5] [5] [5] [5] 2 SLVS_0P_HISPI SLVS_0N_HISPI Dat e: Size B Title SLVS_0P_HISPI J251 3 1 3 1 V5P0_OR J252 3 1 Sunday, October 28, 2012 Document Number <Doc> 1 Sheet 3 ICE40_SS_CSI_0_CMOS_LT SLVS_0P_CSI_0P_HISPI SMD_0402_JPR DEFAULT_OPTION = 1&2 2 SMD_1210_JPR DEFAULT_OPTION = 1&2 2 J274 V5P0_TI LED_CMOS_CSI0N_HISPI SLVS_0N_CSI_0N_HISPI SMD_0402_JPR DEFAULT_OPTION = 1&2 2 MIPI_IMX_NANOVESTRA_REV_2 V5P0 SLVS_0N_HISPI of 9 BOTTOM CONN CONNECTIONS SLVS_CLKN_CSI_CKN_HISPI SLVS_CLKP_CSI_CKP_HISPI Fitting & Boss have no electrical function, can be used as vias SLVS_1N_CSI_1N_HISPI SLVS_1P_CSI_1P_HISPI SLVS_2N_CSI_2N_HISPI SLVS_2P_CSI_2P_HISPI EXTCLK LINE_VALID D06 D02 D07 D03 D10 D11 ICE40_SI_CSI_0_CMOS_LT ICE40_SCK_CSI_0_CMOS_LT XCLR_BOTTOM ICE40_SO_CSI_0_CMOS_LT SLVS_1N_CSI_1N_HISPI SLVS_1P_CSI_1P_HISPI [5] [5] [8] EXTCLK [4,6] LINE_VALID [4,6] D06 [4,6] D02 [4,6] D07 [4,6] D03 [4,6] D10 [4,6] D11 [4] ICE40_SI_CSI_0_CMOS_LT [4] ICE40_SCK_CSI_0_CMOS_LT [5] XCLR_BOTTOM [4] ICE40_SO_CSI_0_CMOS_LT SLVS_2N_CSI_2N_HISPI SLVS_2P_CSI_2P_HISPI [5] [5] SLVS_0N_CSI_0N_HISPI SLVS_0P_CSI_0P_HISPI V5P0_OR BOTTOM - HIGH SPI to ECP3 4 Hirose DF12 Series Hirose DF12 Series 5 Rev 2 A B C D CSI2 to Parallel Bridge Board User’s Guide Bottom Conn Connections 11 A B [8] U16F iCE40 iC SEC 6/6 6 5 SADDR_BOTTOM [3,4] [3,4] [3,4] ICE40_SCK_CSI_0_CMOS ICE40_SS_CSI_0_CMOS G7 F7 ICE40_SS_CSI_0_CMOS_LT 1% V1P8_3_3V J277 3 1 [5,6] 7 8 SF8K_SADDR1 SADDR 3PIN_SMD_0603 DEFAULT_OPTION = Install 0/0603 Resitor DEFAULT 1&2 2 ICE40_SO_CSI_0_CMOS_LT GND R153 10K 10 11 ICE40_SCK_CSI_0_CMOS ICE40_SS_CSI_0_CMOS 13 12 ICE40_SO_CSI_0_CMOS 14 ICE40_SI_CSI_0_CMOS GND C27 100nF V3P3 16V V3P3 ICE40_SI_CSI_0_CMOS ICE40_SO_CSI_0_CMOS GND H7 G6 H8 V3P3 C928 0.1uF 16V V3P3 ICE40_SCK_CSI_0_CMOS_LT PIOS_SPI_SS_B SPI SS S PIOS_SPI_SCK S_SPI_SC PIOS_SPI_SI OS_SPI_ OS_SPI_S PIOS_SPI_SO OS_SPI_S iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 SPI SPI_VCC SPI SPI_VC VC NOT USED SED C D 5 TXB0104DR NC1 NC2 A4 A3 A2 A1 VCCA ICE40_SI_CSI_0_CMOS ICE40_SS_CSI_0_CMOS 4 [6] 1 3 5 MOSI GND [8] NC_+5V HDR_2X3 MISO SCLK SS J273 6 9 5 4 3 2 1 1 4 3 2 GND VCC D C HOLD_L 5 6 7 8 3 0 ICE40_SO_CSI_0_CMOS_LT 3 1 [3,4] [5,6] SF8K_SCLK SCLK [3,4] [3,4] 3 3PIN_SMD_0603 DEFAULT_OPTION = Install 0/0603 Resitor DEFAULT 1&2 2 J276 ICE40_SI_CSI_0_CMOS_LT ICE40_SS_CSI_0_CMOS_LT ICE40_SCK_CSI_0_CMOS_LT [3,4] [3,4] ICE40_SO_CSI_0_CMOS ICE40_SI_CSI_0_CMOS_LT V5P0 GND C28 100nF 16V V1P8_3_3V R24 10.0K 1% GND V3P3 [6] C927 0.1uF 16V ICE40_SCK_CSI_0_CMOS V3P3 M25P80-VMW6TG Manufacturer = MICRON PART_NUMBER = M25P80-VMW6TG VSS W_L Q S_L U14 V1P8_3_3V R102 GND R12 10.0K 1% V3P3 SCLK_BOTTOM 2 4 6 LT_TXB0104DR PART_NUMBER = TXB0104DR Manufacturer = TI GND OE B4 B3 B2 B1 VCCB U15 4 1 2 V3P3 37 38 35 36 34 Date: Size B Title Thursday, October 25, 2012 Document Number <Doc> MIPI_IMX_NANOVESTRA_REV_2 RESET_BAR V5P0_TI ECP3_PRL_SADDR ECP3_PRL_SCLK D01 D00 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 FRAME_VALID LINE_VALID PIXCLK DNL 33 GND R31 31 32 29 30 27 28 25 26 13 14 15 16 17 18 19 20 21 22 23 24 11 12 10 9 8 7 6 4 5 1 2 3 PART_NUMBER = 0541043631 Manufacturer = MOLEX MECH1 MECH2 AFE_D14 AFE_D15 SPI_EN AFE_RESET SPI_SDO SPI_SCLK I2C_SCLK I2C_SDATA AFE_D1 AFE_D0 GND4 GND5 AFE_D13 AFE_D12 AFE_D11 AFE_D10 AFE_D9 AFE_D8 AFE_D7 AFE_D6 AFE_D5 AFE_D4 AFE_D3 AFE_D2 AFE_VD AFE_HD GND3 AFE_CLK GND2 EXT_CLK GND1 VCC5.5_1 VCC5.5_2 VCC3.3_1 VCC3.3_2 VCC3.3_3 0541043631 J9 [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] [3,6] 1 Sheet RESET_BAR 4 [6] of ECP3_PRL_SADDR [3,8] ECP3_PRL_SCLK [3,8] D01 D00 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 FRAME_VALID [3,6] LINE_VALID [3,6] PIXCLK 9 I2C BYPASS CONNECTION 2 Rev 2 A B C D CSI2 to Parallel Bridge Board User’s Guide 12C Bypass Connection A B C XCLR_SONY R115 1 SLVS_CLKN_LVDS SLVS_0P_HISPI SLVS_0P_LVDS DMO1P VCAP2 VCAP1 XVS SDO DCKN DCKP DMO3N DMO3P DMO2N DMO2P DMO1N SLVS_2P_CSI_2P SLVS_2N_CSI_2N SLVS_3P_CSI_3P SLVS_3N_CSI_3N SLVS_CLKP_CSI_CKP SLVS_CLKN_CSI_CKN R114 R103 K3 J3 K7 J7 K5 J5 A5 A6 E1 4 SLVS_2P_LVDS VCCIO_2_J5 O_2_J5 CONFIG V1P8 GND SLVS_2N_LVDS DEFAULT_OPTION = 2&3 3 DPR32 0 DEFAULT_OPTION = 2&3 4 5 GND J272 [3] DEFAULT_OPTION = 2&3 DPR33 0 SLVS_3P_LVDS V1P8 2 Title Date: Size B Monday, October 29, 2012 Document Number <Doc> S heet DEFAULT_OPTION = 2&3 DPR34 0 1 5 of 9 Rev 2 [3] SLVS_3N_LVDS SLVS_3N_CSI_3N_HISPI SLVS_3N_CSI_3N 3 SLVS_3N_LVDS 1 2 DEFAULT_OPTION = 2&3 [6] [6] [6] [6] [3] SLVS_CLKP_LVDS SLVS_CLKP_CSI_CKP_HISPI SLVS_CLKP_CSI_CKP 3 SLVS_CLKP_LVDS 1 DPR37 0 [6] [6] [6] [6] SLVS_CLKN_LVDS_1 SLVS_CLKP_LVDS_1 SLVS_2N_LVDS_1 SLVS_2P_LVDS_1 SLVS_3N_LVDS_1 SLVS_3P_LVDS_1 2 J279 SMD_0402_JPR DEFAULT_OPTION = 1&2 MIPI_IMX_NANOVESTRA_REV_2 [3] [6] R433 300 1 SLVS_CLKN_LVDS_1 SLVS_CLKP_LVDS_1 SLVS_0N_LVDS_1 SLVS_0P_LVDS_1 SLVS_1N_LVDS_1 SLVS_1P_LVDS_1 SLVS_2N_LVDS_1 SLVS_2P_LVDS_1 SLVS_3N_LVDS_1 SLVS_3P_LVDS_1 SLVS_1N_LVDS_1 R432 220 [3] C2 B2 B1 C1 D2 C3 D1 E1 F1 F3 E2 D3 E3 E4 G2 H2 G3 G1 SLVS_1P_LVDS_1 GND SLVS_3P_CSI_3P_HISPI SLVS_3P_CSI_3P 2 3 SLVS_3P_LVDS 1 DEFAULT_OPTION = 2&3 DPR36 0 R449 DNL SLVS_1N_CSI_1N_HISPI SLVS_1N_CSI_1N 3 SLVS_1N_LVDS 2 120 R430 120 R422 V1P8 R431 220 PIO3_DP00A PIO3_DP00B PIO3_DP01A PIO3_DP01B PIO3_DP0 PIO3_DP02A PIO3_DP0 IO3_DP PIO3_DP02B PIO3_DP0 PIO3_DP03A PIO3_DP0 O3_DP PIO3_DP03B PIO3_DP0 PIO3_DP04A PIO3_DP0 PIO3_DP04B PIO3_DP0 PIO3_DP05A PIO3_DP0 O3_DP0 GBIN7_PIO3_DP05B GB PIO3_DP0 GBIN6_PIO3_DP06A GB PIO3_DP0 PIO3_DP06B PIO3 DP0 P0 PIO3_DP07A PIO3_DP07B PIO3_DP08A PIO3_DP08B iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 SLVS_1N_LVDS 1 iCE40 SEC 4/6 VCCIO_3_H3 U16D SLVS_1P_LVDS H3 2 PLACE close to the device U16 NOTE: GND V1P8 470 R420 1% V2P5 J278 SMD_0402_JPR DEFAULT_OPTION = 1&2 [3] [6] 2 GND R15 10.0K 1% V2P5 SLVS_0N_LVDS_1 R429 300 R428 220 SLVS_2N_CSI_2N_HISPI SLVS_2N_CSI_2N 2 3 SLVS_2N_LVDS 1 DEFAULT_OPTION = 2&3 DPR35 0 R448 DNL 1 SLVS_0P_LVDS_1 R427 220 E6 H6 G5 H5 H1 J2 J1 J3 J4 H4 G4 LED14 PART_NUMBER = SML-512MWT86 Green SLVS_1P_CSI_1P_HISPI SLVS_1P_CSI_1P 3 SLVS_1P_LVDS 2 120 R426 120 R421 1 SLVS_0N_LVDS SLVS_0P_LVDS V1P8 CDONE CRESET_B PIO2_CBSEL0 PIO2_CBS IO2_CBS PIO2_CBS PIO2_CBSEL1 IO2_CBS PIO2_3 PIO2_4 PIO PIO2_5 PIO PIO2_6 PIO PIO2_7 PIO GBIN4_PIO2 GBIN4_P GBIN5_PIO2 GBIN5_P iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 DPR31 0 [3] [6] TP3 TP2 iCE40 SEC 3/6 DEFAULT_OPTION = 2&3 [3] [6] SLVS_0N_HISPI SLVS_0N_LVDS SLVS_2P_CSI_2P_HISPI SLVS_2P_CSI_2P 2 3 SLVS_2P_LVDS 3 1 2 1 SLVS_0N_DPHY AGND DPR26 0 DEFAULT_OPTION = 2&3 SLVS_0N_DPHY AGND C898 0.22UF 6.3V SLVS_1N_CSI_1N C899 0.22UF 6.3V SLVS_1P_CSI_1P K6 J6 H1 SLVS_0N_CSI_0N 10 1% 10 1% SLVS_0P_CSI_0P K4 J4 IMX169CQKC Manufacturer = SONY PART_NUMBER = IMX169CQK-C TEST5 TEST4 TEST3 TEST2 TEST1 XCLR DMO0P DMO0N SEC 2/3 SLVS_0N_CSI_0N [6] [3] K2 J2 E2 B8 A8 C6 XCE SDA SCL INCK U12B J5 U16C DPR38 0 [3] [6] [3] [6] SLVS_0P_DPHY SLVS_CLKN_CSI_CKN_HISPI SLVS_CLKN_CSI_CKN 3 4 2 3 XCLR_iCE XCLR_BOTTOM DPR25 0 DEFAULT_OPTION = 2&3 SLVS_0P_DPHY SLVS_CLKN_LVDS 2 3 1 10 1% B6 B5 0 SADDR R104 SMD_0402_JPR DEFAULT_OPTION = 1&2 2 J275 1 SLVS_0P_CSI_0P [5] V1P8 A7 C5 10 1% SCLK R116 R111 1K 1% PLACE resistors R103, R114, R115, R116, CLOSE TO THE SONY SENSOR PINS XCLR_SONY SADDR [4,6] [5] SCLK [4,6] SONY_INCK R110 1K 1% V2P5 BANK 2 BANK2 AND BANK3 R419 3 1 2 SONY_INCK 4 1 2 V1P8 4 BANK 3 4 2 3 [6,8] 1 2 3 1 2 3 1 2 3 3 D 1 2 3 1 2 3 1 2 3 2 1 240 1% 1 2 3 1 2 3 1 2 3 SONY SENSOR 1 NOT USED 2 LED15 PART_NUMBER = SML-512MWT86 Green 1 NOT USED 3 5 A B C D Bank2 and Bank3 A B C 5 120 R434 120 R423 VCCIO_0_A5 O_0_A5 R450 DNL V1P8 R71 R72 R73 R74 R75 R76 R77 R81 R82 R83 R84 R85 R86 R87 R88 4 SLVS_3N_LVDS SLVS_3N_LVDS C91 0.1uF 16V V1P8_3_3V 120 R438 120 R424 GND C57 0.1uF 16V C93 0.1uF 16V GND C58 0.1uF 16V DECAPS FOR BANK1 V1P8 3 R441 220 3 C6 U16B SEC 2/6 iCE40 VCCIO_1_C6 IO_ IO_1_C6 GBIN2_PIO1_1 GBIN3_PIO GBIN3_PIO1_2 BIN3_PIO PIO1_3 P PIO PIO1_4 PIO PIO1_5 PIO PIO1_6 PIO PIO1_7 PIO PIO1_8 PIO PIO1_9 PIO PIO1_10 PIO PIO1 PIO1_11 PIO PIO1 PIO1_12 PIO1 O PIO1_13 PIO1_14 PIO1_15 SLVS_3N_LVDS_1 SLVS_CLKN_LVDS SLVS_CLKP_LVDS C95 0.1uF 16V GND C59 0.1uF 16V DECAPS FOR BANK2 V2P5 D8 E8 F8 G8 D6 E7 D7 D9 B9 C9 A9 H9 J8 G9 J9 2 2 1 SLVS_CLKN_LVDS SLVS_CLKP_LVDS SF8K_SADDR1 [4] [5] [5] SLVS_CLKP_LVDS_1 J282 SMD_0402_JPR DEFAULT_OPTION = 1&2 SLVS_CLKN_LVDS_1 R445 300 R444 220 V1P8 R451 DNL R443 220 SF8K_SADDR1 SLVS_0P_DPHY SLVS_0N_DPHY SONY_INCK [5,8] SADDR [4,5] SF8K_SCLK [4] SCLK [4,5] RESET_BAR [4] XCLR_iCE [5] V1P8 GND 3 Date: Size B Title GND C60 0.1uF 16V Thursday, October 25, 2012 Document Number <Doc> MIPI_IMX_NANOVESTRA_REV_2 C97 0.1uF 16V V1P8 1 Sheet DECAPS FOR BANK3 120 R439 120 R425 SLVS_0P_DPHY SLVS_0N_DPHY SONY_INCK R446 DNI SF8K_SCLK R447 DNI RESET_BAR XCLR_iCE 6 of 9 SLVS_CLKN_LVDS_1 SLVS_CLKP_LVDS_1 BANK0 AND BANK1 PLACE close to the device U16 NOTE: [5] [5] [5] [5] iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 SLVS_3P_LVDS_1 V1P8 J281 SMD_0402_JPR DEFAULT_OPTION = 1&2 SLVS_3N_LVDS_1 R442 300 SLVS_3P_LVDS_1 R440 220 V1P8 R452 DNL V1P8 LINE_VALID [3,4] D06 [3,4] D02 [3,4] D07 [3,4] D03 [3,4] D10 [3,4] D11 [3,4] PIXCLK [3,4] FRAME_VALID [3,4] D04 [3,4] D00 [3,4] D05 [3,4] D01 [3,4] D08 [3,4] D09 [3,4] GND [5] [5] SLVS_3P_LVDS LINE_VALID D06 D02 D07 D03 D10 D11 PIXCLK FRAME_VALID D04 D00 D05 D01 D08 D09 SLVS_3P_LVDS 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 V1P8 J280 SMD_0402_JPR DEFAULT_OPTION = 1&2 SLVS_2N_LVDS_1 [5] [5] 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% GND R436 220 SLVS_2N_LVDS_1 R437 300 SLVS_2P_LVDS_1 R435 220 iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 C4 C5 B8 B7 A8 B6 A7 A6 B5 A4 E5 A3 B4 A2 D5 B3 A1 SLVS_2P_LVDS_1 GBIN0_PIO0_1 GBIN1_PIO0_2 PIO0_3 PIO PIO0_4 PIO PIO0_5 PIO PIO0_6 PIO PIO0_7 PIO PIO0_8 PIO PIO0_9 PIO PIO0_10 PIO PIO0 PIO0_11 PIO0 O0 PIO0_12 PIO0 PIO0_13 PIO0 O0 PIO0_14 PIO0_15 PIO0_16 PIO0_17 DECAPS FOR BANK0 SLVS_2N_LVDS SLVS_2N_LVDS [5] SLVS_2P_LVDS SLVS_2P_LVDS [5] iCE40 SEC 1/6 3 A5 U16A 1 V1P8_3_3V 2 BANK 0 2 3 BANK B ANK 1 D 4 1 NOT USED 2 NOT USED 1 5 Re v 2 [5] [5] A B C D Bank0 and Bank1 A B C D 5 GND GND C84 0.1uF 16V C78 0.1uF 16V V1P2 GND GND 5% GND R47 5% C9 10uF/6V3 6.3V R49 1R 5% V5P0 1ms RC GND GND C11 10uF/6V3 6.3V R34 1R 5% V5P0 C4 10uF/6V3 6.3V R32 1R 5% V5P0 1ms RC GND 6 3 6 3 6 R117 0 3 6 R106 0 3 EN IN U6 LTC3025 EN IN U9 LTC3025 EN IN U4 LTC3025 EN IN U5 LTC3025 C33 0.01uF 25V C32 0.01uF 25V GND 100K-0402SMT R57 C16 10uF/6V3 6.3V 100K-0402SMT C79 0.1uF 16V V1P8 GND C80 0.1uF 16V R48 1R 5% V5P0 1 BIAS GND PWP GND GND GND ADJ OUT R13 10.0K 1% 5 4 5 4 GND 5 GND ADJ OUT 5 4 4 GND LTC3025EDC#PBF ADJ OUT 4 LTC3025EDC#PBF ADJ OUT R43 57.6K R0402 1% GND R22 10.0K R0402 1% R23 73.2K R0402 1% R20 GND 10.0K R0402 1% R16 20K R0402 1% C21 10uF/6V3 6.3V C13 10uF/6V3 6.3V C5 10uF/6V3 6.3V C12 10uF/6V3 6.3V GND R46 GND 10.0K R0402 1% R44 34.8K R0402 1% GND LTC3025EDC#PBF 4 LTC3025EDC#PBF GND 2 7 1 BIAS GND PWP 2 7 1 BIAS GND PWP DNI-0603SMT DNI-0603SMT GND DNI-0603SMT R19 V3P3 V3P3 3.3v 300mA GND R14 V1P2 V1P2 1.2v 300mA GND R40 V1P8 V1P8 1.8v 300mA GND DNI-0603SMT R41 V2P7 V2P7 2.7v 300mA 3 3 C81 0.1uF 16V GND 6 R109 0 3 U10 LTC3025 EN IN C6 10uF/6V3 6.3V GND 3 6 EN IN 5 4 1&2 3&4 5&6 GND 5 4 2 ADJ OUT 5 4 J253 GND GND Date: Size B Title GND R21 10.0K R0402 1% R18 20K R0402 1% GND R53 10.0K R0402 1% 1 DNI-0603SMT GND DNI-0603SMT R17 V1P2_VDD V1P2_VDD 1.2v 300mA GND R55 V2P5 GND Thursday, October 25, 2012 Document Number <Doc> GND C22 10uF/6V3 6.3V GND DNI-0603SMT R42 V1P8_3_3V 1 Sh e e t 7 of 9 Rev 2 V1P8_3_3V 1.8V or 2.5V or 3.3V 300mA R50 10.0K R0402 1% MIPI_IMX_NANOVESTRA_REV_2 C7 10uF/6V3 6.3V 34.8K R0402 52.3K R0402 73.2K R0402 V2P5 2.5v 300mA V1P8 V2P5 3_3V VOLTAGE C20 10uF/6V3 6.3V 34.8K 52.3K 73.2K VALUE R54 52.3K R0402 1% SHUNT LTC3025EDC#PBF ADJ OUT 1 2 R45 1% 3 4 R58 1% 5 6 R59 1% 2x3_HEADER_100mil LTC3025EDC#PBF ADJ OUT GND U8 LTC3025 EN IN U11 LTC3025 R107 0 6 R108 0 3 2 REGULATOR CONNECTIONS LTC3025EDC#PBF R33 1R 5% V5P0 C19 10uF/6V3 6.3V R56 1R 5% V5P0 C23 10uF/6V3 6.3V GND GND C76 0.1uF 16V GND GND GND C77 0.1uF 16V R52 1R 5% V5P0 1 BIAS 2 7 GND PWP 1 BIAS 2 7 GND PWP 1 BIAS GND PWP 2 7 2 7 1 BIAS GND PWP 2 7 5 A B C D Regulator Connections 5 1 2 4 [3] EXTCLK 3 2 1 EXTCLK_OSC SMD_0603_JPR DEFAULT 1&2 J5 EXTCLK 4 EN VCC 3 R28 27 GND OUT 1% 27 MHZ DI Part Number = DSC1001AE2-27.0000 Manufacturer = DISCERA 3 SONY_INCK SONY_INCK [5,6] [4] [4] SADDR_BOTTOM SCLK_BOTTOM 1% V1P8 GND 2 C25 100nF 16V V1P8 R152 10K V1P8 6 4 5 3 TXS0102DC GND B2 B1 VCCB 2 1 8 7 Title GND R112 1K 1% V1P8_3_3V MIPI_IMX_NANOVESTRA_REV_2 TXS0102DC PART_NUMBER = TXS0102DCUR Manufacturer = TI OE A2 A1 VCCA U13 R113 1K 1% Sheet V1P8_3_3V 8 of ECP3_PRL_SCLK 9 ECP3_PRL_SADDR GND C26 100nF 16V V1P8_3_3V [3,4] Rev 2 [3,4] C D Date: Size B Sunday, October 28, 2012 Document Number <Doc> 1 A GND 4_7K 1 LEVEL TRANSLATOR CONNECTIONS 2 A GND R150 1% Place R28 near Y2 3 B GND C10 1uF 6.3V Y2 OSCILLATOR 4 B C FB1 BLM21AG601SN1D C225 0.1uF 16V V1P8 1 2 D 5 Level Translator Connections A C8 V1P8_VDDM 5 AGND C916 10UF 10V PART_NUMBER = 74437324047 4.7UH L41 1 2 V2P7_VDDH C915 10UF 10V VSSL1 VSSL2 VSSL3 VSSL4 VSSL5 VSSL6 VSSL7 VSSL8 VRL VCP B7 C4 D7 F2 F3 G7 H4 H7 B3 A3 B4 C2 D2 G2 G3 H2 H8 C913 0.1uF 16V C123 1uF 16V C921 1uF 16V C909 0.1uF 16V C914 0.1uF 16V C910 0.1uF 16V C125 1uF 16V C127 1uF 16V C126 1uF 16V C908 1uF 16V C911 0.1uF 16V AGND GND R105 C124 1uF 16V C920 0.1uF 16V C912 0.1uF 16V IMX169CQKC Manufacturer = SONY PART_NUMBER = IMX169CQK-C VDDM VDDL1 VDDL2 VDDL3 VDDL4 VDDL5 VSSH1 VSSH2 VSSH3 VSSH4 VSSH5 VSSH6 VSSH7 DECAPS FOR V2P7 C7 E3 F1 H5 H6 V1P2_VDDL VDDH1 VDDH2 VDDH3 VDDH4 VDDH5 VDDH6 VDDH7 SEC 1/3 SONY SENSOR B V2P7 A4 C1 C9 D1 G1 H3 H9 V2P7_VDDH U12A 4 0 AGND 4 V1P2 C917 10UF 10V GND V1P8 C922 10UF 10V iCE40 SEC 5/6 SE GND_1 GND_ GND_2 GN GND_ GND_3 GND GND_ GND_4 GND GND_ PLLGND PLLGN GN iCE40_CM81 Manufacturer = LATTICE PART_NUMBER = iCE40 PLLVCC LLVCC LVCC VCC_1 CC_1 VCC_2 CC_2 VCC_3 CC_3 VPP_FAST PP_FAST VPP_2V5 PP_2V5 C905 0.1uF 16V C901 0.1uF 16V C906 1uF 16V C900 0.1uF 16V C907 1uF 16V C903 0.1uF 16V C136 1uF 16V C902 0.1uF 16V L43 4.7UH 2 3 V1P8_VDDM C924 10UF 10V C919 0.1uF 16V DECAPS FOR VIP8 C923 10UF 10V 1 J7 D4 F2 E9 C7 C8 U16E DECAPS FOR VIP2 PLLVCC_G2 PART_NUMBER = 74437324047 4.7UH L42 2 1 V1P2_VDDL AGND C897 2.2UF 16V V1P2_VDD TP4 V2P5 3 NOT USED C D 5 J6 F5 F4 F9 F6 GND C918 1uF 16V C137 1uF 16V C904 0.1uF 16V GND 1 C138 1uF 16V GND PLLGND_H2 2 R119 100 V1P2_VDD C926 10UF 10V C87 0.1uF 16V PLLGND_H2 GND D at e: Size B Title C71 0.1uF 16V C74 0.1uF 16V C73 0.1uF 16V C53 0.1uF 16V C89 0.1uF 16V GND Thursday, October 25, 2012 Document Number <Doc> MIPI_IMX_NANOVESTRA_REV_2 V2P5 1 Sheet C54 0.1uF 16V DECAPS FOR V2P5 C70 0.1uF 16V 9 GND of C75 0.1uF 16V R120 DECAPS FOR V1P2_VDD PLLVCC_G2 V1P2_VDD 1% 0 9 Rev 2 AGND SENSOR POWER AND DECAPS 2 A B C D Sensor Power and Decaps