LT8602 - 42V Quad Monolithic Synchronous Step-Down Regulator

LT8602
42V Quad Monolithic
Synchronous Step-Down
Regulator
Description
Features
Flexible Power Supply System Providing Four
Outputs with a Wide Input Range
n Two High Voltage Synchronous Buck Regulators:
3V to 42V Input Voltage Range
Output Currents Up to 2.5A and 1.5A
High Efficiency Up to 93%
n Two Low Voltage Synchronous Buck Regulators:
2.6V to 5.5V Input Voltage Range
Output Currents Up to 1.8A and 94% Efficiency
n Resistor Programmable and Synchronizable
250kHz to 2.2MHz Switching Frequency
n Low Ripple Burst Mode® Operation:
30µA IQ at 12VIN
Output Ripple < 15mV
n Programmable Power-On Reset
n Power Good Indicators
n2-Phase Clock Reduces Input Current Ripple
n Available in Thermally Enhanced 40-Lead QFN
(6mm × 6mm) Package
The LT®8602 is a quad channel, current mode, monolithic
buck switching regulator with a programmable power-on
reset. All regulators are synchronized to a single oscillator
with an adjustable frequency from 250kHz to 2.2MHz. The
LT8602 can be configured for micropower Burst Mode
operation or pulse-skipping operation at light load. Micropower operation results in quiescent current of 30µA
with all four regulators operating in the application below.
n
The high voltage channels are synchronous buck regulators that operate from an input of 3V to 42V. The output
currents are up to 1.5A (OUT1) and 2.5A (OUT2). The
low voltage channels operate from an input of 2.6V to
5.5V. Internal synchronous power switches provide high
efficiency with output currents up to 1.8A. The LT8602
uses a 2-phase clock with channels 1 and 3 operating 180°
from channels 2 and 4 to reduce input ripple current on
both HV and LV inputs. All channels have cycle-by-cycle
current limit, providing protection against shorted outputs.
Thermal shutdown provides additional protection.
Applications
The LT8602 is available in a 40-lead 6mm × 6mm QFN
package.
Automotive Systems
Distributed Supply Regulation
n Industrial Controls and Power Supplies
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
n
VIN
BST1
PVIN2
SW1
FB1
PVIN1 LT8602
EN/UVLO
POREN
4
2
5V, 3.3V, 1.8V and 1.2V Step-Down Regulators
OUT1
5V, 1.5A
BST2
RST
SW2
FB2
PG1-4
RUN3-4
OUT2
3.3V*
SW3
FB3
PVIN4
OUT3
1.8V, 1.7A
INTVCC
CPOR
2
TRKSS1, 2
RT
SYNC
SW4
FB4
OUT4
1.2V, 1.8A
GND
*IOUT2 = 2.5A – IPVIN3 – IPVIN4
2.0
100
90
1.8
90
1.6
80
70
1.4
70
60
1.2
EFFICIENCY
80
FSW = 1MHz
FSW = 2MHz
50
40
1.0
0.8
0.4
20
0.2
10
0
0.3
0.6
0.9
LOAD CURRENT (A)
0
1.5
1.2
8602 TA01b
0.8
0.7
0.6
FSW = 1MHz
FSW = 2MHz
40
20
0
0.9
EFFICIENCY
50
0.6
POWER
LOSS
1.0
60
30
10
LV Channel Efficiency,
VOUT3 = 1.8V
0.5
0.4
0.3
30
0
0.2
POWER
LOSS
0
0.3
0.6
0.9
1.2
LOAD CURRENT (A)
POWER LOSS (W)
PVIN3
100
POWER LOSS (W)
BIAS
OUT2
HV Channel Efficiency,
VIN = 12V, VOUT1 = 5V
EFFICIENCY (%)
IN
6V TO 42V
EFFICIENCY (%)
Typical Application
0.1
1.5
0
1.8
8602 TA01c
8602 TA01a
8602f
For more information www.linear.com/LT8602
1
LT8602
Absolute Maximum Ratings
Pin Configuration
(Note 1)
CPOR
RST
SYNC
PVIN3
GND
SW3
PVIN1
GND
POREN
TOP VIEW
PG3
Supply Voltages
VIN, PVIN1,2............................................. –0.3V to 42V
PVIN3,4...................................................... –0.3V to 6V
PG1-4, SYNC, TRKSS1-2, RUN3-4, RST Voltages.........6V
RT, FB1-4, CPOR, POREN Voltages...........................3.6V
EN/UVLO Voltage.......................................................42V
BIAS Voltage............................................... –0.3V to 15V
Operating Junction Temperature (Notes 2, 3)
LT8602E............................................. –40°C to 125°C
LT8602I.............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
40 39 38 37 36 35 34 33 32 31
PG1 1
30 RUN3
GND 2
29 RT
SW1 3
28 INTVCC
BST1 4
27 FB3
BST2 5
26 FB1
41
GND
SW2 6
25 FB2
SW2 7
24 FB4
GND 8
23 VIN
GND 9
22 EN/UVLO
BIAS 10
21 TRKSS1
TRKSS2
NC
RUN4
PVIN4
GND
SW4
PVIN2
GND
PG4
PG2
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
θJA = 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8602EUJ#PBF
LT8602EUJ#TRPBF
LT8602UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LT8602IUJ#PBF
LT8602IUJ#TRPBF
LT8602UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8602f
2
For more information www.linear.com/LT8602
LT8602
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Operating Voltage
l
2.7
3
V
Minimum Operating Voltage, to Start
l
3.1
3.5
V
1
VIN Quiescent Current, Shutdown
EN/UVLO = 0.4V
0.1
VIN Quiescent Current, Operating
No Load (Note 4)
100µA on VOUT2 (Note 4)
30
70
EN/UVLO Threshold
EN/UVLO Rising
1.15
EN/UVLO = 2V
–40
EN/UVLO Hysteresis
EN/UVLO Input Current
1.2
µA
µA
µA
1.25
50
V
mV
40
nA
Oscillator
l
1.8
0.225
SYNC Input Frequency Range
l
0.25
SYNC Input Voltage Low
l
SYNC Input Voltage High
l
Switching Frequency
RT = 28.9k
RT = 254k
SYNC Input Current
2
0.25
2.2
0.275
MHz
MHz
2.2
MHz
0.3
V
100
nA
1
1.012
V
0.002
0.01
%/V
100
nA
1.2
V
–100
Channel 1
Feedback Voltage
FB Voltage Line Regulation
0.988
l
–100
VIN = 3V to 42V
Input Current FB1
SW1 Peak Current Limit
l
VIN = PVIN1 = 6V
2.3
SW1 Leakage Current
2.7
3.0
A
0.1
1
µA
SW1 Top On Resistance
ISW1 = 1A
240
mΩ
SW1 Bottom On Resistance
ISW1 = 1A
170
mΩ
Lower FB1 Power Good Threshold
Percentage of VFB1
l
89
92
95
%
Upper FB1 Power Good Threshold
Percentage of VFB1
l
105
108
111
%
PG1 Output Voltage Low
IPG1 = –100μA
l
0.1
0.2
V
l
30
µA
2.4
3.1
μA
PG1 Leakage Current
PG1 = 5V, FB1 = 1V
TRKSS1 Pull-Up Current
SS1 = 0.2V
Minimum Switch-On Time
ISW1 = 1A
60
ns
Minimum Switch-Off Time
ISW1 = 1A
70
ns
1.5
8602f
For more information www.linear.com/LT8602
3
LT8602
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
0.988
1
1.012
V
0.002
0.01
%/V
l
–100
100
nA
Channel 2
Feedback Voltage
FB Voltage Line Regulation
VIN = 3V to 42V
Input Current FB2
SW2 Peak Current Limit
VIN = PVIN2 = 6V
3.5
SW2 Leakage Current
4.0
4.5
A
0.1
1
µA
SW2 Top On Resistance
ISW2 = 1A
150
mΩ
SW2 Bottom On Resistance
ISW2 = 1A
100
mΩ
Lower FB2 Power Good Threshold
Percentage of VFB2
l
89
92
95
%
Upper FB2 Power Good Threshold
Percentage of VFB2
l
105
108
111
%
PG2 Output Voltage Low
IPG2 = –100μA
l
0.1
0.2
V
l
30
µA
2.4
3.1
µA
PG2 Leakage Current
PG2 = 5V, FB2 = 1V
TRKSS2 Pull-Up Current
SS2 = 0.2V
Minimum Switch-On Time
ISW2 = 2A
60
ns
Minimum Switch-Off Time
ISW2 = 2A
70
ns
1.5
Channel 3
Operating Voltage
Feedback Voltage
FB Voltage Line Regulation
l
2.6
l
790
VIN = 3V to 42V
5.5
V
800
810
mV
0.002
0.01
%/V
100
nA
3.1
3.5
A
PVIN3 = 5.5V
0.1
1
µA
SW3 PMOS On Resistance
ISW3 = 1A
150
mΩ
SW3 NMOS On Resistance
ISW3 = 1A
120
mΩ
Input Current FB3
l
SW3 Current Limit
SW3 Leakage
–100
1.8
Lower FB3 Power Good Threshold
Percentage of VFB3
l
89
92
95
%
Upper FB3 Power Good Threshold
Percentage of VFB3
l
105
108
111
%
PG3 Output Voltage Low
IPG3 = –100μA
l
0.1
0.2
V
PG3 Leakage Current
PG3 = 5V, FB3 = 0.8V
l
30
µA
RUN3 Threshold Voltage
RUN3 Input Current
RUN3 = 3.3V
Soft-Start Time
l
0.695
l
–100
0.72
0.75
V
100
nA
1
ms
Minimum Switch-On Time
ISW3 = 1A
70
ns
Minimum Switch-Off Time
ISW3 = 1A
70
ns
PVIN3 UVLO
2.35
2.6
V
8602f
4
For more information www.linear.com/LT8602
LT8602
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Channel 4
Operating Voltage
Feedback Voltage
FB Voltage Line Regulation
l
2.6
l
790
VIN = 3V to 42V
Input Current FB4
l
SW4 Current Limit
5.5
800
810
mV
0.002
0.01
%/V
–100
1.8
V
100
nA
3.1
3.5
A
1
SW4 Leakage
PVIN4 = 5.5V
0.1
SW4 PMOS On Resistance
ISW4 = 1A
150
SW4 NMOS On Resistance
ISW4 = 1A
Lower FB4 Power Good Threshold
Percentage of VFB4
l
89
92
95
%
Upper FB4 Power Good Threshold
Percentage of VFB4
l
105
108
111
%
PG4 Output Voltage Low
IPG4 = –100μA
l
0.1
0.2
V
PG4 Leakage Current
PG4 = 5V, FB4 = 0.8V
l
30
µA
120
RUN4 Threshold Voltage
RUN4 Input Current
RUN4 = 3.3V
l
0.695
l
–100
Soft-Start Time
Minimum Switch-On Time
ISW4 = 1A
Minimum Switch-Off Time
ISW1 = 1A
0.72
mΩ
0.75
V
100
nA
1
ms
70
ns
70
PVIN4 UVLO
µA
mΩ
2.35
ns
2.6
V
Power-On Reset
CPOR Pull-Up Current
CPOR = 0V
POR Delay Time
CPOR = 1000pF
2
31
RST Output Voltage Low
IRST = –100μA
RST Pull-Up Current
POR Timed Out, RST = 0V
RST Leakage Current
RST = 5V, POREN = 0V
l
POREN Threshold
POREN Pull-Up Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8602E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8602I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. High junction temperatures degrade
35.2
39.4
0.1
0.2
30
–40
l
POREN = 0V
μA
ms
V
μA
40
nA
1.15
1.2
1.25
V
0.8
1.2
1.6
μA
operating lifetimes. Operating lifetime is derated at junction temperatures
above 125°C.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
Note 4: All four channels enabled as shown in the application circuit
details of front page application (using the 1MHz component values) found
in the Typical Application section.
8602f
For more information www.linear.com/LT8602
5
LT8602
Typical
Performance Characteristics
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
and PVIN3 = PVIN4 = 3.3V, unless otherwise noted.
Channel 2 Efficiency vs Load
VOUT2 = 3.3V, FSW = 2MHz
100
100
3.6
90
80
80
3.2
80
70
70
2.8
70
50
40
30
PV IN = 12V
PV IN = 28V
PV IN = 42V
10
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
2.4
60
50
40
30
1.6
1.2
20
0.4
10
1.0
1.5
LOAD CURRENT (A)
80
80
70
70
EFFICIENCY (%)
90
40
30
20
10
0
0.0001
0
0.0001
PV IN2 = 5.5V
PV IN2 = 12V
PV IN2 = 28V
0.001
0.01
0.1
LOAD CURRENT (A)
1
40
30
0
0.0001
1 2
8602 G03
4.0
50
10
8602 G04
PVIN4 = 2.6V
PVIN4 = 3.3V
PVIN4 = 5.5V
0.001
0.01
0.1
LOAD CURRENT (A)
3.5
3.0
2.5
2.0
1.5
1 2
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
8602 G06
8602 G05
Channel 2 Peak Current Limit vs
Duty Cycle
Channel 3/Channel 4 Maximum
Output Current vs Duty Cycle
Channel 3/4 Peak Current Limit
vs Duty Cycle
5.0
3
Channel 1 Peak Current Limit vs
Duty Cycle
60
20
PVIN3 = 2.6V
PVIN3 = 3.3V
PVIN3 = 5.5V
0.001
0.01
0.1
LOAD CURRENT (A)
0
2.5
2.0
LV Channel Efficiency vs Load
VOUT4 = 1.2V, FSW = 2MHz
100
90
50
30
8602 G02
LV Channel Efficiency vs Load
VOUT3 = 1.8V, FSW = 1MHz
60
40
10
8602 G01
100
50
0.8
0.5
Channel 2 Efficiency vs Load
VOUT2 = 3.3V, FSW = 1MHz
60
20
0
0.0
1 2
2.0
PVIN2 = 5.5V
PVIN2 = 12V
PVIN2 = 24V
TOP FET CURRENT LIMIT (A)
60
EFFICIENCY (%)
90
EFFICIENCY (%)
90
20
EFFICIENCY (%)
4.0
POWER LOSS (W)
EFFICIENCY (%)
100
Channel 1 Efficiency vs Load
VOUT1 = 8V, FSW = 2MHz
2.0
4.0
4.0
3.5
3.0
3.5
MAX OUTPUT CURRENT (A)
TOP FET CURRENT LIMIT (A)
TOP FET CURRENT LIMIT (A)
1.8
4.5
3.0
2.5
2.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
8602 G07
1.5
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
8602 G08
0
0
20
40
60
DUTY CYCLE (%)
80
100
8602 G09
8602f
6
For more information www.linear.com/LT8602
LT8602
Typical
Performance Characteristics
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
and PVIN3 = PVIN4 = 3.3V, unless otherwise noted.
Switching Frequency vs
Temperature
RT = 30k
RT = 60k
RT = 250k
8
6
TRKSS CURRENT (µA)
FREQUENCY CHANGE (%)
TRKSS Pull-Up Current vs Voltage
4
2
0
–2
–4
–6
RST Pull-Up Current vs Voltage
1
10
0
0
RST CURRENT (µA)
10
–1
–2
–10
–20
–8
10
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
–3
0
0.5
1
1.5
2
2.5
TRKSS VOLTAGE (V)
8602 G10
350
2.00
300
1.75
200
150
0.50
10000
0.25
8602 G13
60
50
CHANNEL 1
0
0.5
1
1.5
SWITCH CURRENT (A)
2
2.5
8602 G16
5
10
15
25 30
VIN (V)
35
40
45
8602 G15
90
ISW = 1A
80
80
CHANNEL 1
CHANNEL 2
70
CHANNEL 2
70
60
CHANNEL 1
50
60
50
20
Minimum On-Time vs
Temperature
Minimum Off-Time vs ISW
90
MINIMUM OFF-TIME (ns)
MINIMUM ON-TIME (ns)
90
70
30
10
25 50 75 100 125 150 175 200 225 250 275
RT (kΩ)
100
CHANNEL 2
3.5
Quiescent Current vs VIN
8602 G14
Minimum On-Time vs ISW
80
3
20
MINIMUM ON-TIME (ns)
100
1.5
2
2.5
RST VOLTAGE (V)
1.00
50
8000
1
40
1.25
0.75
4000
6000
CPOR (pF)
0.5
1.50
100
2000
50
IQ (µA)
FREQUENCY (MHz)
POR DELAY TIME (ms)
2.25
250
0
8602 G12
Switching Frequency vs RT
Power-On Reset Time vs CPOR
0
–30
3.5
8602 G11
400
0
3
0
0.5
1
1.5
2
SWITCH CURRENT (A)
2.5
8602 G17
40
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8602 G18
8602f
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7
LT8602
Typical
Performance Characteristics
and PVIN3 = PVIN4 = 3.3V, unless otherwise noted.
Minimum Off-Time vs
Temperature
180
ISW = 1A
Channel 3/Channel 4 Minimum
On-Time vs ISW
100
160
80
CHANNEL 1
70
CHANNEL 2
60
PVIN = 2.6V
120
100 PVIN = 3.3V
80
60
PVIN = 5.5V
40
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
0.3
0.6
0.9
ISW (A)
8602 G19
Channel 1 RDSON vs Temperature
500
80
70
60
50
20
50
–50 –25
1.2
40
1.5
400
0
0.3
8602 G20
0.6
0.9
ISW (A)
1.2
1.5
8602 G21
Channel 3/Channel 4 RDSON vs
Temperature
Channel 2 RDSON vs Temperature
ISW1 = 1A
Channel 3/Channel 4 Minimum
Off-Time vs ISW
90
140
MINIMUM OFF-TIME (ns)
90
MINIMUM ON-TIME (ns)
MINIMUM OFF-TIME (ns)
100
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
300
ISW2 = 1A
ISW = 1A
250
300
TOP FET
300
200
TOP FET
200
100
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
100
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3.0
45
2.5
CHANNELS 3, 4
2.0
1.5
1.0
0
0.790
25 50 75 100 125 150
TEMPERATURE (°C)
0.0
25
20
VOUT = 3.3V
VOUT = 5V
15
10
0.5
0.990
–50 –25
FULL FREQUENCY
REGION (2MHz)
30
0.795
0.995
RT = 28.9k
35
VIN (V)
IEN/UVLO (µA)
CHANNELS 1, 2 VFB (V)
CHANNELS 3, 4 VFB (V)
0.800
25 50 75 100 125 150
TEMPERATURE (°C)
Channel 1 Full Frequency
VIN vs Load Current
40
0.805
CHANNELS 1, 2
0
8602 G24
EN/UVLO Current vs Voltage
0.810
1.000
BOTTOM FET
8602 G23
Feedback Voltage vs Temperature
1.005
TOP FET
150
50
8602 G22
1.010
200
BOTTOM FET
BOTTOM FET
100
–50 –25
RDSON (mΩ)
RDSON (mΩ)
RDSON (mΩ)
400
5
0
5
10
15
20
25
30
VEN/UVLO (V)
35
8602 G25
40
45
8602 G26
0
0
0.2
0.4
0.6
0.8 1
IOUT (A)
1.2
1.4
1.6
8602 G27
8602f
8
For more information www.linear.com/LT8602
LT8602
Typical
Performance Characteristics
and PVIN3 = PVIN4 = 3.3V, unless otherwise noted.
45
Channel 2 Full Frequency
VIN vs Load Current
6.0
RT = 28.9k
40
RT = 28.9k
VIN (V)
FULL FREQUENCY
REGION (2MHz)
15
FULL FREQUENCY
REGION (2MHz)
4.5
25
20
VIN
5.0
VOUT = 3.3V
VOUT = 5V
30
VIN (V)
Channel 1 Start-Up and Dropout,
RL = 20Ω
Channel 3, 4 Full Frequency
VIN vs Load Current
5.5
35
VOUT1
2V/DIV
4.0
3.5
VOUT = 1.8V
VOUT = 1.2V
3.0
10
100ms/DIV
2.5
5
0
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
0
0.3
0.7
1
1.3 1.6
IOUT (A)
1.9
2.3
2.0
2.6
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IOUT (A)
2
8602 G29
8602 G28
Channel 1 Start-Up and Dropout,
RL = 3.3Ω
Channel 2 Start-Up and Dropout,
RL = 20Ω
VIN
Channel 2 Start-Up and
Dropout, RL = 2Ω
VIN
VIN
VOUT1
2V/DIV
100ms/DIV
8602 G29
2V/DIV
8602 G30
VOUT2
100ms/DIV
2V/DIV
8602 G32
Full Frequency Waveforms
VOUT2
100ms/DIV
8602 G33
Light Load Waveforms
VOUT
20mV/DIV
VSW1
10V/DIV
VSW2
10V/DIV
VSW
5V/DIV
VSW3
2V/DIV
IL
0.5A/DIV
VSW4
2V/DIV
200ns/DIV
8602 G34
VOUT1 = 5V
VOUT2 = 3.3V
VOUT3 = 1.8V
VOUT4 = 1.2V
5µs/DIV
CHANNEL 1
12VIN TO 5VOUT AT 10mA
VSYNC = 0V
8602 G35
8602f
For more information www.linear.com/LT8602
9
LT8602
Typical
Performance Characteristics
TA = 25°C
Radiated EMI Performance, (CISPR25 Radiated Emission Tests with Class 5 Peak Limit)
Vertical Polarization
Horizontal Polarization
DC1949A Demo Board with EMI Filter Installed 14VIN, 1A at All Outputs, FSW = 2MHz
8602f
10
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LT8602
Pin Functions
BIAS (Pin 10): Power to the internal 3.3V regulator. Connect to an output ≥3.1V. Decouple to ground with a low
ESR capacitor.
BST1, BST2 (Pins 4, 5): Boost Voltage for HV Channels.
The Boost Voltage provides a drive voltage higher than
PVIN to the gate of the NMOS top switch.
CPOR (Pin 31): Power-On Reset Timer. Connect a capacitor from this pin to ground to program the power-on reset
timer. CPOR has a 2μA pull-up current.
EN/UVLO (Pin 22): Enable/Undervoltage Lockout Input.
The LT8602 is in low power shutdown when this pin is
below 0.5V. A precision threshold at 1.2V enables the
switching regulators. This allows the EN/UVLO pin to be
used as an input undervoltage lockout by connecting to
a resistor divider between VIN and GND. Connect to VIN if
the UVLO function is not needed.
FB1, FB2 (Pins 26, 25): Feedback Input Pins for the High
Voltage Converters. The converters regulate the corresponding feedback pin to the lesser of 1V or the voltage
on the associated TRKSS pin.
FB3, FB4 (Pins 27, 24): Feedback Input Pins for the Low
Voltage Converters. The converters regulate the corresponding feedback pin to 800mV.
GND (Pins 2, 8, 9, 13, 16, 35, 38, 41): Ground. These
pins must be soldered to PCB ground. The exposed pad
(pin 41) must also be soldered to PCB ground.
INTVCC (Pin 28): Internal 3.3V Regulator Bypass. Do not
load the INTVCC pin with external circuitry. Decouple to
ground with a low ESR 4.7μF capacitor.
PG1, PG2 (Pins 1, 11): Power Good Indicators for Channels 1 and 2. Open drain logic output pulls down until
the corresponding FB pin rises above 0.92V but remains
below 1.08V.
PG3, PG4 (Pins 40, 12): Power Good Indicators for Channels 3 and 4. Open drain logic output pulls down until the
corresponding FB pin rises above 0.736V but remains
below 0.864V.
POREN (Pin 39): Power On Reset Enable. This is a logic
input that starts the ramp on the POR timing capacitor.
This input has a weak pull-up.
PVIN1, PVIN2 (Pins 37, 14): Input Supply Voltage to HV Channels 1 and 2, respectively. These pins are independent and
can be powered from different sources if necessary. Bypass
each input with a low ESR capacitor to the adjacent GND pin.
PVIN3, PVIN4 (Pins 34, 17): Input Supply Voltage to low
voltage Channels 3 and 4. These pins are typically connected
to one of the high voltage converter outputs and should
be locally bypassed with a low ESR capacitor. PVIN3 and
PVIN4 are independent and do not need to be connected
to the same supply voltage.
RST (Pin 32): Power-On Reset Output. CMOS output with
weak pull-up, this pin is held low until the POR times out.
RT (Pin 29): Frequency Programming Resistor. Connect
a resistor from this pin to ground to set the internal oscillator frequency.
RUN3, RUN4 (Pins 30, 18): Run Inputs for the low voltage converters.
SW1 (Pin 3): Channel 1 Switch Node. This is the output
of the internal power switches for Channel 1.
SW2 (Pins 6, 7): Channel 2 Switch Node. This is the output
of the internal power switches for Channel 2. These pins
must be connected together.
SW3, SW4 (Pins 36, 15): Switch Nodes for low voltage
converters. These are the outputs of the internal power
switches for Channels 3 and 4.
SYNC (Pin 33): Clock Synchronization Input. A digital
input to allow the LT8602 to synchronize its switching
frequency to an external clock. If clock synchronization is
not used, connect this pin to ground to enable low ripple
burst mode or connect high to enable pulse skip operation
of the synchronous converters. Do not allow SYNC to float.
TRKSS1, TRKSS2 (Pins 21, 20): Track/Soft-Start Inputs
for the High Voltage Converters. When this pin is below
1V, the converter regulates the FB pin to the TRKSS voltage instead of the internal reference. The TRKSS pin has
a 2.4μA pull-up current. TRKSS may be left floating
VIN (Pin 23): Input Supply Voltage to Internal Functions.
This pin is independent from any PVIN pin and can be
powered from different sources if necessary. VIN must
be above 3V for the part to operate.
8602f
For more information www.linear.com/LT8602
11
LT8602
Block Diagram
POREN
CPOR
RST
VIN
POWER-ON
RESET
EN/UVLO
INTVCC
RT
INTVCC
3.3V
REGULATOR
SYNC
OSCILLATOR
1V
REFERENCE
0.8V
SS3
ENABLE
SS4 CLK1 CLK2
BIAS
BST1
BST2
ILIM1
PVIN1
–
+
CLK1
CLK2
CURRENT
SENSE
COMPARATOR
LOGIC
SW2
LOGIC
DRIVER
–
+
DRIVER
–
+
+
2.4µA
–
+
REVERSE
CURRENT
COMPARATOR
REVERSE
CURRENT
COMPARATOR
LOOP
COMPENSATION
ILIM1
ILIM2
FB2
–
+
+
LOOP
COMPENSATION
2.4µA
1V
TRKSS1
1V
0.92V
1.08V
PG1
–
+
–
+
ILIM3
PVIN3
–
+
CLK1
0.86V
–
+
REVERSE
CURRENT
COMPARATOR
GND
ERROR
AMPLIFIER
LOOP
COMPENSATION
ILIM4
ILIM3
FB4
–
+
+
LOOP
COMPENSATION
0.8V
0.74V
PVIN4
–
+
DRIVER
REVERSE
CURRENT
COMPARATOR
–
+
+
SS3
PG2
SW4
ERROR
AMPLIFIER
FB3
1.08V
LOGIC
DRIVER
–
+
0.92V
CURRENT
SENSE
COMPARATOR
LOGIC
TRKSS2
ILIM4
CLK2
CURRENT
SENSE
COMPARATOR
SW3
GND
GND
ERROR
AMPLIFIER
ERROR
AMPLIFIER
FB1
PVIN2
–
+
CURRENT
SENSE
COMPARATOR
SW1
GND
ILIM2
SS4
0.8V
–
+
PG3
GND
RUN3
RUN4
PG4
–
+
0.74V
0.86V
8602 BD
8602f
12
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LT8602
Operation
The LT8602 is a quad channel, constant frequency, current
mode, monolithic buck switching regulator with power-on
reset. All channels are synchronized to a single oscillator.
Two of the channels are high voltage (up to 42V input)
while the other two are low voltage (up to 5.5V input) and
are typically powered from the high voltage buck outputs.
Start-Up
When enabled by setting the EN/UVLO voltage above its
threshold, the LT8602 starts charging the INTVCC capacitor
from VIN. If BIAS is higher than 3.1V, BIAS supplies current
to the INTVCC regulator to reduce VIN quiescent current.
High Voltage Buck Regulators
Each high voltage channel is a synchronous buck regulator
that operates from an independent PVIN pin. The internal
top power MOSFET is turned on at the beginning of each
oscillator cycle, and turned off when the current flowing
through the top MOSFET reaches a level determined by the
error amplifier. The error amplifier measures the output
voltage through an external resistor divider tied to the FB
pin to control the peak current in the top switch. The reference of the error amplifier is determined by the lower of
the internal 1V reference and the voltage at its TRKSS pin.
While the top MOSFET is off, the bottom MOSFET is
turned on for the remainder of the oscillator cycle or
until the inductor current starts to reverse. If overload
conditions result in more than 2A (Ch 1) or 3.3A (Ch 2)
flowing through the bottom switch, the next clock cycle
will be delayed until switch current returns to a safe level.
Low Voltage Buck Regulators
Each low voltage channel is a synchronous buck regulator
that operates from an independent PVIN pin. The PVIN pins
have an undervoltage lockout set at 2.35V. Each internal
top power MOSFET is turned on at the beginning of each
oscillator cycle, and turned off when the current flowing
through the top MOSFET reaches a level determined by
the error amplifier. The error amplifier measures the
output voltage through an external resistor divider tied to
the FB pin to control the peak current in the top switch.
The reference of the error amplifier is an internal 800mV
reference. Each LV channel has a RUN pin to allow power
sequencing and an internal soft-start circuit ramps the
output voltage up in 1ms.
While the top MOSFET is off, the bottom MOSFET is turned
on for the remainder of the oscillator cycle or until the
inductor current starts to reverse. If overload conditions
result in more than 2.4A flowing through the bottom switch,
the next clock cycle will be delayed until switch current
returns to a safe level.
Multiphase Switching
The oscillator generates two clock signals 180° out of
phase. Channels 1 and 3 operate on CLK1, while channels 2
and 4 operate on CLK2. Since a buck regulator only draws
input current during the top switch on cycle, multiphase
operation reduces peak input current and doubles the input
current frequency. These effects reduce input current ripple
and reduce the input capacitance required.
Light Load Operation
At light load, the regulators operate in low ripple burst
mode. Low ripple burst mode shuts down most internal
circuitry between switch on cycles to conserve power
while still retaining low ripple at the output.
Undervoltage Lockout
The EN/UVLO pin is used to put the LT8602 in shutdown,
reducing the input current to less than 1μA. The accurate
1.2V threshold of the EN/UVLO pin allows a programmable
VIN undervoltage lockout through an external resistor
divider tied to the EN/UVLO pin. A 50mV (typ) hysteresis
voltage on the EN/UVLO pin prevents switching noise from
inadvertently shutting down the LT8602.
Power Good Comparators
Each channel has a power good comparator that trips
when the feedback pin is above or below its reference
voltage by more than 8%. The PG output pins are open
drain. The PG pin for each channel is pulled low when the
corresponding output is out of regulation. The PG outputs
are not valid until INTVCC rises to 2.7V
8602f
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13
LT8602
Operation
Power-On Reset Timer
The LT8602 includes a power-on reset timer. The poweron reset time is adjustable using an external capacitor on
the CPOR pin. The timer is enabled by the POREN pin.
The RST pin is the output of the POR timer and is an
open-drain output with a weak internal pull-up. The RST
pin is valid when the LT8602 is enabled and INTVCC is
above 2.7V.
Applications Information
Setting the Output Voltages
VOUTx
SWx
The output voltages are set by the resistor dividers on the
outputs as shown in Figure 1. The formula used is:
COUT
LT8602
R1
Cff
OPTIONAL
FBx
R2
V

R1= R2 •  OUTx – 1
 FBREF 
8602 F01
Figure 1. Feedback Resistor Divider
where VOUTx is the output voltage of regulator x and FBREF
is the feedback reference voltage. FBREF is 1V for the high
voltage regulators (1 and 2) and 800mV for the low voltage
channels (3 and 4). Use 1% resistors in the dividers. R2
should be 200k or less to avoid noise problems.
To improve the frequency response, a feedforward capacitor
Cff may be used. Typical values are 10pf to 100pf. Great
care should be taken to route the VFB node away from
noise sources, such as the inductor or a SW line.
Switching Frequency
The LT8602 uses a constant frequency architecture that
can be programmed from 250kHz to 2.2MHz by tying a
resistor from the RT pin to ground. Table 1 shows the
value of RT for common switching frequencies.
Table 1. Switching Frequency vs RT Value
The following equation approximates the values shown
in Table 1:
RT =
61.9
– 1.9
fS – 0.009
where RT is in kΩ and fS is in MHz.
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The advantage of low frequency operation is higher efficiency.
The high switching frequency also decreases the duty
cycle range because of finite minimum on- and off-times
which are independent of the switching frequency. The
top switch in the high voltage channel has a minimum
on-time of 60ns and minimum off-time of of 70ns. The top
switch in the low voltage channel has a minimum on-time
of 70ns and minimum off-time of 70ns. The minimum and
maximum duty cycles are:
SWITCHING FREQUENCY (MHz)
RT (kΩ)
0.25
254
0.35
179
0.5
124
0.75
81.2
DCMIN = fS • tON(MIN)
1.0
60.4
1.25
47.6
DCMAX = 1 – fS • tOFF(MIN)
1.5
39.4
1.75
33.3
2.0
28.9
2.2
26.3
where fS is the switching frequency, tON(MIN) is the minimum switch on-time, and tOFF(MIN) is the minimum switch
off-time. These equations illustrate how duty cycle range
increases when the switching frequency decreases.
8602f
14
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LT8602
Applications Information
The internal oscillator of the LT8602 can be synchronized to
an external 250kHz to 2.2MHz clock signal on the SYNC pin.
VIN Voltage Range
The LT8602’s minimum operating voltage is 3V. To program a higher minimum operating voltage, use a resistor
divider between the VIN pin and the EN/UVLO pin. The EN/
UVLO threshold is 1.2V. The EN/UVLO pin has 50mV of
hysteresis to prevent glitches from falsely disabling the
LT8602.
The UVLO circuit is shown in Figure 3, Reverse Protection
Diodes. The calculation for the lockout voltage is:
R +R
VIN(UVLO) = UV1 UV2 •1.2V
RUV2
Where DCMIN is the minimum duty cycle (refer to Switching
Frequency section) for that channel. If PVIN is above the
calculated maximum voltage, the channel starts to skip
switch on cycles (pulse-skipping). In this case, the channel
switching frequency will no longer be the programmed
frequency. The output will continue to regulate, but the
peak inductor current and output ripple will increase
significantly.
Inductor Selection
Inductor selection involves inductance, saturation current,
series resistance (DCR) and magnetic loss.
A good starting point for the inductance values are:
PVIN Voltage Range
Each switching regulator channel operates from its own
PVIN pin (PVIN1 to PVIN4). The PVIN pin can be connected
to either an independent voltage supply or a high voltage
channel output. The PVIN1 and PVIN2 voltage range is 3.0V
to 42V. The PVIN3 and PVIN4 voltage range is 2.6V to 5.5V.
VOUTx
DCMAX
Once the inductance is selected, the inductor current ripple
and peak current can be calculated:
The maximum PVIN voltage to regulate output voltage at
full frequency is:
PVINx(MAX) =
VOUTx
DCMIN
∆ILx =
Where DCMAX is the maximum duty cycle (refer to Switching Frequency section) for that channel. If PVIN is below
the calculated minimum voltage, the channel starts to skip
switch off cycles. At low input voltages the part will turn on
the top switch for longer than a full switch cycle in order to
extend the effective duty cycle. When the part is extending
the effective duty cycle the switching frequency will drop
to one half (or less) of the programmed frequency.
VOUTx PVINx – VOUTx
•
PVINx
fS
where fS is the switching frequency in MHz, Lx is in µH,
VOUTx is the channel output voltage and K1 = 1.6, K2 =
1.0 and K3 and K4 = 1.3.
The minimum PVIN voltage to regulate output voltage at
full frequency is:
PVINx(MIN) =
Lx = Kx •
VOUTx
Lx • fS

VOUTx 
•  1–

 PVINx(MAX) 
ILx(PEAK) =IOUTx(MAX) +
∆ILx
2
To guarantee sufficient output current, peak inductor current must be lower than the switch current limit (ILIM).
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be <0.1Ω
for channels 1, 3 and 4; <0.06Ω for channel 2), and the
core material should be intended for the chosen switching frequency. Table 2 lists several vendors and suitable
inductor series.
Table 2. Inductor Vendors
VENDOR
SERIES
WEBSITE
TDK
SLF, VLC, VLF
www.tdk.com
Sumida
CDRH, CDR, CDMC
www.sumida.com
Coilcraft
XAL, XFL, MSS
www.coilcraft.com
NIC
NPIM, NPIS
www.niccomp.com
Würth
TPC, SPC, PD, PDF, PD3
www.we-online.com
8602f
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15
LT8602
Applications Information
Of course, such a simple design guide will not always result
in the optimum inductors for the applications. A larger
value inductor provides a slightly higher maximum load
current and will reduce the output voltage ripple. A larger
value inductor can result in higher efficiency if the DCR
and magnetic losses are the same. However, for inductors
of the same dimensions, the larger value inductor has
higher DCR. The trade-off between inductance and DCR
is not always obvious. Use experiments to find optimum
inductors.
capacitor is required to reduce the resulting voltage ripple
at the LT8602 input and to force this switching current
into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency
to do this effectively and it must have an adequate ripple
current rating.
Low inductance may result in discontinuous mode
operation, which is acceptable, but reduces maximum
load current. For details of maximum output current and
discontinuous mode operation, see the Linear Technology Application Note 44. For duty cycles greater than
50%, there is a minimum inductance required to avoid
subharmonic oscillations.
LMINx =
LMINx =
1.05 • ( VOUTx + VBOTx )
, chs 1, 3 and 4
fS
0.70 • ( VOUTx + VBOTx )
, ch 2
fS
where VOUTx is the output voltage; VBOTx is the voltage
across the bottom switch; fS is the switching frequency in
MHz and LMINx is in µH. If the frequency is synchronized
over a range, use the lowest frequency to determine LMINx.
Shorted Output Protection
The LT8602 will tolerate a shorted output. If the bottom
MOSFET current exceeds the valley current limit at the
start of a clock cycle, the top MOSFET is kept off until the
overcurrent situation clears. This prevents the buildup of
inductor current during a shorted output.
Input Capacitor Selection
Bypass each PVIN pin of the LT8602 with a ceramic capacitor of X7R or X5R type.
The worst case ripple current is when VOUT is one half of
PVIN. In this case, the ripple current is:
ICIN(RMS) =
IOUT
2
A reasonable value for the input capacitor is:
CIN =
4.7µF (for Chs 1, 3, 4) or 10µF ( for Ch 2)
fS
where fS is the switching frequency in MHz.
Careful placement of CIN is essential to get the lowest
ripple and EMI. CIN should be placed as close to the PVIN
pin as possible and on the same side of the PC board. The
layer immediately below the component traces should be
an unbroken ground plane. The ground side of CIN should
have at least 2 vias to the ground plane as close to CIN
as possible. This provides a high frequency return path
directly under the PVIN to CIN trace. This minimizes loop
area of the high frequency, high current path from PVIN
to CIN and back to the GND exposed pad. See Figure 8,
Recommended PCB Layout.
A word of caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit back to the supply. If power is applied quickly (for
example by plugging the circuit into a live power source),
this tank can ring, as much as doubling the input voltage.
The solution is to either clamp the input voltage or dampen
the tank circuit by adding a lossy capacitor in parallel with
the ceramic capacitor. For details, see Linear Technology
Application Note 88.
Step-down converters draw current from the input supply in pulses with very fast rise and fall times. The input
8602f
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LT8602
Applications Information
Output Capacitor Selection
The output capacitor performs two functions. First, it
filters the inductor current to generate an output with
low voltage ripple. Second, it stores energy to minimize
overshoot during transient loads. Because the LT8602
operates at a high frequency, minimal output capacitance is
necessary. The control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following equations:
VRIPPLE =
∆IL
, for ceramic
8 • fS •COUT
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR, organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 3 lists
several capacitor vendors.
Table 3. Low ESR Capacitor Vendors
VENDOR
SERIES
TYPE
Taiyo-Yuden
www.t-yuden.com
Ceramic
where VRIPPLE is the peak-to-peak output ripple, fS is the
switching frequency in MHz, ΔIL is the peak-to-peak ripple
current in the inductor, COUT is the output capacitor value
in µF and ESR is the output capacitor series resistance.
TDK
www.tdk.com
Ceramic
Another constraint on the output capacitor is that it must
have greater energy storage than the inductor. When the
load current steps from high to low, the stored energy
in the inductor transfers to the output and the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
Panasonic
www.panasonic.com SP-CAP
Ceramic
Alum. Organic Polymer
AVX
www.avx.com
Ceramic
Tantalum
VRIPPLE = ∆IL • ESR, for aluminum or tantalum.
 I

COUT ≥ 10 •L •  LIM 
 VOUT 
2
where ILIM is the maximum switch current limit.
The low ESR and small size of ceramic capacitors make
them the preferred type for LT8602 applications. Not all
ceramic capacitors are the same, however. Many of the
higher value capacitors use poor dielectrics with high
temperature and voltage coefficients. In particular, Y5V
and Z5U types lose a large fraction of their capacitance
with applied voltage and at temperature extremes. Because
loop stability and transient response depend on the value
of COUT, this loss may be unacceptable. Use X7R or X5R
types.
Kemet
www.kemet.com
Ceramic
T494, T495
Tantalum
T510, T520, T525, T530 Tantalum Organic Polymer
A700
Alum. Organic Polymer
TPS, TES, TCH
BST and SW Pin Considerations
The high voltage channels require a voltage above PVIN
to drive the gates of the top NFET switches. Connect an
external capacitor between the BST and SW pins. An
internal MOS switch connects BST to the internal 3.3V
supply during the switch off cycles. Then BST is boosted
to 3.3V above SW during the switch on cycles. In most
cases, a 0.1μF capacitor will work well.
Soft-Start
The LT8602 has a soft-start pin for each high voltage channel and internal soft-start for each low voltage channel.
The low voltage channel soft-start is set to 1ms.
On the high voltage channels, the feedback pin voltage
is regulated to the lower of the corresponding TRKSS
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17
LT8602
Applications Information
pin and the internal reference of 1V. A capacitor from the
TRKSS pin to ground is charged by an internal 2.4μA current source resulting in an output ramping linearly from
0V to the regulated voltage. The duration of the ramp is:
tSS = CTRKSS •
1V
2.4µA
where tSS is the ramping time in seconds and CTRKSS is
the capacitance on the TRKSS pin in F.
The TRKSS pin is pulled down at start-up until INTVCC
has reached operating voltage. It is also pulled down in
an undervoltage condition, either the internal lockout on
PVIN or the programmable EN/UVLO pin. The resistance
when TRKSS is pulled down is 400Ω. Pulling TRKSS to
ground does not guarantee the channel will stop switching.
The TRKSS pin can also be used to allow the output to
track another regulator, either the other HV channel or an
external regulator. Use a resistor divider from the controlling output to the TRKSS pin. Figure 2 shows the circuit
for channel 2 tracking VOUT1 as well as output waveforms
for coincident and ratiometric tracking.
R2 should be 10k or less to minimize the offset from the
2.4µA pull-up current.
Another easy method to ratiometrically track channels 1
and 2 is to tie both TRKSS1 and TRKSS2 together with a
single capacitor to ground. This will double the soft-start
current.
For applications with a start-up sequence that requires a
PG pin be tied to a TRKSS input, a 10k or less resistor
must be used as an external pull-up. The soft-start time
with this configuration can be approximated by:
tSS = 0.5 • RPULLUP • CTRKSS
A more exact formula, that includes the dependence on
the pull-up voltage, VPULLUP, is given by:
1V 

tSS = –RPULLUP •CTRKSS •loge  1–
 VPULLUP 
Reverse Protection
In battery charging applications or in battery backup
systems, an output will be held high by the battery when
the input to the LT8602 is absent. If the VIN and PVIN
pins are floated and the LT8602 is enabled, the internal
circuitry will pull its quiescent current through the SW
pin of the output that is held high. This is acceptable if
VOUT1
COINCIDENT TRACKING VOUT1 > VOUT2
R1
LT8602
R1= R2 • ( VOUT2 – 1)
RATIOMETRIC TRACKING
TRKSS2
R2
V

R1= R2 •  OUT1 – 1
 1.1

VOUT2
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
TIME
(2a) Coincident Tracking
8602 F02
(2b) Ratiometric Tracking
Figure 2. Tracking Circuit
8602f
18
For more information www.linear.com/LT8602
LT8602
Applications Information
the system can tolerate a small current (<100µA) in this
state. If the LT8602 is disabled, the SW pin current will
drop to essentially zero. However, if the VIN or PVIN pin is
grounded while the output is held high, an external diode
is required at the VIN/PVIN pin to prevent current being
pulled out of the VIN/PVIN pin. An example is shown in
Figure 3. In this case, both OUT1 and OUT3 are held high
by batteries. PVIN1 must be diode protected, as well as
PVIN3 if it is connected to an external supply.
IN
VIN
BST1
PVIN1
RUV1
EN/UVLO
SW1
OUT1
+
–
FB1
four channels go into Burst Mode operation, the oscillator
will also shut off between bursts with a further savings in
power (Figure 5). Because the channels of the LT8602 may
have different loads, channels can have different switching
frequencies when in Burst Mode operation.
VERT
5V/DIV
VSW1
VSW2
VSW3
VSW4
RUV2
LT8602
100ms/DIV
SW3
IN3
OUT3
PVIN3
+
–
FB3
Figure 5. Burst Mode SW Waveforms with
All Channels in Burst Mode
Mode Selection and Synchronization
GND
8602 F03
Figure 3. Reverse Protection Diodes
Burst Mode Operation
To improve efficiency at light loads, the LT8602 automatically switches to Burst Mode operation which minimizes
the switching loss and keeps the output voltage ripple
small. In Burst Mode operation, most of the circuits are
shut down between switch-on bursts to minimize power
loss. If at least one channel remains full frequency, the
oscillator remains on and all bursts are synchronized to
the appropriate phase of the oscillator (Figure 4). If all
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
5V/DIV
VSW4
5V/DIV
1µs/DIV
8602 F05
8602 F04
Figure 4. Burst Mode SW Waveforms with Oscillator Running
To select low ripple Burst Mode operation, tie the SYNC
pin below 0.3V (this can be ground or a logic low output).
To select pulse-skipping operation, tie the SYNC pin above
1.2V. To synchronize the LT8602 oscillator to an external
frequency connect a square wave (with 20% to 80% duty
cycle) to the SYNC pin. The square wave amplitude should
have valleys that are below SYNC VIL and peaks above
SYNC VIH (up to 6V).
The LT8602 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain regulation. The LT8602
may be synchronized over a 250kHz to 2.2MHz range. The
RT resistor should be chosen to set the LT8602 switching
frequency equal to the synchronization input. If a range
of frequencies is used, set RT to the center of the range.
For example, if the synchronization signal will be 400kHz
to 600kHz, the RT should be selected for 500kHz.
For some applications it is desirable for the LT8602 to
operate in pulse-skipping mode, offering two major differences from Burst Mode operation. First is that the clock
stays awake at all times and all switching cycles are aligned
to the clock. Second is that full switching frequency is
reached at lower output load than in Burst Mode operation.
8602f
For more information www.linear.com/LT8602
19
LT8602
Applications Information
These two differences come at the expense of increased
quiescent current. To enable pulse-skipping mode, the
SYNC pin is tied high either to a logic output or to the
INTVCC pin.
Do not leave the SYNC pin floating.
POREN
1V/DIV
CPOR
1V/DIV
Power Good Comparators
Each channel of the LT8602 has a power-good comparator
that monitors the corresponding feedback voltages when
the LT8602 is enabled. The threshold of power-good comparator is 0.92V to 1.08V for the high voltage channels,
and 736mV to 864mV for the low voltage channels. The
PG outputs are open-drain and require an external pull-up
resistance value of 20k or less.
Power-On Reset Timer
The power-on reset timer circuit provides a programmable reset timer. The POREN pin is the enable for the
reset timer. The RST output is an open-drain output with
a weak internal pull-up (100k to ~2.8V). The weak pull-ups
eliminate the need for external pull-ups when the rise time
of these pins is not critical. The open-drain configuration
allows wired-OR connections of the RST pin.
The power-on reset timeout period, tRST, can be programmed by connecting a capacitor, CPOR, between the
CPOR pin and ground. The value of tRST is calculated by:
RSTb
2V/DIV
1ms/DIV
8602 F06
Figure 6. Power-On Reset Timing CPOR = 230pF
Sequencing
The LT8602 provides great flexibility in sequencing the
4 channels and the power-on reset timer. Each channel
has a power good output (PG1 to PG4) and a controlling input (TRKSS1 and 2, RUN3 and 4). The POR has
a control input (POREN) and a reset output (RST). All 5
outputs are open-drain. All 5 inputs are active high and
3 of them (TRKSS1 and 2, POREN) have internal pull-up
currents to reduce external component counts. The softstart function on the TRKSS pins will work when using
sequencing; simply connect the capacitor to the TRKSS
pin, connect an external pull-up resistor of value 10k or
less and use the desired PG output to short the cap. A
sequencing example is shown in Figure 7.
tRST = 35.2 • CPOR
OUT1
Where CPOR is in pF and tRST is in microseconds. When
POREN is enabled, the CPOR pin is ramped up at 2µA until
it reaches 1.2V. The current reverses and ramps down at
20µA. When it reaches 0.2V, it ramps back up at 2µA. This
cycle repeats a total of 64 times, then the RST pin is set
high. For example, using a capacitor value of 8.2nF gives
a 289ms reset timeout period. The accuracy of tRST will
be limited by the accuracy and temperature coefficient
of the capacitor CPOR. Extra parasitic capacitance on the
CPOR pin, such as probe capacitance, can affect tRST.
Figure 6 shows the power on reset timing. CPOR values
above 10nF are not recommended.
10k
LT8602
RST
20k
START
PG1
TRKSS2
PG2
RUN3
RUN4
PG3
20k
OUT1
PG4
POREN
TRKSS1
8602 F07
Figure 7. Sequencing the Outputs and POR
8602f
20
For more information www.linear.com/LT8602
LT8602
Applications Information
In this example, channel 1 starts first, and soft-starts according to the cap on TRKSS1. Once OUT1 has reached
regulation, channel 2 soft-starts. When OUT2 is good,
channels 3 and 4 start up. When OUT3 is in regulation,
then the POR is started. One caution when connecting
RUN pins to TRKSS pins: the TRKSS channel will start
ramping immediately, but the RUN channel will not start
until the voltage reaches the RUN threshold.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 8 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT8602’s PVIN pins, GND pins, and the input
capacitors. The loop formed by the input capacitor should
be as small as possible by placing the capacitor close to
the PVIN pin and the adjacent GND pin. When using a
physically large input capacitor the resulting loop may
VOUT2
L1
COUT1
COUT2
COUT3
CBST2
COUT4
CIN2
VOUT4
VOUT3
CBST1 C
IN1A
1
L3
L4
CIN1B
CIN4
Thermal Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8602. The exposed pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to large copper layers
below with thermal vias; these layers will spread heat
dissipated by the LT8602. Recommended layer use for
a 4 layer board is:
VOUT1
L2
become too large in which case using a small case/value
capacitor placed close to the PVIN and GND pins plus a
larger capacitor further away is preferred. These components, along with the inductor and output capacitor, should
be placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
unbroken ground plane under the application circuit on
the layer closest to the surface layer. The SW and BOOST
nodes should be as small as possible. Finally, keep the FB
and RT nodes small so that the ground traces will shield
them from the SW and BOOST nodes. The exposed pad
on the bottom of the package must be soldered to ground
so that there is a good electrical connection as well as a
good thermal connection so that the PCB can act as a heat
sink. To keep thermal resistance low, extend the ground
plane as much as possible, and add thermal vias under
and near the LT8602 to additional ground planes within
the circuit board and on the bottom side.
CIN3
Layer 1 (Components): use 2oz copper; unbroken high
frequency/high current routing (CIN loop, SW node, BST
node, inductor, COUT), high current DC routing, ground
plane on remainder
Layer 2 (Internal): Unbroken ground plane
Layer 3 (Internal): Signal routing, ground plane on remainder
8602 F08
Figure 8. Recommended PCB Layout
8602f
For more information www.linear.com/LT8602
21
LT8602
Applications Information
Layer 4 (Bottom): Use 2oz copper; high current DC routing
(VIN, VOUT), ground plane on remainder
Placing additional vias can reduce thermal resistance
further. Many small thermal vias are better than a few
large ones. Following these PCB design guidelines can
reduce θJA to 22°C/W.
Power dissipation within the LT8602 can be estimated by
adding the power dissipated in each channel. Calculate
each channel’s power loss from an efficiency measurement and subtract the inductor loss. The die temperature
is calculated by multiplying the total LT8602 power dissipation by the thermal resistance from junction to ambient
and adding the ambient temperature. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. The LT8602 will
stop switching if the internal temperature rises too high.
This thermal protection is above the maximum operating
temperature and is intended as a failsafe only.
Even with the best thermal practices, the LT8602 must be
derated at high ambient temperature. The thermal derating
curves in Figure 9 show the front page application (Ch1:
5VOUT, Ch 2: 3.3VOUT, Ch 3:1.8VOUT, Ch 4:1.2VOUT). The
PCB layout is as described above and the QJA is 22°C/W. The
output currents are decreased uniformly as a percentage
of maximum. Although derating is application dependent,
this set of curves is representative of typical applications
with a range of frequencies and input voltages.
% OF MAX LOAD CURRENT (%)
100
80
60
12VIN, 1MHz
12VIN, 2.2MHz
28VIN, 1MHz
28VIN, 2.2MHz
40
20
0
3.5in x 3.5in 4–LAYER BOARD
2oz Cu TOP AND BOTTOM
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
LIMITED BY MAXIMUM
JUNCTION TEMPERATURE
θJA = 22°C/W
125
8602 F09
Figure 9. Thermal Derating, I-Grade
8602f
22
For more information www.linear.com/LT8602
LT8602
Typical Applications
Details of Front Page Application
VIN
6V TO 42V
VIN
C12
4.7µF
BST1
PVIN1
SW1
LT8602
PVIN2
C11
10µF
EN/UVLO
SW2
TRKSS1
TRKSS2
L2
2.2µH
R3
316k
R4
137k
PVIN3
RUN4
C5
4.7µF
PG1
PVIN4
4.7pF
22pF
THE MAX CURRENT ON OUT2 IS A FUNCTION
OF THE CURRENTS ON OUT3 AND OUT4:
I(OUT2) = 2.5A – 0.6 • I(OUT3) – 0.4 • I(OUT4)
PG4
SW3
POREN
RST
SWITCHING FREQUENCY = 1MHz
R9
60.4k
L3
2.2µH
10pF
FB3
CPOR
SW4
RT
GND
R5
249k
C3
22µF
R6
200k
L4
1.8µH
22pF
FB4
INTVCC
OUT2
C2 3.3V, 0.8A
47µF
C6
4.7µF
PG3
SYNC
OUT1
C1 5V, 1.5A
22µF
R2
113k
C8
0.1µF
FB2
PG2
OUT2
R1
453k
BIAS
RUN3
R10
20k
L1
6.2µH
FB1
BST2
C13
2200pF
C7
0.1µF
R7
100k
C4
47µF
OUT3
1.8V, 1.7A
OUT4
1.2V, 1.8A
R8
200k
C9
4.7µF
8602 TA02a
Start-Up Sequence
VOUT1
5V/DIV
THE VALUES SHOWN ARE FOR 1MHz OPERATION.
FOR 2MHz OPERATION, MAKE THE FOLLOWING CHANGES:
L1 = 3.3µH
L2 = 1.2µH
L3 = 1.2µH
L4 = 1µH
R9 = 28.9k
THE INPUT VOLTAGE RANGE AT 2MHz IS 6V TO 24V.
ABOVE 24V, THE HV CHANNELS WILL REGULATE
BUT WITH HIGH RIPPLE DUE TO MISSED PULSES.
VOUT2
5V/DIV
VOUT3
2V/DIV
VOUT4
2V/DIV
200µs/DIV
8602 TA02b
8602f
For more information www.linear.com/LT8602
23
LT8602
Typical Applications
Automotive Input Steps Down to 5V, 3.3V, 1.8V and 1.2V
VIN
6V TO 42V
VIN
C12
4.7µF
BST1
C7
0.1µF
PVIN1
SW1
L1
4.7µH
LT8602
C11
10µF
R11
2M
UVLO = 6V
PVIN2
FB1
BST2
SW2
TRKSS1
C13
2700pF
TRKSS2
FB2
OUT2
PG1
PVIN4
SW3
SYNC
POREN
uP_START
RST
POR TIME = 7.7ms
CPOR
C10
220pF
R9
47.5k
L3
1.5µH
22pF
FB3
L4
1.2µH
22pF
FB4
GND
R5
249k
R6
200k
SW4
RT
OUT2
C2 3.3V, 0.8A
47µF
THE MAX CURRENT ON OUT2 IS A FUNCTION
OF THE CURRENTS ON OUT3 AND OUT4:
I(OUT2) = 2.5A – 0.6 • I(OUT3) – 0.4 • I(OUT4)
C6
4.7µF
PG4
SYNC INPUT
SWITCHING FREQUENCY = 1.25MHz
C5
4.7µF
PG3
10k
R3
316k
R4
137k
PVIN3
RUN4
PG2
OUT2
22pF
BIAS
RUN3
R10
20k
L2
2.2µH
OUT1
C1 5V, 1.5A
22µF
R2
113k
C8
0.1µF
EN/UVLO
R12
499k
4.7pF
R1
453k
INTVCC
R7
100k
OUT3
C3 1.8V, 1.7A
22µF
OUT4
C4 1.2V, 1.8A
47µF
R8
200k
C9
4.7µF
8602 TA03a
Start-Up Sequence
VOUT1
5V/DIV
VOUT2
5V/DIV
VOUT3
2V/DIV
RST
2V/DIV
1ms/DIV
8602 TA03b
START-UP SEQUENCE:
CH1 AND CH2 SOFT-START
RATIOMETRICALLY;
THEN CH3 AND CH4 TURN ON;
THEN POR TIMER STARTS.
8602f
24
For more information www.linear.com/LT8602
LT8602
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
8602f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LT8602
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
25
LT8602
Typical Application
10V to 42V Input Steps Down to 5V, 2.5V, 1.8V and 8V (Delayed)
VIN
10V TO 42V
VIN
C12
4.7µF
BST1
C7
0.1µF
PVIN1
SW1
L1
4.7µH
LT8602
C11
10µF
R11
2M
UVLO = 9.6V
PVIN2
FB1
BST2
SW2
TRKSS1
C13
2700pF
TRKSS2
FB2
R10
20k
10k
PVIN3
PVIN4
PG2
SW3
SYNC
C14
2.2nF
POREN
10pF
L3
1µH
10pF
R5
243k
FB3
R9
26.1k
CPOR
R6
115k
SW4
L4
1µH
10pF
R7
215k
FB4
RT
VCPOR
1V/DIV
VOUT1
10V/DIV
2ms/DIV
RST
C10
330pF
OUT2
C2 5V, 0.8A
47µF
THE MAX CURRENT ON OUT2 IS A FUNCTION
OF THE CURRENTS ON OUT3 AND OUT4:
I(OUT2) = 2.5A – 0.56 • I(OUT3) – 0.4 • I(OUT4)
C6
4.7µF
PG3
PG4
R3
549k
C5
4.7µF
RUN4
PG1
VOUT3
2V/DIV
VOUT4
2V/DIV
R4
137k
BIAS
RUN3
OUT2
L2
2.2µH
VOUT2
5V/DIV
R2
143k
C8
0.1µF
EN/UVLO
R12
287k
C1
47µF
R1
1000k
10pF
Start-Up Sequence
OUT1
8V, 1.5A
INTVCC
C9
4.7µF
GND
C3
47µF
OUT3
2.5V, 1.7A
8602 TA04b
IN THIS APPLICATION, THE POR IS USED AS A DELAY FOR
THE 8V SUPPLY. THE 8V SUPPLY WILL START RAMPING
UP 12ms AFTER ALL OTHER SUPPLIES HAVE REACHED REGULATION.
START-UP SEQUENCE:
CH2 SOFT-STARTS;
THEN CH3 AND CH4 TURN ON;
THEN POR TIMER STARTS;
AFTER POR TIMES OUT, THEN CH1 SOFT-STARTS.
OUT4
C4 1.8V, 1.8A
47µF
R8
174k
8602 TA04a
SWITCHING FREQUENCY = 2.2MHz
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT3507/
LT3507A
36V, 2.7A + 1.8A + 1.8A + LDO Controller, 2.5MHz, High Efficiency, Triple VIN = 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD < 1µA,
5mm × 7mm QFN
Output Step-Down DC/DC Converter
LT8640
42V, 6A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down
DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA,
3mm × 4mm QFN
LT8616
42V Dual (2.5A + 1.5A), 95% Efficiency 3MHz Synchronous MicroPower
Step-Down DC/DC Converter with IQ = 6.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.8V, IQ = 6.5µA, ISD < 1µA,
TSSOP-28E Package
LT8614
42V, 4A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down
DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA,
3mm × 4mm QFN
LT8612
42V, 6A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down
DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA,
3mm × 6mm QFN
LT8610
42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA,
MSOP-16E
DC/DC Converter with IQ = 2.5µA
LT8611
42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down VIN = 3.4V to 42V, VOUT(MIN) = 0.985V , IQ = 2.5µA, ISD < 1µA,
DC/DC Converter with IQ = 2.5µA and Input/Output Current Limit/Monitor 3mm × 5mm QFN-24
LT8610A/
LT8610AB
42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA,
MSOP-16E
DC/DC Converter with IQ = 2.5µA
8602f
26 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT8602
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT8602
LT 0715 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015