LTC3649 60V, 4A Synchronous Step-Down Regulator with Rail-to-Rail Programmable Output DESCRIPTION FEATURES Wide VIN Range: 3.1V to 60V nn Wide V OUT Range: 0V to (VIN – 0.5V) nn Single Resistor V OUT Programming nn Integrated 110mΩ Top N-Channel/50mΩ Bottom N-Channel MOSFETs nn 95% Efficiency with 12V and 5V IN OUT nn Regulated I : 440µA, Shutdown I : 18µA Q Q nn Accurate Current Monitoring (±4%) without Sense Resistor nn Accurate Resistor Programmable Frequency (300kHz to 3MHz) with ±50% Frequency Sync Range nn Accurate Programmable Output Current nn Input Voltage Regulation for MPPT Applications nn ±0.8% Output Voltage Accuracy nn Peak Current Mode Operation nn Programmable Wire Drop Compensation nn Burst Mode® Operation, Forced Continuous Mode nn Internal Compensation and Programmable Soft-Start nn Overtemperature Protection nn Available in Thermally Enhanced 28-Lead (4mm × 5mm) QFN and TSSOP Packages The LTC®3649 is a high efficiency 60V, 4A synchronous monolithic step-down regulator. The regulator features a single resistor programmable output voltage, internal compensation and high efficiencies over a wide VOUT range. nn The step-down regulator operates from an input voltage range of 3.1V to 60V and provides an adjustable rail-to-rail output range from (VIN – 0.5V) to ground while delivering up to 4A of output current. The switching frequency is also adjusted with an external resistor. A user-selectable mode input is provided to allow the user to trade off ripple noise for efficiency at light loads; Burst Mode operation provides the highest efficiency at light loads, while forced continuous mode provides low output ripple. The MODE/ SYNC pin can also be used to allow the user to synchronize the switching frequency to an external clock. The LTC3649 operates with a peak current mode architecture that allows for fast transient response with inherent cycle-to-cycle current limit protection. It also features programmable output current limit, current monitoring and input voltage regulation. L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258. APPLICATIONS nn nn Industrial Applications Automotive Applications TYPICAL APPLICATION Efficiency with VOUT = 5V 24V to 5VOUT Burst Mode Operation 100 0.1µF 98 VIN = 12V VIN = 24V 96 VIN BOOST SW RUN VOUT 22µF LTC3649 ITH VINREG INTVCC 2.2µF fSW = 500kHz EXTVCC MODE/SYNC SGND PGND RT ISET 100k 47µF ×2 VOUT 5V 4A 10nF EFFICIENCY (%) 6.8µH VIN 5.5V TO 60V 10k 92 90 88 86 84 IMON 200k 94 82 80 10nF 3649 TA01a 0 0.5 1 1.5 2 2.5 IOUT (A) 3 3.5 4 3649 TA01b 3649fa For more information www.linear.com/LTC3649 1 LTC3649 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) VIN Voltage (Note 3)................................... 64V to –0.3V ISET, OUT Voltage...................................... 64V to –0.3V RUN Voltage............................................... 64V to –0.3V MODE/SYNC Voltage ................................... 6V to –0.3V PGDFB, RT............................................ INTVCC +0.3V to –0.3V EXTVCC Voltage.......................................... 28V to –0.3V IMON, PGOOD Voltage.................................. 4V to –0.3V VINREG, ITH Voltage...................................... 4V to –0.3V Operating Junction Temperature Range (Notes 5, 7)............. –40°C to 125°C Storage Temperature Range................... –65°C to 125°C PIN CONFIGURATION TOP VIEW PGND 26 SW SW 28 27 26 25 24 23 SW 27 SW 3 PGND 28 SW 2 PGND 1 PGND PGND PGND SW TOP VIEW PGND 1 22 SW PGND 4 25 SW PGND 2 21 SW PGND 5 24 SW VIN 3 20 SW VIN 6 23 SW VIN 4 19 SW VIN 7 18 BOOST RUN 8 SGND 6 17 INTVCC SGND 9 20 INTVCC MODE/SYNC 7 16 EXTVCC MODE/SYNC 10 19 EXTVCC 29 SGND RUN 5 PGOOD 8 15 ITH TJMAX = 125°C, θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION 21 BOOST 18 ITH PGDFB 12 17 ISET IMON 13 16 VOUT VINREG 14 UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 22 SW PGOOD 11 ISET VOUT RT VINREG IMON PGDFB 9 10 11 12 13 14 29 SGND 15 RT FE PACKAGE 28-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 30°C/W, θJC = 5°C to 10°C/W EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC3649#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3649EUFD#PBF LTC3649EUFD#TRPBF 3649 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3649IUFD#PBF LTC3649IUFD#TRPBF 3649 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC3649EFE#PBF LTC3649EFE#TRPBF LTC3649 28-Lead Plastic TSSOP –40°C to 125°C LTC3649IFE#PBF LTC3649IFE#TRPBF LTC3649 28-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 3649fa For more information www.linear.com/LTC3649 LTC3649 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C. (Note 5) VIN = 24V, VEXTVCC = 0V unless otherwise noted. (Notes 5, 7) SYMBOL VIN VOUT IVIN PARAMETER Input Supply Operating Voltage Range Output Operating Voltage Range Input Quiescent Current IISET Reference Current CONDITIONS MIN 3.1 0.05 (Note 4) Shutdown Mode; VRUN = 0V Burst Mode Operation FC Mode (Note 6) VISET = 3.3V l ΔVOUT(LOAD+LINE) VEA(OFFSET) gm (EA) ILSW RSW-GND RDS(ON) DMAX tON(MIN) VRUN IRUN VMODE/SYNC IMODE/SYNC ILIM Output Voltage Load + Line Regulation Error Amp Input Offset Error Amplifier Transconductance Topside NMOS Switch Leakage SW Resistance to GND Topside NMOS On-Resistance Bottom Side NMOS On-Resistance Maximum Duty Cycle Minimum On-Time RUN Input Rising RUN Hysteresis RUN Input Current Burst Mode Operation FC Mode MODE/SYNC Input Current Peak Current Limit l VISET = 3.3V VITH = 0.7V, VOUT = 3.3V –5 400 0.5 VISET = VIN (Note 4) l VINTVCC Undervoltage Lockout VINTVCC Undervoltage Lockout Hysteresis VIN Overvoltage Lockout Rising VIN Overvoltage Lockout Hysteresis Oscillator Frequency SYNC Capture Range VINTVCC LDO Output Voltage VEXTVCC EXTVCC Switchover Voltage 1.08 VRUN = 12V VMODE/SYNC = 0V l VUVLO VUVLO(HYS) VOVLO VOVLO(HYS) fOSC fSYNC VINTVCC 49.6 49.4 VIN Rising l 1.2 –8 5.7 5.4 2.4 64 RT = 100kΩ % of Programmed Frequency l VIN > 5.0V, VEXTVCC > 3.2V l RVOUT IPGDFB OVPGDFB UVPGDFB ∆VPGDFB RPGOOD IPGOOD(LEAK) tPGOOD VOUT Resistance to GND PGDFB Leakage Current Output Overvoltage PGOOD Upper Threshold Output Undervoltage PGOOD Lower Threshold PGOOD Hysteresis PGOOD Pull-Down Resistance PGOOD Leakage Current PGOOD Delay VOUT = 5V VPGDFB = 0.6V PGFB Rising PGFB Falling PGFB Returning AIMON IOUT/IIMON IIMON IMON Pin Current VIMON VVINREG IVINREG Regulated IMON Voltage Under Output Current Regulation Input Voltage Regulation Voltage VINREG Leakage Current VVINREG = 3.3V 0.92 50 3.25 2.85 3.1 3.25 80 0.63 0.54 VPGOOD = 3.3V PGOOD Low to High PGOOD High to Low Ratio of Output Current to IIMON l Current IOUT = 4A l l l TYP 18 440 1.4 50 50 0.1 550 0.1 1 110 50 95 60 1.2 120 0 –5 6 6 2.65 200 68 2 1.00 3.45 3.0 3.15 100 0 0.645 0.555 10 550 MAX 60 VIN 30 600 2.5 50.4 50.6 0.5 5 700 1 1.5 1.32 10 0.4 6.3 6.6 2.9 4 1.08 150 3.65 3.15 3.2 120 100 0.66 0.57 100 38.5 36 96 90 1.94 1.85 16 64 40 40 100 100 2.0 2.0 0 41.5 44 104 110 2.06 2.15 0.1 UNITS V V µA µA mA µA µA % mV µS µA MΩ mΩ mΩ % ns V mV nA V V µA A A V mV V V MHz % V V V V kΩ nA V V mV Ω nA Switch Cycles Switch Cycles k k µA µA V V µA 3649fa For more information www.linear.com/LTC3649 3 LTC3649 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are referred to VSGND/VPGND. Note 3: Transient absolute maximum voltages should not be applied for more than 4% of the switching duty cycle. Note 4: VOUT can be programmed to VIN if the ISET pin is driven to that voltage. If a resistor is used to program VISET, the current into the ISET pin will decrease as VISET approaches VIN. Refer to the ISET current vs VISET graph as an example and reference. Furthermore, during high IOUT and high duty cycle operation, VOUT may be limited by the voltage drop across the top switch. Refer to the High Duty Cycle/Dropout Operation section for more details. Note 5: The LTC3649 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3649E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3649I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 6: The quiescent current in FC mode does not include switching loss of the power FETs. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS Load Regulation ISET Current vs Temperature 100 99 51 50.3 50 50.1 49 49.9 ISET Current vs VISET 48 49.7 47 49.5 –55 –35 –15 46 FC MODE BM VIN = 24V VOUT = 5V 0 50.5 ISET (µA) 101 ISET (µA) NORMALIZED VOUT (%) 102 98 TA = 25°C, unless otherwise noted. 1 2 IOUT (A) 4 3 5 25 45 65 85 105 125 TEMPERATURE (°C) VIN = 24V 0 4 8 12 VISET 16 20 3649 G02 3649 G01 ISET Voltage Line Regulation 3649 G03 Quiescent Current vs Temperature 5.01 24 Shutdown Current vs VIN 20 500 400 16 4.99 300 12 4.97 4.96 4.95 10 20 30 VIN (V) 40 50 60 3649 G04 4 200 8 100 4 SHUTDOWN RISET = 100kΩ 0 IQ (µA) 5.00 IQ (µA) VISET (V) SLEEP 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3649 G05 0 0 10 20 30 VIN (V) 40 50 60 3649 G06 3649fa For more information www.linear.com/LTC3649 LTC3649 TYPICAL PERFORMANCE CHARACTERISTICS 200 RDS(ON) vs Temperature Transient Response, CCM 160 RDSON (mΩ) MTOP 120 80 Transient Response, Burst Mode VOUT 100mV/DIV AC-COUPLED VOUT 100mV/DIV AC-COUPLED IL 2A/DIV IL 2A/DIV MBOT 40 0 –55 –35 –15 TA = 25°C, unless otherwise noted. 20µs/DIV VIN = 24V, VOUT = 5V IOUT = 0A TO 4A, L = 2.2µH, fSW = 1MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF FC MODE, COUT = 2× 47µF 5 25 45 65 85 105 125 TEMPERATURE (°C) 3649 G08 3649 G09 20µs/DIV VIN = 24V, VOUT = 5V IOUT = 0.2A TO 4A, L = 2.2µH, fSW = 1MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF BURST MODE, COUT = 2× 47µF 3649 G07 Switching Frequency/Period vs RT Switching Frequency vs Temperature 3.0 3000 2500 2.0 PERIOD 2000 1.5 1500 1.0 1000 0.5 0 50 100 150 200 250 RT RESISTOR (kΩ) 300 1000 VOUT 2V/DIV 995 VIN 50V/DIV 990 500 0 IL 1A/DIV 1005 PERIOD (ns) FREQUENCY (MHz) FREQUENCY FREQUENCY (kHz) 2.5 Output Regulation with VIN Slew 1010 3500 985 –55 –35 –15 0 350 10ms/DIV VIN = 12V TO 60V, VOUT = 5V IOUT = 0A, L = 2.2µH, fSW = 2.25MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF FC MODE, COUT = 2× 47µF 5 25 45 65 85 105 125 TEMPERATURE (°C) 3649 G12 3649 G11 3649 G10 Continuous Conduction Mode Operation Burst Mode Operation Run Rising Threshold vs Temperature 1.210 IL 1A/DIV SW 10V/DIV RUN RISING THRESHOLD (V) IL 1A/DIV SW 10V/DIV 2µs/DIV VIN = 24V, VOUT = 5V IOUT = 100mA, L = 2.2µH, fSW = 1MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF BURST MODE, COUT = 2× 47µF 3649 G13 500ns/DIV VIN = 24V, VOUT = 5V IOUT = 0A, L = 2.2µH, fSW = 1MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF FC MODE, COUT = 2× 47µF 3649 G14 1.205 1.200 1.195 1.190 1.185 1.180 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3649 G15 3649fa For more information www.linear.com/LTC3649 5 LTC3649 TYPICAL PERFORMANCE CHARACTERISTICS VIMON vs Load (Temperature) Start-up Waveform 1.2 IL 2A/DIV 0.8 VOUT 2V/DIV 0.5 –45°C 25°C 130°C % ERROR NORMALIZED TO 1MHz 1.0 VIMON (V) VRUN 2V/DIV TA = 25°C, unless otherwise noted. 0.6 0.4 VPGOOD 2V/DIV 1ms/DIV VIN = 24V, RISET = 100kΩ RLOAD = 120Ω, L = 2.2µH, fSW = 1MHz RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF BURST MODE, COUT = 2× 47µF VIN = 24V VOUT = 5V fSW = 1MHz RIMON = 10kΩ 0.2 3649 G16 0 0 0.5 1 1.5 2 2.5 IOUT (A) 3 3.5 4 VIMON Error vs Frequency VIN = 24V VOUT = 5V 0 –0.5 –1.0 –1.5 IOUT = 4A –2.0 300 800 1300 1800 2300 FREQUENCY (kHz) 3649 G17 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs Load Current at 5VOUT 80 75 70 fSW = 500kHz L = 6.8µH 65 VIN = 12V VIN = 24V VIN = 48V VIN = 60V 60 55 50 0 0.5 1 1.5 2 2.5 LOAD (A) 3 3.5 3649 G18 Efficiency vs Load Current at 3.3VOUT 80 75 70 fSW = 500kHz L = 4.7µH 65 VIN = 12V VIN = 24V VIN = 48V VIN = 60V 60 55 4 50 0 0.5 1 1.5 2 2.5 LOAD (A) 3 3649 G19 6 3.5 4 3649 G20 Output Capacitor Charging with Fixed Average Current Limit Load Step with Cable Drop Compensation VRUN 2V/DIV VIMON 1V/DIV IL 2A/DIV VOUT 500mV/DIV VOUT 2V/DIV IL 2A/DIV 3649 G21 20ms/DIV VIN = 24V, RISET = 100kΩ RLOAD = 10Ω, L = 2.2µH RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF, RIMON = 40kΩ, CIMON = 0.47nF, COUT = 2× 47µF + 36mF 2800 50ms/DIV CABLE DROP RESISTANCE OF 200mΩ 3649 G22 3649fa For more information www.linear.com/LTC3649 LTC3649 PIN FUNCTIONS (QFN/TSSOP) PGND (Pins 1, 2, 26-28/Pins 1-5): Ground Pins for Power Switch. VOUT (Pin 13/Pin 16): Output Voltage Error Amplifier Input Pin. Connect to the output of the LTC3649 voltage regulator. VIN (Pin 3, 4/Pins 6, 7): Input Supply Pin of the StepDown Regulator. ISET (Pin 14/Pin 17): Accurate 50µA Bias Current and Positive Input to the Error Amplifier. Connect an external resistor from this pin to SGND to program the output voltage. Connecting an external capacitor from ISET to ground will soft start the output voltage by reducing current inrush during start-up. RUN (Pin 5/Pin 8): Logic Controlled RUN Input. Do not leave this pin floating. Place a resistor divider from VIN to GND for an accurate VIN undervoltage threshold. SGND (Pins 6, 29/Pins 9, 29): Signal Ground Pin of the Step-Down Regulator. The exposed pad must be soldered to PCB ground for electrical connection and rated thermal performance. MODE/SYNC (Pin 7/Pin 10): Mode Select and Oscillator Synchronization Input of the Step-Down Regulator. Leave MODE/SYNC floating for forced continuous mode operation or tie MODE/SYNC to GND for Burst Mode operation. Furthermore, connecting MODE/SYNC to an external clock will synchronize the internal oscillator to the external clock signal and put the part in forced continuous mode. PGOOD (Pin 8/Pin 11): VOUT Within Regulation Indicator. PGOOD is pulled to GND when VPGFB is more than 0.645V or less than 0.555V. PGDFB (Pin 9/Pin 12): Power Good Feedback. Place a resistor divider from VOUT to GND to detect power good level. IMON (Pin 10/Pin 13): Output Current Monitoring Pin. The current coming out of this pin is equal to 1/40,000 of the average output current. ITH (Pin 15/Pin 18): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage. Tying this pin to INTVCC activates internal compensation. EXTVCC (Pin 16/ Pin 19): External Power Input to the Internal Regulator. The internal regulator will draw current from EXTVCC instead of VIN when EXTVCC is tied to a voltage higher than 3.2V and VIN is above 5V. For output voltages at or above 3.3V and less than 28V, this pin can be tied to VOUT. If this pin is tied to a supply other than VOUT, locally bypass with at least a 1µF to GND. INTVCC (Pin 17/Pin 20): Low Dropout Regulator. Locally bypass with at least 2.2µF to GND. BOOST (Pin 18/Pin 21): Boosted Floating Driver Supply for Internal Top Power MOSFET. Place a 0.1µF bootstrap capacitor between BOOST and SW. SW (Pins 19-25/Pins 22-28): Switch Node Connection to the Inductor of the Step-Down Regulator. VINREG (Pin 11/Pin 14): Input Voltage Regulation Sense Input. Place a resistor divider from VIN to GND to program the level of input voltage regulation. RT (Pin 12/Pin 15): Oscillator Frequency Programming Pin. Connect an external resistor between 333.3k to 33.3k from RT to GND to program the frequency from 300kHz to 3MHz respectively. Since the synchronization range is limited to ±50% of the set frequency, be sure that either the external clock is within this range or RT is set to accommodate the external clock for proper frequency lock. 3649fa For more information www.linear.com/LTC3649 7 LTC3649 FUNCTIONAL DIAGRAM BOOST VIN INTVCC EXTVCC 1/50k VIN – PEAK CURRENT COMPARATOR REVERSE COMPARATOR 50µA ISET + – VOUT + + LDO 0A – + 1/40k IMON ITH SW VINREG 2V – + + – MODE/SYNC RT 2V BUCK LOGIC AND GATE DRIVE INTVCC PGDFB PGOOD LOGIC PGOOD CLK OSC RUN SGND PGND 3649 FD OPERATION The LTC3649 is a current mode monolithic step-down regulator. The accurate 50µA bias current on the ISET pin allows the user to program the output voltage in a unitygain buffer fashion with just one external resistor from the ISET pin to GND (RSET). The output voltage is set such that: VOUT = 50µA • RSET The LTC3649 operates through a wide VIN range, and its frequency can be programmed to a wide range with the RT resistor. To suit a variety of applications, the MODE/SYNC pin allows the user to trade off output ripple for efficiency. 8 Main Control Loop In normal operation, the internal top power MOSFET is turned on at the beginning of a clock pulse. The inductor current is allowed to ramp up to a peak level. Once that level is reached, the top power switch is turned off and the bottom switch is turned on until the next clock cycle. The peak inductor current is determined by sensing the voltage drop across the SW and VIN nodes of the top power MOSFET. The voltage on the ITH pin sets the comparator threshold corresponding to inductor peak current. The error amplifier, EA, adjusts this ITH voltage by comparing the VOUT voltage with the voltage on ISET. If the load current increases, it causes a drop in VOUT relative to VISET. This causes the ITH voltage to rise until the average inductor current matches that of the load current. 3649fa For more information www.linear.com/LTC3649 LTC3649 OPERATION Low Current Operation Burst Mode operation can be selected by connecting the MODE/SYNC pin to GND. In this mode, the LTC3649 will automatically transition from continuous mode operation to Burst Mode operation when the load current is low. A reverse current comparator looks at the voltage across SW to GND and turns off the bottom power MOSFET when that voltage difference approaches zero. This prevents the inductor current from going negative. An internal burst clamp is set to be approximately 1A, which means that in Burst Mode operation, the peak inductor current will never go below 1A regardless of what the ITH voltage demands the peak current to be. As a result, when the load is low enough, VOUT will rise relative to VISET because the average programmed inductor current is above the load current, thus driving VITH low. Once the ITH voltage is driven below an internal threshold (~400mV), the switching regulator will enter its sleep mode and wait for VOUT to drop and VITH to rise above the threshold before it starts to switch again. During sleep mode, the quiescent current of the part is reduced to less than 400µA to conserve input power. The LTC3649 is designed to operate with single burst pulse behavior to minimize output voltage ripple while keeping the efficiency high at light loads. Lastly, if at any point the top power MOSFET is on for roughly 8 consecutive clock cycles, the part will turn on the bottom power MOSFET for a brief duration such that the BOOST capacitor can be replenished. set the output voltage, the 50µA of current out of the ISET pin is only guaranteed to be accurate when VISET is more than 500mV below VIN. As the input voltage drops below that 500mV threshold, the ISET current will decrease, thus limiting the programmed voltage. Typically, VISET will never get within 300mV of VIN. Since VISET programs VOUT, this limitation essentially enforces a maximum duty cycle for the switcher. This limitation can be overcome if an accurate external supply is used to drive the ISET pin directly. The second limitation against full dropout operation is the requirement for the BOOST to SW capacitor to refresh. When the top power MOSFET is on for multiple clock cycles during dropout operation, the BOOST to SW capacitor slowly gets depleted by the internal circuitry of the chip. When the bottom switch does not turn on for at least 80ns for 8 periods, it is forced to turn on in order to guarantee sufficient voltage on the bootstrap capacitor. During a refresh, the bottom switch will only turn on for roughly 30% of the period to limit inductor ripple, thus limiting output voltage ripple. Output Current Monitoring and Regulation The LTC3649 has the ability to accurately sense the average inductor current without the use of an external sense resistor. The IMON pin output current is 1/40000th scale of the inductor current. Placing a resistor from IMON to GND allows the voltage on that node to be equal to: VIMON = RIMON •IL 40000 Forced Continuous Mode Operation Floating the MODE/SYNC pin defaults the LTC3649 into forced continuous mode operation. In this mode, the part switches continuously regardless of load current, and the inductor peak current is allowed to decrease to approximately –1A to allow for negative average current. Since the IMON current mirrors the inductor current, it is necessary to place a capacitor from IMON to GND to filter the voltage on the node. The choice of this capacitor is discussed below. High Duty Cycle/Dropout Operation As the input voltage decreases towards the desired output voltage, the duty cycle will increase towards 100%. However, given the architecture, there are two restrictions that prevent the LTC3649 from operating in full dropout mode. The first restriction is due to how the ISET voltage is programmed. If a resistor is placed between ISET and GND to In addition to simply sensing the inductor current, the LTC3649 can also be programmed to regulate the average output current limit. The regulator will limit the peak inductor current if it senses that the voltage on IMON has exceeded 2V. As a result, the programmed average inductor current depends on the size of RIMON such that: ILAVG = 2V • 40000 RIMON 3649fa For more information www.linear.com/LTC3649 9 LTC3649 OPERATION If current monitoring is needed but current limiting is not, simply pick an RIMON resistor small enough such that VIMON will never approach 2V. A 10k resistor along with a 10nF capacitor is typically a good RC pair to use in this case. If current limiting is useful for the application, it is important to carefully pick the value of the capacitor from IMON to GND, CIMON. If CIMON is picked to be too large, then the switching regulator will be slow to react to a large output transients, and the average inductor current will rise above the programmed level until the loop can react. If CIMON is picked to be too small, then the loop can become unstable. Typically, an RC time constant that is at least 10 times slower than the switching frequency is a good place to start. 10 1.59 CIMON • RIMON ≥ = 2π • fSW fSW Cable Drop Compensation In certain applications, the point of load will be separated from the switching regulator with a significant amount of wire resistance. Thus, the voltage at the point of load, VPOL, will be reduced from VOUT near the regulator by the resistance of the trace/wire multiplied by the current. In those applications, it is useful to adjust for the VOUT regulation point depending on the average output current to maintain an accurate VPOL. The IMON feature of the LTC3649 along with its single resistor output voltage programmability allows this feature to be implemented with the following configuration shown in Figure 1. LTC3649 ISET SW VOUT IMON RCABLE COUT VPOL(DESIRED) = VOUT – IOUT • RCABLE LOAD RSET1 CSET1 RSET2 CSET2 3649 F01 Figure 1. Cable Drop Compensation Application 10 The general idea behind this setup is that once the inductor current rises, the current out of the IMON pin will rise proportionally. As a result, the ISET voltage will increase, thus increasing the regulated output voltage. This rise of VOUT offsets the voltage drop across the cable, RCABLE, thus keeping VPOL constant. RSET2 should be sized to account for the amount of cable resistance: RSET2 = 40000 • RCABLE Furthermore, in order to regulate VPOL at the desired voltage: (RSET1 + RSET2) • 50µA = VPOL(DESIRED) CSET1 is still required if soft-start is desired for the application, and CSET2 is required to filter out the AC ripple noise of the inductor current. Once again, typically CSET2 and RSET2 should be sized to have a RC time constant 10 times slower than the switching frequency. Input Voltage Regulation In certain applications, the input supply to the power regulator can exhibit fairly high output impedance. As a result, when the regulator is running at heavy loads, VIN might droop more than desired. The input voltage regulation loop allows the application to be programmed to decrease the peak inductor current level, and consequently the input current draw, when it senses that the input voltage has dropped below a programmed threshold. This threshold is programmed by connecting a resistor divider from VIN to GND with its intermediate node fed back to VINREG. With this setup, if VVINREG ever falls below 2V, the regulator will decrease the output current level in order to maintain a 2V level at the pin. If this feature is not required, tie the VINREG pin to INTVCC to prevent this control loop from interfering with normal operation. Another useful application for the input voltage regulation loop is for momentary hold up supplies. Suppose an input supply is suddenly removed from the application, VIN will immediately start to drop until it reaches the programmed input voltage regulation point. When this happens and CCM operation is selected, the regulator will actually take charge from the output capacitor and boost charge back to 3649fa For more information www.linear.com/LTC3649 LTC3649 OPERATION the input to hold the input voltage at the regulated point. The regulator will continue to perform this operation until the output capacitor has dissipated so much energy that it can no longer hold up the input voltage. This momentary input voltage holdup proves to be a handy tool for certain applications. INTVCC Regulator The LTC3649 has two onboard internal low dropout (LDO) regulators that power the drivers and internal bias circuitry. Regardless of which one is in operation, the INTVCC must be bypassed to GND with a minimum of 2.2µF ceramic capacitor. Good bypassing is necessary to supply the high transient current required by the power MOSFET gate drivers. The first LDO is powered from VIN, and the INTVCC voltage is regulated to 3.3V. The power dissipated across this LDO would thus equal to (VIN – 3.3) • IINTVCC. For a typical 1MHz application running in CCM, the current drawn from INTVCC by the chip is roughly 20mA. Thus, if the input voltage is high, the power loss and heat rise due to this LDO is significant. To combat this issue, a separate LDO exists that is powered from EXTVCC. As long as the input voltage is above 5V and the EXTVCC voltage is above 3.2V, this LDO will take over and regulate the INTVCC voltage to 3.1V. In applications where the output voltage is programmed to 3.3V or above, it is recommended that the VOUT (<28V) pin be directly tied to the EXTVCC pin. Otherwise, if a separate lower voltage rail exists on board that can supply INTVCC current, then attaching that supply to EXTVCC will also suffice provided that a 1µF ceramic bypass capacitor is placed from the EXTVCC pin to GND physically close to the chip. Both examples should significantly reduce the power loss through the LDO. VIN Undervoltage Programming LTC3649 offers an accurate RUN threshold to start the regulator. As a result, a resistor divider from IN to GND can be placed with the intermediate node fed back to RUN to set an accurate VIN undervoltage threshold. As the input voltage rises, the RUN voltage will increase above the VRUN rising threshold (1.2V), and the regulator will turn on. Similarly, once on, if the input voltage decreases below the VRUN falling threshold (1.1V), the regulator will turn off. VIN Overvoltage Protection In order to protect the internal power MOSFET devices against transient voltage spikes, the LTC3649 constantly monitors the VIN pin for an overvoltage condition. When VIN rises above 70V, the regulator suspends operation by shutting off both power MOSFETs and discharges the ISET pin voltage to ground. Once VIN drops below the VOVLO threshold, the regulator resumes normal switching operation. Programming Switching Frequency Connecting a resistor from the RT pin to GND programs the switching frequency from 300kHz to 3MHz according to the following formula: f (kHz) = 105 RT (kΩ) Do not float the RT pin. The internal phase-locked loop has a synchronization range of ±50% around its programmed frequency. Therefore, during external clock synchronization, the proper RT value should be selected such that the external clock frequency is within this 50% range of the RT programmed frequency. Output Voltage Tracking and Soft-Start The LTC3649 allows the user to program its output voltage ramp rate by means of the ISET pin. Since VOUT servos its voltage to that of VISET, placing an external capacitor CSET from the ISET pin to GND will program the ramp-up rate of the ISET pin and thus the VOUT voltage. 1 t RSET •CSET VOUT (t)=IISET •RSET 1− e From 0% to 90% VOUT: tSS ≅ –RSET • CSET • In(1 – 0.9) tSS ≅ 2.3 • RSET • CSET 3649fa For more information www.linear.com/LTC3649 11 LTC3649 OPERATION The soft-start time tSS (from 0% to 90% of VOUT) is 2.3 times the time constant (RSET • CSET). The ISET pin can also be driven by an external supply capable of sinking 50µA. When starting up into a pre-biased VOUT, the LTC3649 will stay in Burst Mode operation and keep the power switches off until the voltage on ISET has ramped up to be equal to VOUT, at which point the switcher will begin switching and VOUT will ramp up with ISET. Output Power Good When the LTC3649’s output voltage is within the 7.5% window of the regulation point, which is divided down as a VPGDFB voltage in the range of 0.555V to 0.645V, the output voltage is in regulation and the PGOOD pin is pulled high with an external resistor connected to INTVCC or another voltage rail. Otherwise, an internal open-drain pull-down device will pull the PGOOD pin low. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTC3649’s PGOOD falling edge includes a blanking delay of approximately 64 clock cycles. Internal/External ITH Compensation For ease of use, the user can simplify the loop compensation by tying the ITH pin to INTVCC to enable internal compensation. Because the internal compensation is required to provide a stable output voltage for a wide range of switching frequencies, it is designed to have a loop response that is typically much slower than optimal. 12 This thus becomes a trade-off between simplicity and OPTI‑LOOP® optimization, where ITH components are external and are selected to optimize the loop transient response with minimum output capacitance. Minimum On-Time Considerations Due to the architecture of the LTC3649, a minimum on-time restriction is imposed such that the top power MOSFET can have enough time to turn on and accurately determine if it has reached its peak current level before shutting off. The typical minimum on-time of the regulator is 60ns. Thus, given an application with varying input and output voltage ranges, the frequency must be designed to be slow enough to ensure the minimum on-time restriction is not violated. Freq (kHz) ≤ VOUT(MIN) 60 • 10−6 • VIN(MAX) In the rare cases where the minimum on-time restriction is violated, the frequency of the LTC3649 will automatically and gradually fold back down to one-fifth of its programmed switching frequency to allow the output to remain in regulation. This feature is designed for applications where the input voltage only experiences momentary spikes in voltage. In such applications, the frequency does not have to be programmed so slow to account for those momentary spikes, thus significantly saving component size and cost. 3649fa For more information www.linear.com/LTC3649 LTC3649 APPLICATIONS INFORMATION Input Capacitor (CIN) Selection The input capacitance, CIN, is needed to filter the square wave current at the drain of the top power MOSFET. To prevent large input voltage droops from occurring, a low effective series resistance (ESR) input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by: IRMS ≅ IOUT(MAX) VOUT VIN important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Using Ceramic Input and Output Capacitors VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS ≅ IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. Output Capacitor (COUT) Selection The selection of COUT is determined by the ESR that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, ∆VOUT, is determined by: 1 ∆VOUT < ∆IL +ESR 8 • f • COUT The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When only a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, use X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. Typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. The output droop, VDROOP, is usually about three times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately: COUT = 3 ∆IOUT f • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is 3649fa For more information www.linear.com/LTC3649 13 LTC3649 APPLICATIONS INFORMATION very low. A 10μF ceramic capacitor is usually enough for these conditions. Place this input capacitor as physically close to the VIN pin as possible. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ∆IL = VOUT V 1− OUT f • L VIN(MAX) Lower ripple current reduces core losses in the inductor and reduces output voltage ripple. However, at extremes, low ripple causes inductor current sensing issues. Highest efficiency operation is obtained at low frequency with reasonably small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 50% of IOUT(MAX). To guarantee that ripple current does not exceed specified inductor saturation current ratings, the inductance should be chosen according to: VOUT VOUT L= 1− f • ∆IL(MAX) VIN(MAX) Table 1. Inductor Selection Table INDUCTOR INDUCTANCE (µH) DCR (mΩ) MAX CURRENT (A) DIMENSIONS (mm) HEIGHT (mm) MANUFACTURER XAL8080 Series 4.7 8.89 17.4 8.6 × 8.1 8.0 Coilcraft www.coilcraft.com XAL1010 Series FDV0840 Series IHLP-4040DZ-A1 Series WE-HCI 1050 Series 14 6.8 13.20 14.0 8.6 × 8.1 8.0 10.0 21.00 10.9 8.6 × 8.1 8.0 3.3 3.70 27.4 11.3 × 10 10.0 4.7 5.20 25.4 11.3 × 10 10.0 5.6 6.30 23.6 11.3 × 10 10.0 6.8 8.10 21.8 11.3 × 10 10.0 8.2 11.70 18.3 11.3 × 10 10.0 10.0 13.40 17.5 11.3 × 10 10.0 2.1 10.40 10.6 9.1 × 8.4 4.0 3.9 18.80 8.4 9.1 × 8.4 4.0 4.9 24.60 6.9 9.1 × 8.4 4.0 6.9 31.70 6.1 9.1 × 8.4 4.0 2.2 8.20 25.6 11.5 × 10.3 4.0 3.3 13.70 18.6 11.5 × 10.3 4.0 4.7 15.00 17.0 11.5 × 10.3 4.0 5.6 17.60 16.0 11.5 × 10.3 4.0 6.8 21.20 13.5 11.5 × 10.3 4.0 10.0 33.20 12.0 11.5 × 10.3 4.0 2.4 3.50 17.0 10.6 × 10.6 5.0 3.3 5.90 15.0 10.6 × 10.6 5.0 4.2 7.10 14.0 10.6 × 10.6 5.0 5.5 10.30 12.0 10.6 × 10.6 5.0 6.5 12.50 10.0 10.6 × 10.6 5.0 7.8 13.60 9.5 10.6 × 10.6 5.0 10.0 16.30 8.5 10.6 × 10.6 5.0 Toko www.toko.com Vishay www.vishay.com Wurth Elektronik www.we-online.com 3649fa For more information www.linear.com/LTC3649 LTC3649 APPLICATIONS INFORMATION Once the value for L is known, the type of inductor must be selected. Core loss is very dependent on the material, frequency and inductance selected. Higher inductance reduces ripple. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. optimization of the control loop behavior and provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects these closed-loop responses. Assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. Ferrite materials have very low core losses and are preferred at high switching frequencies, so design goals can minimize copper loss and preventing saturation. However, ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! The ITH external component network shown in the Figure 2 circuit will provide an adequate starting point for most applications. The RC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested value) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Toko, Vishay, NEC/Tokin, Cooper, TDK and Wurth Elektronik. Refer to Table 1 for more details. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to the ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Checking Transient Response The OPTI-LOOP external compensation allows the transient response to be optimized for a wide range of loads and output capacitors via the ITH pin. This allows for CBOOST 0.1µF VIN 24V L 1.5µH + VIN CIN 22µF CVCC 2.2µF BOOST SW RUN VOUT COUT 3.3V 47µF ×2 VOUT VINREG INTVCC LTC3649 RT ISET RSET 50k CSET 10nF RT 100k MODE/SYNC SGND PGND ITH IMON RITH 3k CITH 4.7nF RIMON 10k CIMON 10nF 3649 F02 Figure 2. 24V to 3.3V, 1MHz Buck Regulator with Output Current Monitoring 3649fa For more information www.linear.com/LTC3649 15 LTC3649 APPLICATIONS INFORMATION The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with the RITH and the bandwidth of the loop increases with decreasing CITH. If RITH is increased by the same factor that CITH is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in most critical frequency ranges of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>10µF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-start operation. through the SW pin. Depending on the size of the output capacitor and the resistivity of the short, high currents may flow through the internal body diode, and cause damage to the part. If a VIN discharge is possible, preventative measures should be taken to prevent current flow through the internal body diode. Simple solutions would be placing a Schottky diode in series with the supply (Figure 3), or placing a Schottky diode from VOUT to VIN (Figure 4). Output Short Considerations In an event where the output of the LTC3649 is shorted to GND through a low resistance, high inductance trace/ wire, it is likely for the output voltage to momentarily drop below GND. In a typical application where the output is tied directly to the VOUT pin, it would violate the ABSMAX specification of the pin and potentially cause damage to the IC. To prevent damage in this case, connect a 100Ω resistor between the output and the VOUT pin. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual power losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: Input Disconnect/Input Short Considerations % Efficiency = 100% – (P1 + P2 + P3 +…) If at any point the input supply is removed with the output voltage still held high through its capacitor, power will be drawn from the output capacitor to power the chip, until the output voltage drops below the minimum VIN requirements of the chip. where P1, P2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3649 circuits: 1) I2R losses, 2) switching and biasing losses, 3) other losses. However, if the VIN pin is grounded while the output is held high, regardless of the RUN state, parasitic body diodes inside the LTC3649 will pull current from the output L VIN VIN VIN VIN SW VOUT LTC3649 LTC3649 CIN 22µF CIN 22µF COUT 47µF 3649 F03 3649 F04 Figure 3. Schottky Diode in Series with the Supply 16 Figure 4. Schottky Diode from VOUT to VIN 3649fa For more information www.linear.com/LTC3649 LTC3649 APPLICATIONS INFORMATION 1.I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows: RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 2.The switching current is the sum of the MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from IN to ground. The resulting dQ/ dt is a current out of IN that is typically much larger than the DC control bias current. In continuous mode: IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. The power loss is thus: diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Thermal Conditions In a majority of applications, the LTC3649 does not dissipate much heat due to its high efficiency and low thermal resistance of its exposed-back QFN and FE packages. However, in applications where the LTC3649 is running at high ambient temperature, high VIN, high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 180°C, both power switches will be turned off until the temperature drops by 15°C. To avoid the LTC3649 from exceeding the maximum junction temperature, some thermal analysis must be done. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA As an example, consider the case when the LTC3649 is used in applications where VIN = 24V, IOUT = 4A, f = 1MHz, and VOUT = 3.3V. The equivalent power MOSFET resistance RSW is: Switching Loss = IGATECHG • VIN The gate charge loss is a function of current through the INTVCC pin as well as frequency. Thus, their effects will be more pronounced in application with high LDO supply voltages (either EXTVCC or VIN) and higher frequencies. 3.Other “hidden” losses such as transition loss and copper trace and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these “system” level losses in the design of a system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The LTC3649 internal power devices switch quickly enough that these losses are not significant compared to other sources. Other losses including V VOUT +RDS(ON)BOT • 1− OUT VIN VIN 3.3V 3.3V + 50mΩ • 1− = 110mΩ • 24V 24V = 58.25mΩ RSW = RDS(ON)TOP • In the case where the EXTVCC pin is connected to the OUT pin, the VIN current will be minimal as most of the current used to bias up internal circuitry and gate drive will come directly from EXTVCC. Typically for a 1MHz application, the current drawn from EXTVCC will be 20mA. Therefore, the total power dissipated by the part is: PD = IOUT2 • RSW + VEXTVCC • IEXTVCC = 16A2 • 58.25mΩ + 3.3V • 20mA = 998mW 3649fa For more information www.linear.com/LTC3649 17 LTC3649 APPLICATIONS INFORMATION The FE28 package junction-to-ambient thermal resistance, θJA, is around 30°C/W. Therefore, the junction temperature of the regulator operating in a 25°C ambient temperature is approximately: TJ = 0.998W • 30°C/W + 25°C = 54.94°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. Redoing the calculation assuming that RSW increased 10% at 54.94°C yields a new junction temperature of 60°C. If the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. If EXTVCC is not connected to VOUT, the IC current will come from VIN. In this case, the total power dissipation will be: PD = 16A2 • 58.25mΩ + 24V • 20mA = 1.41W This will result in an extra 400mW of power dissipation. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3649 (refer to Figure 5). Check the following in your layout: 1.Do the capacitors CIN connect to the VIN and GND as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers. 2.Are COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 3.Solder the exposed pad (Pin 29) on the bottom of the package to the GND plane. Connect this GND plane to other layers with thermal vias to help dissipate heat from the LTC3649. 4.The ground terminal of the ISET resistor must be connected to the other quiet signal GND and together connected to the power GND on only one point. The ISET resistor should be placed and routed away from noisy components and traces, such as the SW line, and its trace should be minimized Figure 5. Sample PCB Layout 18 3649fa For more information www.linear.com/LTC3649 LTC3649 APPLICATIONS INFORMATION 5.Keep sensitive components away from the SW pin. The ISET resistor, RT resistor, the compensation components CITH and RITH, and the INTVCC bypass caps should be routed away from the SW trace and the inductor. 6.A ground plane is preferred. 7.Flood all unused areas on all layers with copper, which reduces the temperature rise of power components. These copper areas should be connected to GND. Design Example As a design example, consider the LTC3649 in an application with the following specifications: VIN = 24V to 36V VOUT = 5V IOUT(MAX) = 4A IOUT(MIN) = 500mA fSW = 1MHz 2ms = 2.3 • RSET • CSET ⇒CSET = 8.7nF A typical 10nF capacitor can be used for CSET. Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. Select from the characteristic curves the correct RT resistor for the 1MHz switching frequency. Based on that, RT should be 100k. Then calculate the inductor value to achieve a current ripple that is about 40% of the maximum load current at maximum VIN: 5V 5V L = 1− = 2.7µH 1MHz • 1.6A 36V COUT will be selected based on the ESR that is required to satisfy the output ripple requirement and the bulk capacitance needed for loop stability. For this design, two 47µF ceramic capacitors will be used. First, the RSET is selected based on: RSET = For a typical soft-start time of 2ms (0% to 90% of final VOUT value), the CSET should be: VOUT 5V = = 100kΩ 50µA 50µA CIN should be sized for a maximum current rating of: For best accuracy, 0.5% 100k resistor is selected. 5V 36V 1/2 IRMS = 4A − 1 = 1.38A 36V 5V Decoupling the VIN pin with one 22µF ceramic capacitor is adequate for most applications. 3649fa For more information www.linear.com/LTC3649 19 LTC3649 TYPICAL APPLICATIONS 0.5V to 32V, 2.1A Low-Noise High Efficiency Lab Supply 0.1µF VIN 40V VIN 10µF 10µF BOOST RUN MODE/SYNC VOUT PGDFB LTC3649 VINREG IN 47µF ISET IMON ITH RT SHDN SET ILIM CDC GND 10k 0.1µF 22µF IMON SGND 40V 2.2µF VOUT 0.5V TO 32V OUT LT3086 47µF PGOOD PGND INTVCC EXTVCC 10µH SW 10k 10nF 10pF 1.5k 200k 1.5nF 100k 357Ω 3649 TA02 20 3649fa For more information www.linear.com/LTC3649 LTC3649 TYPICAL APPLICATIONS Dual Phase Operation 0.1µF VIN 12V NOM 9V TO 36V 10µF 10µF VOUT 5V AT 8A SW VOUT VINREG LTC3649 RUN L1 3.3µH BOOST VIN EXTVCC ISET IMON 47µF PGDFB PGOOD PGND RUN MODE/SYNC INTVCC ITH 47µF RT SGND IMON1 10k 2.2µF V+ OUT1 LTC6908-1 GND OUT2 SET MOD 10pF 4700pF 0.1µF 1k 100k 2nF 49.9k EXT SYNC 1MHz 100k 10k 0.1µF 10pF 4700pF 100k IMON2 EXTVCC ISET IMON ITH INTVCC MODE/SYNC RUN VINREG SGND PGND PGOOD PGDFB LTC3649 VIN 10µF RT 10µF 47µF 47µF VOUT 3.3µH SW BOOST 0.1µF 3649 TA03 3649fa For more information www.linear.com/LTC3649 21 LTC3649 TYPICAL APPLICATIONS Wide Input Signal Range Audio Driver 0.1µF VIN 24V VIN 10µF 10µF SPEAKER BOOST RUN MODE/SYNC SW VOUT LTC3649 PGDFB PGOOD PGND VINREG INTVCC EXTVCC ISET IMON ITH 10µF 4.7µH 10µF 44µF 10µF 0.1µF SGND RT MKP TYPE 22µF 10nF 240k SIGNAL 5nF 10k 200k 1.5k 10nF 10nF 1.5nF LINE LEVEL RECOMMENDED 3649 TA04 Cable Drop Compensation 0.1µF VIN 5.5V to 60V VIN 10µF 10µF BOOST RUN MODE/SYNC EXTVCC INTVCC ISET 0.1µF ITH IMON 95.3k 4.02k PGDFB PGOOD PGND RT SGND 3.9pF 100µF VOUT 5V AT 0A 5V AT 4A RLOAD 50mΩ CABLE RESISTANCE RT 100k 1nF 10pF 2k RISET = 100k 22 50mΩ VOUT LTC3649 VINREG 2.2µF 3.3µH SW 3649 TA05 3649fa For more information www.linear.com/LTC3649 LTC3649 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3649#packaging for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ±0.05 3.10 ±0.05 2.50 REF 2.65 ±0.05 3.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ±0.10 (2 SIDES) 3.50 REF 3.65 ±0.10 2.65 ±0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 ±0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3649fa For more information www.linear.com/LTC3649 23 LTC3649 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3649#packaging for the most recent package drawings. FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation EB 9.60 – 9.80* (.378 – .386) 4.75 (.187) 4.75 (.187) 28 27 26 2524 23 22 21 20 1918 17 16 15 6.60 ±0.10 4.50 ±0.10 2.74 (.108) SEE NOTE 4 0.45 ±0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 6.40 2.74 (.252) (.108) BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.25 REF 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE28 (EB) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3649fa For more information www.linear.com/LTC3649 LTC3649 REVISION HISTORY REV DATE DESCRIPTION A 06/16 Clarified shutdown current to 18μA Clarified IMON conditions Clarified Programming Switching Frequency section PAGE NUMBER 1 3 11 3649fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC3649 25 LTC3649 TYPICAL APPLICATION 5VOUT with Remote Sensing 0.1µF VIN 24V VOUT IN 3.3µH BOOST RUN CABLE RESISTANCE EXTVCC LTC3649 PGDFB INTVCC PGND RT ISET SGND ITH 2k 2.2µF 100k 100k 10nF 47µF 0.1Ω PGOOD VINREG VOUT 5V 47µF ×2 22µF MODE/SYNC 0.1Ω SW 100pF 1.5nF 3649 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3600 15V, 1.5A Synchronous Rail-to-Rail Single Resistor Step-Down Regulator VIN(MIN) = 4V, VIN(MAX) = 15V, VOUT(MIN) = 0V, MSOP-12, 3mm × 3mm DFN-12 LTC3892/ LTC3892-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle PLL Fixed Frequency 50kHz to 900kHz, 4.5V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, IQ = 29µA LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC Controller with 99% Duty Cycle PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA LT®8620 65V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3.4V, VIN(MAX) = 65V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, MSOP-16E 3mm × 5mm QFN-24 LT8641 65V, 4A, 96% Efficiency, 3MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, 3mm × 4mm QFN-18 LT8610A/ LT8610AB 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, MSOP-16E LT8610AC 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA, ISD < 1µA, MSOP-16E LT8611 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA and Input/Output Current Limit/Monitor VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD <1µA, 3mm × 5mm QFN-24 LT8612 42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 3.0µA, ISD <1µA, 3mm × 6mm QFN-28 LT8614 42V, 4A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD <1µA, 3mm × 4mm QFN-18 LT8616 42V, Dual 2.5A + 1.5A, 95% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 5µA VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.8V, IQ = 5µA, ISD <1µA, TSSOP-28E, 3mm × 6mm QFN-28 26 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3649 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3649 3649fa LT 0616 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015