LTC7149 - 60V, 4A Synchronous Step-Down Regulator for Inverting Outputs

LTC7149
60V, 4A Synchronous
Step-Down Regulator for
Inverting Outputs
DESCRIPTION
FEATURES
Wide VIN Range: 3.4V to 60V
nn Wide V
OUT Range: 0V to –28V
nn Single Resistor V
OUT Programming
nn Integrated 110mΩ Top N-Channel/50mΩ Bottom
N-Channel MOSFETs
nn Regulated I : 440µA, Shutdown I : 15µA
Q
Q
nn Board GND Referenced I/O Pins (RUN, PGOOD,
MODE/SYNC)
nn Accurate Resistor Programmable
Frequency (300kHz to 3MHz) with ±50%
Frequency Sync Range
nn 92% Efficiency with 12 V and –5V
IN
OUT
nn ±0.8% Output Voltage Accuracy
nn Peak Current Mode Operation
nn Burst Mode® Operation, Forced Continuous Mode
nn Programmable Soft-Start
nn Overtemperature Protection
nn Available in 28-Lead (4mm x 5mm) QFN and
TSSOP Packages
nn
APPLICATIONS
Industrial Applications
Telecom Power Supplies
nn Distributed Power Systems
nn
The LTC®7149 is a high efficiency 60V, 4A synchronous
monolithic step-down regulator for inverting output
applications. The regulator features a single resistorprogrammable output voltage and high efficiency over a
wide VOUT range.
The inverting regulator operates from an input voltage
range of 3.4V to 60V and provides an adjustable output
from (–28V) to zero volts while delivering up to 4A of
inductor current. The switching frequency is also set
with an external resistor. A user-selectable mode input is
provided to allow the user to trade off ripple noise for efficiency at light loads; Burst Mode operation provides the
highest efficiency at light loads, while forced continuous
mode provides low output ripple. The MODE/SYNC pin
can also be used to synchronize the switching frequency
to an external clock. Internal level-shift circuits allow the
I/O pins (RUN, MODE/SYNC, PGOOD) to be referenced
to board GND.
The LTC7149 operates with a peak current mode architecture that allows for fast transient response with inherent
cycle-to-cycle current limit protection.
L, LT, LTC, LTM, Linear Technology, Burst Mode, OPTI-LOOP and the Linear logo are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554,
6580258.
nn
TYPICAL APPLICATION
Efficiency with V
0.1µF
100
6.8µH
BOOST
RUN
24V
VIN
SW
+
VOUTSNS
22µF
0.1µF
LTC7149
–
INTVCC
ISET
–
SVOUT
90
85
80
MODE/SYNC RT
2.2µF
4.7nF
–
VOUT
–5V
3.3A
VOUT
ITH
100pF
150μF
22µF × 2
GND
1k
95
EFFICIENCY (%)
VIN
75
100k
10nF
VIN = 12V
VIN = 24V
200k
70
fSW = 500kHz
= –5V
Efficiency with V OUT =OUT
–5V
7149 TA01
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
7149 TA01b
7149f
For more information www.linear.com/LTC7149
1
LTC7149
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN Voltage* (Note 3)................................. 64V to –0.3V
ISET Voltage*.............................................. VIN to –0.3V
GND Voltage*.............................................. 28V to –0.3V
RUN Voltage*......................................64V to GND –0.3V
MODE/SYNC, PGOOD Voltage* ...GND + 6V to GND –0.3V
VOUTSNS Voltage*....................................... VIN to –0.3V
RT, PGDFB, ITH, VINREG...............INTVCC +0.3V to –0.3V
EXTVCC Voltage*........................................ 28V to –0.3V
Operating Junction
Temperature Range (Notes 4, 6)......... –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
*All voltage referenced to VOUT –, unless otherwise specified.
PIN CONFIGURATION
TOP VIEW
VOUT– 1
VOUT– 2
–
VOUT
VOUT–
V –
1
28 SW
2
27 SW
3
26 SW
–
VOUT
V –
4
25 SW
5
24 SW
VIN
6
23 SW
VIN
7
RUN
8
GND
9
20 INTVCC
MODE/SYNC 10
19 EXTVCC
SW
SW
SW
OUT
VOUT–
VOUT–
V –
TOP VIEW
28 27 26 25 24 23
OUT
22 SW
21 SW
VIN 3
OUT
20 SW
VIN 4
19 SW
29
SVOUT–
RUN 5
18 BOOST
GND 6
17 INTVCC
MODE/SYNC 7
16 EXTVCC
PGOOD 8
15 ITH
ISET
RT
VOUTSNS
VINREG
SVOUT–
PGDFB
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
29
SVOUT–
22 SW
21 BOOST
PGOOD 11
18 ITH
PGDFB 12
SVOUT– 13
17 ISET
VINREG 14
15 RT
16 VOUTSNS
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS SVOUT–, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 30°C/W, θJC = 5°C to 10°C/W
EXPOSED PAD (PIN 29) IS SVOUT–, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7149EUFD#PBF
LTC7149EUFD#TRPBF
7149
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7149IUFD#PBF
LTC7149IUFD#TRPBF
7149
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7149EFE#PBF
LTC7149EFE#TRPBF
LTC7149
28-Lead Plastic TSSOP
–40°C to 125°C
LTC7149IFE#PBF
LTC7149IFE#TRPBF
LTC7149
28-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
7149f
For more information www.linear.com/LTC7149
LTC7149
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 24V, VEXTVCC = 0V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VIN
Input Supply Operating Voltage Range
VOUT –
Output Operating Voltage Range
(Note 3)
IVIN
Input Quiescent Current
Shutdown Mode; VRUN = 0V
Burst Mode Operation
FC Mode (Note 5)
IISET
Reference Current
VISET + |VOUT –| = 3.3V
MIN
TYP
60 – |VOUT –|
3.4
–28V
l
∆VOUT(LOAD+LINE) Output Voltage Load + Line Regulation
49.6
49.4
l
MAX
–0.05
UNITS
V
V
18
440
1.4
30
600
2.5
µA
µA
mA
50
50
50.4
50.6
µA
µA
0.1
0.5
%
5
mV
700
µS
Error Amp Input Offset
VISET = 3.3V
–5
gm (EA)
Error Amplifier Transconductance
VITH + |VOUT –| = 0.7V,
VOUT – = –3.3V
400
ILSW
Topside NMOS Switch Leakage
RSW
Resistance to VOUT–
RDS(ON)
Topside NMOS On-Resistance
Bottom Side NMOS On-Resistance
110
50
mΩ
mΩ
tON(MIN)
Minimum On-Time
60
ns
VRUN
RUN Input Rising
RUN Hysteresis
IRUN
RUN Input Current
VRUN = 12V
VMODE/SYNC
Burst Mode Operation
FC Mode
VMODE/SYNC = 0V
IMODE/SYNC
MODE/SYNC Input Current
VMODE/SYNC = 0V
ILIM
Peak Current Limit
VEA(OFFSET)
0.5
l
VUVLO
VINTVCC + |VOUT –| Undervoltage Lockout
VUVLO(HYS)
VINTVCC + |VOUT –|
Hysteresis
VIN Rising
1.08
VIN Overvoltage Lockout Rising (VIN + |VOUT –|)
VOVLO(HYS)
VIN Overvoltage Lockout Hysteresis
fOSC
Oscillator Frequency
RT = 100kΩ
fSYNC
SYNC Capture Range
% of Programmed Frequency
VINTVCC
VINTVCC LDO Output Voltage (VINTVCC + |VOUT –|)
VEXTVCC
EXTVCC Switchover Voltage
VIN > 3.6V, VEXTVCC + |VOUT –| = 0V
VIN > 5.0V, VEXTVCC + |VOUT –| > 3.2V
VEXTVCC + |VOUT –|
VOUTSNS Resistance to SVOUT–
IPGDFB
PGDFB Leakage Current
VPGDFB = 0.6V
OVPGDFB
Output Overvoltage PGOOD Upper Threshold
UVPGDFB
Output Undervoltage PGOOD Lower Threshold
VPGFB + |VOUT –| Rising
VPGFB + |VOUT –| Falling
∆VPGDFB
PGOOD Hysteresis
RPGOOD
PGOOD Pull-Down Resistance
IPGOOD(LEAK)
PGOOD Leakage Current
1
µA
1
1.5
MΩ
1.2
120
1.32
V
mV
0
10
nA
0.4
V
V
–8
–5
l
5.7
5.4
6
6
6.3
6.6
A
A
l
2.4
2.65
2.9
V
l
µA
200
mV
64
68
V
2
4
0.92
1
1.08
MHz
150
%
50
l
RVOUTSNS
0.1
1.2
Undervoltage Lockout
VOVLO
550
3.25
2.85
3.45
3
3.65
3.15
V
V
3.1
3.25
3.15
3.2
V
V
80
100
120
kΩ
0
100
nA
0.63
0.645
0.66
V
0.54
0.555
0.57
10
V
mV
550
VPGOOD = 3.3V
V
Ω
100
nA
7149f
For more information www.linear.com/LTC7149
3
LTC7149
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
tPGOOD
PGOOD Delay
PGOOD Low to High
16
PGOOD High to Low
64
VVINREG
Input Voltage Regulation Voltage (VINREG + |VOUT –|)
IVINREG
VINREG Leakage Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Transient absolute maximum voltages should not be applied for
more than 4% of the switching duty cycle.
Note 3: Minimum On-time considerations need to be taken into account
when regulating to an output voltage close to zero. Refer to minimum ontime section in Operations for more details.
Note 4: The LTC7149 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC7149E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
4
MIN
l
1.85
TYP
MAX
UNITS
Switch
Cycles
Switch
Cycles
2
2.15
V
0
100
nA
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7149I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 5: The quiescent current in FC mode does not include switching loss
of the power FETs.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
7149f
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LTC7149
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation
ISET Current vs Temperature
50.5
51
50.3
50
50.1
49
ISET (µA)
100
ISET (µA)
NORMALIZED VOUT (%)
101
49.9
ISET Current vs VISET
48
99
98
VIN = 24V
VOUT = –5V
0
FC MODE
Burst Mode Operation
1
2
IOUT (A)
3
4
49.7
47
49.5
–55 –35 –15
46
5 25 45 65 85 105 125
TEMPERATURE (°C)
VIN = 24V
0
4
8
12
VISET
16
20
7149 G02
7149 G01
ISET Voltage Line Regulation
7149 G03
Quiescent Current vs Temperature
5.01
24
Shutdown Current vs VIN
20
500
400
16
4.99
300
12
4.97
4.96
4.95
RISET = 100kΩ
0
10
20
30
VIN (V)
40
50
60
IQ (µA)
5.00
IQ (µA)
VISET (V)
SLEEP
200
8
100
4
SHUTDOWN
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
7149 G04
0
0
10
20
30
VIN (V)
40
7149 G05
RDS(ON) vs Temperature
50
60
7149 G06
Transient Response, CCM
Transient Response, DCM
200
160
RDSON (mΩ)
MTOP
120
80
MBOT
40
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
VOUT
AC–COUPLED
100mV/DIV
VOUT
AC–COUPLED
100mV/DIV
IL
3A/DIV
IL
2A/DIV
ILOAD
3A/DIV
ILOAD
2A/DIV
20µs/DIV
VIN = 24V, VOUT = –3.3V
IOUT = 0A to 3A, L = 2.2μH, fSW = 1MHz
RITH = 1kΩ, CITH = 2.2nF, CITHP = 100pF
COUT = 2 × 22μF + 150μF
7149 G08
20µs/DIV
VIN = 24V, VOUT = –3.3V
IOUT = 0.2A to 2A, L = 2.2μH, fSW = 1MHz
RITH = 1kΩ, CITH = 2.2nF, CITHP = 100pF
COUT = 2 × 22μF + 150μF
7149 G09
7149 G07
7149f
For more information www.linear.com/LTC7149
5
LTC7149
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency/Period
vs RT
Switching Frequency
vs Temperature
3500
2.5
3000
2500
PERIOD
2000
1.5
1500
1.0
1000
0.5
0
50
100 150 200 250
RT RESISTOR (kΩ)
300
IL
2A/DIV
1000
VOUT –
5V/DIV
995
VPGOOD
5V/DIV
990
500
0
VRUN
2V/DIV
1005
PERIOD (ns)
FREQUENCY (MHz)
FREQUENCY
2.0
Start-Up Waveform
1010
FREQUENCY (kHz)
3.0
0
350
7149 G12
5ms/DIV
985
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
7149 G10
7149 G11
Discontinuous Conduction Mode
Operation
Continuous Conduction Mode
Operation
Run Rising Threshold
vs Temperature
1.210
VSW
10V/DIV
RUN RISING THRESHOLD (V)
VSW
10V/DIV
IL
1A/DIV
IL
1A/DIV
7149 G13
2µs/DIV
7149 G14
500ns/DIV
1.205
1.200
1.195
1.190
1.185
1.180
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
7149 G15
Maximum Output Current vs
Input Voltage
Maximum
Load Current vs. V
Efficiency vs Load Current,
VOUT – = –5V
IN
4.0
100
Efficiency vs Load Current,
VOUT – = –12V
–5VOUT
3.6
90
2.4
2.0
1.6
1.2
0.8
VOUT = –3.3V
VOUT = –5V
VOUT = –12V
0.4
6
0
10
20
30
VIN (V)
40
50
90
EFFICIENCY (%)
EFFICIENCY (%)
IOUT (A)
2.8
0
95
95
3.2
OUT
100
85
80
60
7149 G16
70
0
0.5
1
1.5
2
IOUT (A)
2.5
3
3.5
80
75
70
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
75
85
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
65
60
4
7149 G17
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
7149 G18
7149f
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LTC7149
PIN FUNCTIONS
(QFN/TSSOP)
VOUT – (Pins 1, 2, 26-28/Pins 1-5): Negative Output of the
Step-Down Regulator.
the external clock is within this range or RT is set to accommodate the external clock for proper frequency lock.
VIN (Pin 3, 4/Pins 6, 7): Input Supply Pin of the StepDown Regulator.
VOUTSNS (Pin 13/Pin 16): Output Voltage Error Amplifier
Input Pin. For majority of applications, connect this pin
to GND.
RUN (Pin 5/Pin 8): Logic Controlled RUN Input. Do not
leave this pin floating. Place a resistor divider from VIN to
GND for an accurate VIN undervoltage threshold.
GND (Pins 6/Pins 9): Board Ground Sense Pins. Connect
pins to PCB ground.
MODE/SYNC (Pin 7/Pin 10): Mode Select and Oscillator
Synchronization Input of the Step-Down Regulator. Leave
MODE/SYNC floating for forced continuous mode operation or tie MODE/SYNC to GND for Burst Mode operation.
Furthermore, connecting MODE/SYNC to an external clock
will synchronize the internal oscillator to the external clock
signal and put the part in forced continuous mode.
PGOOD (Pin 8/Pin 11): VOUT – Within Regulation Indicator. PGOOD is pulled to GND when VPGDFB is more than
0.645V or less than 0.555V with respect to VOUT –.
PGDFB (Pin 9/Pin 12): Power Good Feedback. Place a
resistor divider from GND to VOUT – to detect power good
level.
VINREG (Pin 11/Pin 14): Input Voltage Regulation Sense
Input. Place a resistor divider from VIN to VOUT – to program
the level of input voltage regulation. To disable feature,
connect the pin to INTVcc.
RT (Pin 12/Pin 15): Oscillator Frequency Programming
Pin. Connect an external resistor between 500k to 40k from
RT to SVOUT – to program the frequency from 200kHz to
2.5MHz respectively. Since the synchronization range is
limited to ±50% of the set frequency, be sure that either
ISET (Pin 14/Pin 17): Accurate 50µA Bias Current and
Positive Input to the Error Amplifier. Connect an external
resistor from this pin to VOUT – to program the output
voltage. Connecting an external capacitor from ISET to
VOUT – will soft start the output voltage by reducing current
inrush during start-up.
ITH (Pin 15/Pin 18): Error Amplifier Output and Switching
Regulator Compensation Point. The current comparator’s
trip threshold is linearly proportional to this voltage. Tying
this pin to INTVCC activates internal compensation.
EXTVCC (Pin 16/ Pin 19): External Power Input to the
Internal Regulator. The internal regulator will draw current from EXTVCC instead of VIN when EXTVCC is tied to a
voltage higher than 3.2V above VOUT – and VIN is 5V above
VOUT –. For output voltages at or below –3.3V, this pin can
be tied to GND. If this pin is tied to a supply other than
GND, locally bypass with at least a 1µF to VOUT –.
INTVCC (Pin 17/Pin 20): Low Dropout Regulator. Locally
bypass with at least 1µF to VOUT –.
BOOST (Pin 18/Pin 21): Boosted Floating Driver Supply
for Internal Top Power MOSFET. Place a 0.1µF bootstrap
capacitor between BOOST and SW.
SW (Pins 19-25/Pins 22-28): Switch Node Connection to
the Inductor of the Regulator.
SVOUT – (Pins 10, 29/Pins 13, 29): The exposed pad must
be soldered to a PCB metal plane to SVOUT– for electrical
connection and rated thermal performance.
7149f
For more information www.linear.com/LTC7149
7
LTC7149
FUNCTIONAL DIAGRAM
BOOST
VIN
INTVCC
1/50k
VIN
–
50µA
ISET
+
–
VOUTSNS
PEAK-CURRENT
COMPARATOR
REVERSE
COMPARATOR
+
+
EXTVCC
0A
LDO
–
100k
SVOUT–
ITH
VINREG
+
–
+
–
RT
2V
SVOUT
BUCK LOGIC
AND
GATEDRIVE
–
OSC
MODE/SYNC
RUN
SW
PGDFB
INTVCC
PGOOD
LOGIC
CLK
PGOOD
LEVEL
SHIFT
SVOUT–
VOUT–
GND
7149 BD
8
7149f
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LTC7149
OPERATION
The LTC7149 is a current mode monolithic step-down
regulator. The accurate 50μA bias current on the ISET
pin allows the user to program the output voltage in a
unity-gain buffer fashion with just one external resistor,
RSET, from the ISET pin to VOUT–. The output voltage is
set such that:
VOUT– = –50μA • RSET
The LTC7149 operates through a wide VIN range, and its
frequency can be programmed to a wide range with the RT
resistor. To suit a variety of applications, the MODE/SYNC
pin allows the user to trade off output ripple for efficiency.
Main Control Loop
In normal operation, the internal top power MOSFET is
turned on at the beginning of a clock pulse. The inductor
current is allowed to ramp up to a peak level. Once that
level is reached, the top power switch is turned off and
the bottom switch is turned on until the next clock cycle.
The peak inductor current is determined by sensing the
voltage drop across the SW and VIN nodes of the top power
MOSFET. The voltage on the ITH pin sets the comparator
threshold corresponding to inductor peak current. The
error amplifier, EA, adjusts this ITH voltage by comparing
the differential VOUTSNS voltage to VOUT– with the voltage
on ISET. In the typical application where the VOUTSNS pin
is tied to GND, if the load current into VOUT – increases, it
causes an increase in VISET with respect to VOUTSNS. This
causes the ITH voltage to rise until the current into VOUT –
provided by the regulator matches that of the load current.
Low Current Operation
Burst Mode operation can be selected by connecting the
MODE/SYNC pin to GND. In this mode, the LTC7149 will
automatically transition from continuous mode operation
to Burst Mode operation when the load current is low. A
reverse current comparator looks at the voltage across SW
to GND and turns off the bottom power MOSFET when
that voltage difference approaches zero. This prevents the
inductor current from going negative. An internal burst
clamp is set to be approximately 1A, which means that in
Burst Mode, the peak inductor current will never go below
1A regardless of what the ITH voltage demands the peak
current to be. As a result, when the load is low enough,
VOUTSNS will rise relative to VISET because the average
programmed inductor current is above the load current,
thus driving VITH low. Once the ITH voltage is driven below
an internal threshold (~400mV), the switching regulator
will enter its sleep mode and wait for VOUT to drop and
VITH to rise above the threshold before it starts to switch
again. During sleep mode, the quiescent current of the
part is reduced to 440µA to conserve input power. The
LTC7149 is designed to operate with single burst pulse
behavior to minimize output voltage ripple while keeping
the efficiency high at light loads. Lastly, if at any point
the top power MOSFET is on for roughly 8 consecutive
cycles, the part will turn on the bottom power MOSFET
for a brief duration such that the BOOST capacitor can
be replenished.
Forced Continuous Mode Operation
Floating the MODE/SYNC pin defaults the LTC7149 into
forced continuous mode operation. In this mode, the part
switches continuously regardless of load current, and the
inductor peak current is allowed to decrease to approximately –1A to allow for significant negative average current.
High Duty Cycle/Dropout Operation
As the input voltage decreases towards the desired output
voltage, the duty cycle will increase towards 100%. However, given the architecture, there are two restrictions that
prevent the LTC7149 from operating in full dropout mode.
The first restriction is due to how the ISET voltage is
programmed. If a resistor is placed between ISET and
VOUT – to set the output voltage, the 50µA of current out
of the ISET pin is only guaranteed to be accurate when
VISET is more than 500mV below VIN. As the input voltage drops below that 500mV threshold, the ISET current
will decrease, thus limiting the programmed voltage.
Typically, VISET will never get within 300mV of VIN. Since
VISET programs VOUT –, this limitation essentially enforces
a maximum duty cycle for the switcher. This limitation
can be overcome if an accurate external supply is used
to drive the ISET pin directly.
7149f
For more information www.linear.com/LTC7149
9
LTC7149
OPERATION
The second limitation against full dropout operation is the
requirement for the BOOST to SW capacitor to refresh.
When the top power MOSFET is on indefinitely during
dropout operation, the BOOST to SW capacitor slowly
gets depleted by the internal circuitry of the chip. When
the bottom switch does not turn on for at least 80ns for
8 periods, it is forced to turn on in order to guarantee
sufficient voltage on the bootstrap capacitor. During a
refresh, the bottom switch will only turn on for roughly
30% of the period to limit inductor ripple, thus limiting
output voltage ripple.
Input Voltage Regulation
In certain applications, the input supply to the power regulator can exhibit fairly high output impedance. As a result,
when the regulator is running at heavy loads, VIN might
droop more than desired. The input voltage regulation loop
allows the application to be programmed to decrease the
peak inductor current level, and consequently the input
current draw, when it senses that the input voltage has
dropped below a programmed threshold. If VINREG ever
falls below 2V above VOUT –, the regulator will decrease
the output current level in order to maintain the 2V at the
pin. If this feature is not required, tie the VINREG pin to
INTVCC to prevent this control loop from interfering with
normal operation.
INTVCC Regulator
The LTC7149 has two onboard internal low dropout
(LDO) regulators that power the drivers and internal bias
circuitry. Regardless of which one is in operation, the
INTVCC must be bypassed to VOUT – with a minimum of
2.2µF ceramic capacitor. Good bypassing is necessary to
supply the high transient current required by the power
MOSFET gate drivers.
The first LDO is powered from VIN, and the INTVCC voltage is
regulated to 3.3V above VOUT –. The power dissipated across
this LDO would thus be equal to (VIN  + |VOUT –|–3.3V)•
IINTVCC. For a typical 1MHz application running in CCM,
the current drawn from INTVCC by the chip is roughly
20mA. Thus, if the input voltage is high, the power loss
and heat rise due to this LDO might be quite significant.
10
To combat this issue, a separate LDO exists that is powered
from EXTVCC. As long as the input voltage is above 5V and
the EXTVCC voltage is >3.2V above VOUT –, this LDO will take
over and regulate the INTVCC voltage to 3.1V above VOUT–.
In applications where the output voltage is programmed
to –3.3V or below, it is recommended that the EXTVCC pin
be directly tied to the GND pin. Furthermore, if a separate
lower voltage rail exists on board that can supply INTVCC
current, then attaching that supply to EXTVCC will also
suffice provided that a 1µF ceramic bypass capacitor is
placed from the EXTVCC pin to VOUT – physically close to
the chip. Both examples should significantly reduce the
power loss through the LDO.
VIN Undervoltage Programming
LTC7149 offers an accurate RUN threshold to start the
regulator. As a result, a resistor divider from VIN to GND
can be placed with the intermediate node fed back to RUN
to set an accurate VIN undervoltage threshold. As the input
voltage rises, the RUN voltage will increase above the VRUN
rising threshold (1.2V), and the regulator will turn on.
Similarly, once on, if the input voltage decreases below the
VRUN falling threshold (1.1V), the regulator will turn off.
VIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC7149 constantly
monitors the VIN pin for an overvoltage condition. When
VIN + |VOUT –| rises above VOVLO the regulator suspends
operation by shutting off both power MOSFETs and discharges the ISET pin voltage to ground. Once VIN drops
below VOVLO – VOVLO(HYST), the regulator resumes normal
switching operation.
Programming Switching Frequency
Connecting a resistor from the RT pin to SVOUT – programs
the switching frequency from 200kHz to 3MHz according
to the following formula:
Frequency (Hz) =
1011 (1/ F )
RT (Ω) Do not float the RT pin.
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LTC7149
OPERATION
The internal phase-locked loop has a synchronization range
of ±50% around its programmed frequency. Therefore,
during external clock synchronization, the proper RT value
should be selected such that the external clock frequency
is within this 50% range of the RT programmed frequency.
Output Voltage Tracking and Soft-Start
The LTC7149 allows the user to program its output voltage
ramp rate by means of the ISET pin. Since VOUTSNS servos
its voltage to that of VISET, placing an external capacitor
CSET from the ISET pin to VOUT– will program the ramp-up
rate of the ISET pin and thus the VOUT – voltage.


1


VOUT – (t) =IISET •RSET  1− e R SET • C SET 




From 0% to 90% VOUT –:
tSS ≅ –RSET • CSET • In(1 – 0.9)
tSS ≅ 2.3 • RSET • CSET
The soft-start time tSS (from 0% to 90% of VOUT) is 2.3
times the time constant (RSET • CSET). The ISET pin can also
be driven by an external supply capable of sinking 50µA.
When starting up into a pre-biased VOUT –, the LTC7149
will stay in Burst Mode operation and keep the power
switches off until the voltage on ISET has ramped up to
be equal to VOUTSNS, at which point the switcher will begin
switching and VOUT – will start to decrease at the rate to
maintain: VISET = VOUTSNS.
Output Power Good
When the LTC7149’s output voltage is within the 7.5%
window of the regulation point, which is divided down as
a VPGDFB voltage in the range of 0.555V to 0.645V with
respect to VOUT –, the output voltage is in regulation and
the PGOOD pin is pulled high with an external resistor
connected to a voltage rail less than 6V above GND. Otherwise, an internal open-drain pull-down device will pull
the PGOOD pin low to GND. To prevent unwanted PGOOD
glitches during transients or dynamic VOUT – changes, the
LTC7149’s PGOOD falling edge includes a blanking delay
of approximately 64 clock cycles.
Internal/External ITH Compensation
For ease of use, the user can simplify the loop compensation by tying the ITH pin to INTVCC to enable internal
compensation. Because the internal compensation is
required to provide a stable output voltage for a wide
range of switching frequencies, it is designed to have a
loop response that is typically much slower than optimal.
This thus becomes a trade-off between simplicity and
OPTI‑LOOP® optimization, where ITH components are
external and are selected to optimize the loop transient
response with minimum output capacitance.
Minimum On-Time Considerations
Due to the architecture of the LTC7149, a minimum on-time
restriction is imposed such that the top power MOSFET
can have enough time to turn on and accurately determine
if it has reached its peak current level before shutting off.
The typical minimum on-time of the regulator is 60ns.
Thus, given an application with varying input and output
voltage ranges, the frequency must be designed to be
slow enough to ensure the minimum on-time restriction
is not violated.
In the rare cases where the minimum on-time restriction is
violated, the frequency of the LTC7149 will automatically
and gradually fold back down to one-fifth of its programmed
switching frequency to allow the output to remain in regulation. This feature is designed for applications where the
input voltage only experiences momentary spikes in voltage. In such applications, the frequency does not have to
be programmed so slow to account for those momentary
spikes, thus significantly saving component size and cost.
tON(MIN) =
| VOUT – |
1
•
VIN(MAX) +| VOUT – | fSW
Choose the appropriate switching frequency to guarantee
the tON(MIN) does not approach the minimum on-time
number.
The minimum on-time occurs at maximum VIN.
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LTC7149
APPLICATIONS INFORMATION
Input Capacitor (CIN) Selection
The input capacitance, CIN, is needed to filter the square
wave current at the drain of the top power MOSFET. To
prevent large input voltage droops from occurring, a low
effective series resistance (ESR) input capacitor sized for
the maximum RMS current should be used. The maximum
RMS current is given by:
∆VOUT(CHARGE) ≅
IOUT  |VOUT– |

fSW •COUT  VIN +|VOUT–



| 
The ESR of the COUT is also a major factor in total output
voltage ripple. The ripple due to ESR is:
|VOUT– |
IRMS ≅IOUT(MAX) •
VIN
This formula has a maximum at VIN = |VOUT –|, where
IRMS ≅ IOUT. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design. For low input voltage applications, sufficient bulk
input capacitance is needed to minimize transient effects
during output load changes.
Output Capacitor (COUT) Selection
The selection of COUT is determined by the ESR that is
required to minimize voltage ripple and load step transients
as well as the amount of bulk capacitance that is necessary
to ensure that the control loop is stable. Loop stability can
be checked by viewing the load transient response.
When the top power FET is on, the current into the VOUT –
terminal of COUT is equal to the load current, ILOAD. When
the bottom power FET is on, the current into the VOUT –
12
terminal of COUT is equal to the load current subtracted
by the inductor current, IL. In equilibrium, the charge lost
during one phase is replenished in the other, and the output
ripple, ΔVOUT(CHARGE)–, is determined by:
∆VOUT(ESR) ≅ILPK •RESR ,Where:
 V +| V –
OUT
ILPK =IOUT  IN

VIN

VIN •| VOUT– |
| 
+

–
 2fSW •L •(VIN +| VOUT |)
The total output voltage ripple is thus:
∆VOUT = ∆VOUT(CHARGE) + ∆VOUT (ESR)
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Special polymer capacitors are very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR,
but can be used in cost-sensitive applications provided
that consideration is given to ripple current ratings and
long-term reliability. Ceramic capacitors have excellent
low ESR characteristics and small footprints.
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APPLICATIONS INFORMATION
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When only a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
use X5R or X7R dielectric formulations. These dielectrics
have the best temperature and voltage characteristics of
all the ceramics for a given value and size.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load.
More capacitance may be required depending on the duty
cycle and load step requirements. In most applications,
the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is
very low. A 22µF ceramic capacitor is usually enough for
these conditions. Place this input capacitor as physically
close to the VIN pin as possible.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
–VIN(MAX) 
| VOUT– |
∆IL =
|
fSW • L  VIN(MAX) + | VOUT–




| 
Lower ripple current reduces core losses in the inductor
and reduces output voltage ripple. However, at extremes,
low ripple causes inductor current sensing issues. Highest efficiency operation is obtained at low frequency with
reasonably small ripple current. However, achieving this
requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 2A. To guarantee that ripple current does not
exceed specified inductor saturation current ratings, the
inductance should be chosen according to:
L=

| VOUT– |


• ∆IL(MAX)  VIN(MAX) + | VOUT–

VIN(MAX)
fSW



| 
Once the value for L is known, the type of inductor must
be selected. Core loss is very dependent on the material,
frequency and inductance selected. Higher inductance
reduces ripple. Unfortunately, increased inductance requires more turns of wire and therefore copper losses
will increase.
Ferrite materials have very low core losses and are preferred at high switching frequencies, so design goals can
minimize copper loss and preventing saturation. However,
ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Wurth Elektronik. Refer to
Table 1 for more details.
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13
LTC7149
APPLICATIONS INFORMATION
Table 1. Inductor Selection Table
INDUCTOR
INDUCTANCE (µH)
XAL8080 Series
XAL1010 Series
FDV0840 Series
IHLP-4040DZ-A1
Series
WE-HCI 1050 Series
14
DCR (mΩ)
MAX CURRENT (A)
DIMENSIONS (mm)
HEIGHT (mm)
MANUFACTURER
4.7
8.89
17.4
8.6 × 8.1
8.0
6.8
13.20
14.0
8.6 × 8.1
8.0
Coilcraft
www.coilcraft.com
10.0
21.00
10.9
8.6 × 8.1
8.0
3.3
3.70
27.4
11.3 × 10
10.0
4.7
5.20
25.4
11.3 × 10
10.0
5.6
6.30
23.6
11.3 × 10
10.0
6.8
8.10
21.8
11.3 × 10
10.0
8.2
11.70
18.3
11.3 × 10
10.0
10.0
13.40
17.5
11.3 × 10
10.0
15.0
16.9
15.5
11.3 × 10
10.0
2.1
10.40
10.6
9.1 × 8.4
4.0
3.9
18.80
8.4
9.1 × 8.4
4.0
4.9
24.60
6.9
9.1 × 8.4
4.0
6.9
31.70
6.1
9.1 × 8.4
4.0
2.2
8.20
25.6
11.5 × 10.3
4.0
3.3
13.70
18.6
11.5 × 10.3
4.0
4.7
15.00
17.0
11.5 × 10.3
4.0
5.6
17.60
16.0
11.5 × 10.3
4.0
6.8
21.20
13.5
11.5 × 10.3
4.0
10.0
33.20
12.0
11.5 × 10.3
4.0
2.4
3.50
17.0
10.6 × 10.6
5.0
3.3
5.90
15.0
10.6 × 10.6
5.0
4.2
7.10
14.0
10.6 × 10.6
5.0
5.5
10.30
12.0
10.6 × 10.6
5.0
6.5
12.50
10.0
10.6 × 10.6
5.0
7.8
13.60
9.5
10.6 × 10.6
5.0
10.0
16.30
8.5
10.6 × 10.6
5.0
Toko
www.toko.com
Vishay
www.vishay.com
Wurth Elektronik
www.we-online.com
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LTC7149
APPLICATIONS INFORMATION
Checking Transient Response
The OPTI-LOOP external compensation allows the transient response to be optimized for a wide range of loads
and output capacitors via the ITH pin. This allows for
optimization of the control loop behavior and provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test point
truly reflects these closed-loop responses. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin.
The typical application section provides adequate starting
points for different applications. The RC filter sets the
dominant pole-zero loop compensation. The values can be
modified slightly (from 0.5 to 2 times their suggested value)
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1µs to 10µs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a step
in load current. When a load step occurs, VOUT – immediately shifts by an amount equal to the ∆ILOAD • ESR, where
ESR is the effective series resistance of COUT. ∆ILOAD also
begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT – to its
steady-state value. During this recovery time, VOUT – can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the RITH and
the bandwidth of the loop increases with decreasing CITH. If
RITH is increased by the same factor that CITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in most critical frequency ranges of
the feedback loop.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Max Output Current
The maximum output current for the LTC7149 is equal to:
IOUT(MAX) = 4A • (1– Deff )
Such that Deff denotes the effective duty cycle of the
application. On the first order,
Deff ≈
| VOUT – |
VIN + | VOUT – |
However, voltage drops across the power switches and
inductor DCR leads to errors in that approximation.
Deff =
| VOUT – | + 4A • RL + 4A • RBOT
VIN + | VOUT – | – 4A • RTOP + 4A • RBOT
Deff =
| VOUT – | + 4A • RL + 0.2V
VIN + | VOUT – | – 0.24V
Where RL is the DCR of the inductor.
Refer to Maximum Output Current vs Input Voltage in
the typical performance characteristics section for a quick
reference.
Output Short Considerations
In an event where the output of the LTC7149 is shorted
to GND through a low resistance, high inductance trace/
wire, it is likely for the VOUT– voltage to momentarily spike
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LTC7149
APPLICATIONS INFORMATION
above board GND. In a typical application where the GND
and VOUTSNS pins are tied directly to the board GND, it
would violate the ABSMAX specification of those pins and
potentially cause damage to the IC. To prevent damage in
this case, connect a 100Ω resistor between the VOUTSNS
pin to board GND, and a 20Ω resistor between the GND
pin to board GND.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual power losses to determine what is limiting the efficiency and which change
would produce the most improvement. Percent efficiency
can be expressed as:
% Efficiency = 100% – (P1 + P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, three main sources usually account
for most of the losses in LTC7149 circuits: 1) I2R losses,
2) switching and biasing losses, 3) other losses.
1.I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET RDS(ON) and the duty
cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
16
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
2.The switching current is the sum of the MOSFET driver
and control currents. The power MOSFET driver current results from switching the gate capacitance of
the power MOSFETs. Each time a power MOSFET gate
is switched from low to high to low again, a packet of
charge dQ moves from VIN to ground. The resulting dQ/
dt is a current out of VIN that is typically much larger
than the DC control bias current. In continuous mode:
IGATECHG = f(QT + QB)
where QT and QB are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. The power loss is thus:
Switching Loss = IGATECHG • VIN
The gate charge loss is a function of current through
the INTVCC pin as well as frequency. Thus, their effects
will be more pronounced in application with high LDO
supply voltages (either EXTVCC or VIN) and higher
frequencies.
3.Other “hidden” losses such as transition loss and copper trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC7149 internal power devices
switch quickly enough that these losses are not significant compared to other sources. Other losses including
diode conduction losses during dead-time and inductor
core losses which generally account for less than 2%
total additional loss.
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Thermal Conditions
Therefore, the total power dissipated by the part is:
In a majority of applications, the LTC7149 does not dissipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN and FE packages. However, in applications where the LTC7149 is running at high
ambient temperature, high VIN, high switching frequency,
and maximum output current load, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
180°C, both power switches will be turned off until the
temperature drops by 15°C.
To avoid the LTC7149 from exceeding the maximum junction temperature, some thermal analysis must be done.
The goal of the thermal analysis is to determine whether
the power dissipated exceeds the maximum junction
temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
As an example, consider the case when the LTC7149
is used in applications where VIN = 24V, VOUT – = –5V,
IOUT = 4A1 and f = 1MHz. The equivalent power MOSFET
resistance RSW is:
| VOUT |
VIN + | VOUT – |

| VOUT – |
•  1–

VIN + | VOUT –

RSW = RDS(ON)TOP •
+RDS(ON)BOT
= 110mΩ•
–



| 

5V
5V 
+ 50mΩ•  1–

29V
 29V 
= 60.3mΩ
In the case where the EXTVCC pin is connected to the GND,
the VIN current will be minimal as most of the current
used to bias up internal circuitry and gate drive will come
directly from EXTVCC. Typically for a 1MHz application, the
current drawn from EXTVCC will be 20mA.
PD = IOUT 2 • RSW + VEXTVCC •IEXTVCC
= 16A 2 • 60.3mΩ + 5V • 20mA
= 1.07W
The FE28 package junction-to-ambient thermal resistance,
θJA, is around 30°C/W. Therefore, the junction temperature
of the regulator operating in a 25°C ambient temperature
is approximately:
TJ = 1.07W • 30°C/W + 25°C = 57°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. Redoing the calculation
assuming that RSW increased 10% at 57°C yields a new
junction temperature of 63°C. If the application calls for
a higher ambient temperature and/or higher switching
frequency, care should be taken to reduce the temperature
rise of the part by using a heat sink or air flow.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC7149 (refer to Figure 1). Check the following in
your layout:
1.Do the capacitors CIN connect to the VIN and VOUT – as
close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers.
2.Are COUT and L closely connected? The (+) plate of
COUT returns current to GND and the (–) plate of CIN.
3.Solder the exposed pad (Pin 29) on the bottom of the
package to the GND plane. Connect this GND plane to
other layers with thermal vias to help dissipate heat
from the LTC7149.
4.The ground terminal of the ISET resistor must be connected to the other quiet signal SVOUT – and together
connected to the power VOUT – on only one point. The
ISET resistor should be placed and routed away from
noisy components and traces, such as the SW line, and
its trace should be minimized.
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LTC7149
APPLICATIONS INFORMATION
5.Keep sensitive components away from the SW pin. The
ISET resistor, RT resistor, the compensation components CITH and RITH, and the INTVCC bypass caps should
be routed away from the SW trace and the inductor.
6.A ground plane is preferred.
7.Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
Design Example
As a design example, consider the LTC7149 in an application with the following specifications:
VIN = 24V to 36V
IOUT(MAX) = 3A
fSW = 1MHz
First, the RSET is selected based on:
⇒CSET = 8.7nF
A typical 10nF capacitor can be used for CSET.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized. Select from
the characteristic curves the correct RT resistor for the
1MHz switching frequency. Based on that, RT should be
100k. Then calculate the inductor value to achieve a current ripple that is about 40% of the maximum load current
at maximum VIN:
CIN should be sized for a maximum current rating of:
V
5V
= OUT =
= 100kΩ
50µA 50µA
For best accuracy, a 0.1% 100k resistor is selected.
18
COUT will be selected based on the ESR that is required
to satisfy the output ripple requirement and the bulk capacitance needed for loop stability. For this design, two
47µF ceramic capacitors will be used.
IOUT(MIN) = 500mA
2ms = 2.3 • RSET • CSET

  5V 
36V


L = 
  41V  = 1.8µH
1MHz
•
2.4A



VOUT – = –5V
RSET
For a typical soft-start time of 2ms (0% to 90% of final
VOUT value), the CSET should be:
IRMS = 3A
5V
= 1.37A
24V
Decoupling the VIN pin with one 22µF ceramic capacitor
is adequate for most applications.
7149f
For more information www.linear.com/LTC7149
LTC7149
TYPICAL APPLICATIONS
12V Input to –5V Output at 1MHz Operation
CBOOST
0.1µF
L1
2.4μH
VIN
12V
RUN
CIN
22µF
BOOST
VIN
SW
VOUTSNS
LTC7149
GND
MODE/SYNC
VINREG
OUT
RT
CVCC
2.2µF
RT
100k
OUT
–5V
2.8A
SVOUT–
INTVCC
CIN2
0.1µF
COUT
22µF × 4
V –
EXTVCC
V –
ISET
RSET
100k
ITH
CSET
10nF
RITH
1.4k
CITH
2.2nF
CITHP
220pF
7149 TA03
Transient Response
300mA–1.8A–300mA
ILOAD 2A/DIV
IL 2A/DIV
VOUT
100mV/DIV
20µs/DIV
7149 TA03b
7149f
For more information www.linear.com/LTC7149
19
LTC7149
TYPICAL APPLICATIONS
12V Input to –12V Output at 1MHz Operation
CBOOST
0.1µF
L1
6.5μH
VIN
12V
RUN
CIN
22µF
BOOST
VIN
SW
VOUTSNS
LTC7149
GND
MODE/SYNC
VINREG
OUT
RT
CVCC
2.2µF
ISET
RT
100k
OUT
–12V
2A
SVOUT–
INTVCC
CIN2
0.1µF
COUT
22µF × 4
V –
EXTVCC
V –
RSET
240k
ITH
CSET
10nF
RITH
845Ω
CITH
4.7nF
CITHP
220pF
7149 TA04
Transient Response
200mA–1.2A–200mA
ILOAD 1A/DIV
IL 2A/DIV
VOUT
200mV/DIV
20µs/DIV
20
7149 TA04b
7149f
For more information www.linear.com/LTC7149
LTC7149
TYPICAL APPLICATIONS
24V Input to –5V Output at 1MHz Operation
CBOOST
0.1µF
L1
2.4μH
VIN
24V
RUN
CIN
22µF
BOOST
VIN
SW
VOUTSNS
LTC7149
GND
MODE/SYNC
VINREG
OUT
RT
CVCC
2.2µF
OUT
–5V
3.3A
SVOUT–
INTVCC
CIN2
0.1µF
COUT
22µF x 4
V –
EXTVCC
V –
ISET
RT
100k
ITH
RSET
100k
CSET
10nF
RITH
1.5k
CITH
1.5nF
CITHP
150pF
7149 TA05
Transient Response
300mA–1.8A–300mA
ILOAD 2A/DIV
IL 2A/DIV
VOUT
100mV/DIV
20µs/DIV
7149 TA05b
7149f
For more information www.linear.com/LTC7149
21
LTC7149
TYPICAL APPLICATIONS
24V Input to –12V Output at 1MHz Operation
CBOOST
0.1µF
L1
7.8μH
VIN
24V
RUN
CIN
22µF
BOOST
VIN
SW
VOUTSNS
LTC7149
GND
MODE/SYNC
VINREG
OUT
RT
CVCC
2.2µF
ISET
RT
100k
OUT
–12V
2.6A
SVOUT–
INTVCC
CIN2
0.1µF
COUT
22µF × 4
V –
EXTVCC
V –
RSET
240k
ITH
CSET
10nF
RITH
1.33k
CITH
3.3nF
CITHP
220pF
7149 TA06
Transient Response
ILOAD 1A/DIV
IL 2A/DIV
VOUT
100mV/DIV
20µs/DIV
22
7149 TA06b
7149f
For more information www.linear.com/LTC7149
LTC7149
TYPICAL APPLICATIONS
24V Input to –24V Output at 1MHz Operation
CBOOST
0.1µF
L1
15μH
VIN
24V
RUN
CIN
22µF
BOOST
VIN
SW
VOUTSNS
LTC7149
GND
MODE/SYNC
VINREG
OUT
INTVCC
CIN2
0.1µF
RT
CVCC
2.2µF
COUT
22µF × 4
EXTVCC
V –
–
SVOUT
ISET
RT
100k
RSET
480k
COUT2
33µF
VOUT–
–24V
2A
ITH
CSET
10nF
RITH
1.33k
CITH
3.3nF
CITHP
220pF
7149 TA07
Transient Response
ILOAD 500mA/DIV
IL 1A/DIV
VOUT
50mV/DIV
20µs/DIV
7149 TA07b
7149f
For more information www.linear.com/LTC7149
23
LTC7149
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC7149#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
24
7149f
For more information www.linear.com/LTC7149
LTC7149
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC7149#packaging for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV K 0913
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
7149f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC7149
25
LTC7149
TYPICAL APPLICATION
24V Input Concurrent ±12V Supply
CBOOST1
0.1µF
L1
3.3μH
VIN
24V
RUN
BOOST
VIN
CIN1
22µF
VOUT
MODE/SYNC
SGND
VINREG
PGND
INTVCC
RT
ISET
RT1
100k
COUT1
47µF × 2
EXTVCC
LTC3649
ITH
CVCC1
2.2µF
12V
4A RAIL
SW
RSET3
1k
IMON
RSET1
240k
CSET1
10nF
CBOOST2
0.1µF
L2
4.7μH
RUN
CIN2
22µF
BOOST
VIN
VOUTSNS
EXTVCC
MODE/SYNC
VOUT–
SV –
LTC7149
GND
VINREG
RT
CVCC2
2.2µF
COUT2
47µF × 2
OUT
INTVCC
CIN3
0.1µF
SW
ISET
ITH
RT2
100k
RITH
1.33k
CITH
3.3nF
CITHP
220pF
CSET2
10nF
RSET2
240k
RSET4
1k
7149 TA02
–12V
2.5A RAIL
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3649
60V, 4A Synchronous Rail-to-Rail Single Resistor Step-Down
Regulator
VIN(MIN) = 3.1V, VIN(MAX) = 60V, VOUT(MIN) = 0V, 4mm × 5mm
QFN-28, TSSOP-28E
LTC3600
15V, 1.5A Synchronous Rail-to-Rail Single Resistor Step-Down
Regulator
VIN(MIN) = 4V, VIN(MAX) = 15V, VOUT(MIN) = 0V, MSOP-12,
3mm × 3mm DFN-12
LTC3892/
LTC3892-1
60V, Low IQ, Dual 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4.5V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 0.99VIN, IQ = 29µA
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC Controller with
99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LT®8620
65V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN(MIN) = 3.4V, VIN(MAX) = 65V, VOUT(MIN) = 0.97V, IQ = 2.5µA,
ISD < 1µA, MSOP-16E 3mm × 5mm QFN-24
LTC3863
60V, Low IQ Inverting DC/DC Controller
VIN(MIN) = 3.5V, VIN(MAX) = 60V, VOUT(MIN) = –150V, 3mm × 4mm
DFN-12, MSOP-12E
LT8611
42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA and Input/Output
Current Limit/Monitor
VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA,
ISD <1µA, 3mm × 5mm QFN-24
LT8612
42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 3.0µA,
ISD <1µA, 3mm × 6mm QFN-28
LT8614
42V, 4A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN(MIN) = 3.4V, VIN(MAX) = 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA,
ISD <1µA, 3mm × 4mm QFN-18
26 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC7149
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC7149
7149f
LT 0216 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2016