LT8714 Bipolar Output Synchronous Controller with Seamless Four Quadrant Operation DESCRIPTION FEATURES Bipolar Output Cleanly Transitions Through 0V nn Output Can Source or Sink Current for Any Output Voltage nn CTRL Pin Externally Sets Output Voltage nn Wide Input Range: 4.5V to 80V nn Power Good Indication Pin (PG) nn Switching Frequency Up to 750kHz nn Can Be Synchronized to an External Clock nn High Gain EN Pin Accepts Slowly Varying Input Signals nn 20-Lead TSSOP Exposed Pad Package The LT®8714 is a synchronous PWM DC/DC controller designed for a four quadrant output converter. The output voltage cleanly transitions through zero volts with sourcing and sinking output current capability. nn The LT8714 is ideal for regulating to positive, negative, or zero volts when configured for the novel four quadrant topology. Applications include four quadrant power supplies, high power bidirectional current sources, active loads, and high power, low frequency signal amplification. In addition, the LT8714 incorporates a power good feature to let the user know if VOUT is above or below its target regulation voltage. APPLICATIONS Four Quadrant Power Supplies Bidirectional Current Sources nn High Power, Low Frequency Signal Amplification nn Test and Measurement nn Electronic Window Tinting nn The LT8714’s switching frequency range can be programmed between 100kHz and 750kHz via a resistor from the RT pin to GND. A SYNC pin is also provided if the user would like to synchronize the part to an external clock. Additional features such as current limiting and soft-start are included. The LT8714 is available in a 20‑lead TSSOP package. nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending. TYPICAL APPLICATION 200kHz, –5V to 5V Output from a 10V to 14V Input 6mΩ ISN ISP 10µH • TG 22µF ×2 10µH VOUT –5V TO 5V ±5A MAX • VIN 10V TO 14V 22µF ×4 100µF ×4 2.5mΩ VCTRL 1V/DIV TG BG CSN CSP TG VIN 51.1k 2.2µF INTVCC 178k ISN ISP ISP VOUT 0V 5V/DIV 73.2k IL1 + IL2 10A/DIV VIN BIAS EN 10k ISN LT8714 VOUT Cleanly Transitions from –5V to 5V (VIN = 12V) 2.2µF 3.9ms/DIV INTVEE PG FB RT CTRL VC SYNC GND IMON VCTRL = SS 68nF 100pF 470nF 0A 4.75k 8714 TA01b 0.1V FOR –5VOUT 0.55V FOR 0VOUT 1.0V FOR 5VOUT 100nF 10nF 8714 TA01a 8714f For more information www.linear.com/LT8714 1 LT8714 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage.................................................. –0.3V to 80V BIAS Voltage............................................... –0.3V to 80V EN Voltage.................................................. –0.3V to 80V BG Voltage.............................................................Note 5 TG Voltage.............................................................Note 5 RT Voltage.................................................... –0.3V to 5V SS Voltage.................................................... –0.3V to 3V FB Voltage..................................................... –0.3V to 5V VC Voltage..................................................... –0.3V to 2V SYNC Voltage............................................. –0.3V to 5.5V PG Voltage.................................................... –0.3V to 7V PG Current.............................................................. ±1mA CTRL Voltage................................................ –0.3V to 5V INTVCC Voltage............................................. –0.3V to 7V INTVEE Voltage......................................................Note 5 CSP Voltage.................................................. –0.3V to 2V CSN Voltage.................................................. –0.3V to 2V ISP Voltage.................................. ISN – 0.4V to ISN + 2V ISN Voltage................................................. –0.3V to 80V IMON Voltage............................................. –0.3V to 2.5V Operating Junction Temperature Range LT8714E.............................................. –40°C to 125°C LT8714I............................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION TOP VIEW FB 1 20 GND VC 2 19 SYNC SS 3 18 RT PG 4 17 CTRL IMON 5 ISN 6 ISP 7 14 CSN BIAS 8 13 VIN INTVEE 9 12 INTVCC 21 GND TG 10 16 EN 15 CSP 11 BG FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8714EFE#PBF LT8714EFE#TRPBF LT8714FE 20-Lead Plastic TSSOP Exposed Pad –40°C to 125°C LT8714IFE#PBF LT8714IFE#TRPBF LT8714FE 20-Lead Plastic TSSOP Exposed Pad –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 8714f For more information www.linear.com/LT8714 LT8714 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN = 12V, VBIAS = 12V, unless otherwise noted (Note 2). PARAMETER CONDITIONS Minimum Operating Input Voltage MIN l Quiescent Current, IVIN Not Switching, VBIAS = 7.5V Quiescent Current in Shutdown VEN = 0V EN Chip Enable Thresholds TYP MAX UNITS 4.25 4.5 V 4 5.5 mA 0 1 μA EN Rising l 1.22 1.3 1.38 V EN Falling l 1.18 1.26 1.34 V EN Input Voltage Low Shutdown Mode l EN Pin Bias Current VEN = 3V EN Chip Enable Hysteresis 44 VEN = 1.3V VEN = 0V 7 mV 0.3 V 44 60 μA 12.7 15.2 μA 0 0.1 μA 10.1 13.8 μA mV SS Charge Current VSS = 50mV, Current Flowing Out of SS pin l SS Low Detection Voltage Part Exiting Undervoltage Lockout l 18 50 82 SS Voltage to Enable Switching SS Rising 0.75 1.0 1.21 SS Falling 0.65 0.92 1.15 SS Hysteresis 80 V V mV Low Dropout Regulators, IINTVCC and IINTVEE INTVCC Voltage IINTVCC = 10mA l 6.2 6.3 6.4 V INTVCC Undervoltage Lockout INTVCC Rising l 3.88 4 4.12 V INTVCC Falling l 3.5 3.73 3.95 INTVCC Undervoltage Lockout Hysteresis INTVCC Dropout Voltage VIN = 6V, IINTVCC = 10mA V 270 mV 255 mV INTVCC Load Regulation VIN = 12V, IINTVCC = 0mA to 80mA –0.44 –2 INTVCC Line Regulation 10V ≤ VIN ≤ 80V, IINTVCC = 10mA –0.005 –0.03 %/V 5 mA INTVCC Maximum External Load Current % INTVEE Voltage, VBIAS – VINTVEE IINTVEE = 10mA l 6.03 6.18 6.33 V INTVEE Undervoltage Lockout, VBIAS – VINTVEE VBIAS – VINTVEE Rising l 3.24 3.42 3.6 V VBIAS – VINTVEE Falling l 2.94 3.22 3.48 INTVEE Undervoltage Lockout Hysteresis, VBIAS – VINTVEE IINTVEE Dropout Voltage, VINTVEE VBIAS = 6V, IINTVEE = 10mA V 200 mV 0.75 V Control Loops (Refer to Block Diagram to Locate Amplifiers) Current Limit Voltage, VCSP – VCSN FB Regulation Voltage VFB = 1.4V, CTRL = 1.1V, Minimum Duty Cycle l 60.5 66 71.5 mV VFB = 1.4V, CTRL = 1.1V, Maximum Duty Cycle l 40 47 56 mV VFB = 0.1V, CTRL = 1.1V, Minimum Duty Cycle l –23 –32 –41 mV VFB = 0.1V, CTRL = 1.1V, Maximum Duty Cycle l –38 –51 –65 mV CTRL = 1.1V l 1.092 1.102 1.112 V CTRL = 0.1V l l 0.092 0.102 0.112 V 0 0.0167 0.033 V CTRL = 0V FB Pin Bias Current at FB Regulation. (Note 6) CTRL = 1.1V l 66.4 68.3 70.2 µA CTRL = 0.1V l l –67.7 –69.7 –71.7 µA –77.6 –81.6 –85 µA CTRL = 0V 8714f For more information www.linear.com/LT8714 3 LT8714 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN = 12V, VBIAS = 12V, unless otherwise noted (Note 2). PARAMETER CONDITIONS FB Internal Voltage, V1 IFB = 0.0μA FB Internal Resistance, R1 FB Amp Transconductance, EA1 MIN TYP MAX l 0.597 0.6065 0.616 l 7.1 7.25 7.4 ∆IVC = 2μA 200 FB Amp Voltage Gain, EA1 4.5V ≤ VIN ≤ 80V Output Current Sense Regulation Voltage, VISP – VISN VISN = 80V, VFB = 1.4V, CTRL = 1.1V VISN = 5V, VFB = 1.4V, CTRL = 1.1V IMON Regulation Voltage, EA2 VFB = 1V Output Current Sense Amp Transconductance, A7 ∆IIMON = 10μA V kΩ μmhos 108 FB Line Regulation UNITS V/V –0.02 –0.001 0.02 %/V l 46 50 54 mV l 46 50 54 mV l 1.184 1.208 1.233 Output Current Sense Amp Voltage Gain, A7 –55.5 V 1000 μmhos 12.14 V/V –49.5 –43.5 mV Output Current Sense Amp Input Dynamic Range, A7 Negative Input Range IMON Amp Transconductance, EA2 ∆IVC =2μA, VFB = 1.4V, CTRL=1.1V IMON Amp Voltage Gain, EA2 VISN = 12V, VFB = 1.4V, CTRL = 1.1V Valley Inductor Current Limit, VISP – VISN VISN = 80V l –220 –300 –380 mV VISN = 12V l –220 –300 –380 mV Switching Frequency, fOSC RT = 46.4k l 640 750 860 kHz RT = 357k l 85 100 115 kHz Switching Frequency Range Free-Running or Synchronizing l 100 750 kHz l 1.5 l Positive Input Range 500 mV 160 μmhos 70 V/V Oscillator SYNC High Level for Sync SYNC Low Level for Sync SYNC Clock Pulse Duty Cycle V l VSYNC = 0V to 3V 20 Recommended Min SYNC Ratio fSYNC/fOSC 0.4 V 80 % 3/4 Gate Drivers, BG and TG BG Rise Time CBG = 3300pF (Note 3) 24 ns BG Fall Time CBG = 3300pF (Note 3) 21 ns TG Rise Time CTG = 3300pF (Note 3) 15 ns TG Fall Time CTG = 3300pF (Note 3) 16 ns BG and TG Non-Overlap Time TG Rising to BG Rising, CBG = CTG = 3300pF (Note 3) 80 140 220 ns BG Falling to TG Falling, CBG = CTG = 3300pF (Note 3) 45 90 150 ns BG Minimum On-Time CBG = CTG = 3300pF 150 420 ns BG Minimum Off-Time CBG = CTG = 3300pF 100 480 ns TG Minimum On-Time CBG = CTG = 3300pF 0 150 ns TG Minimum Off-Time CBG = CTG = 3300pF 290 770 ns 4 8714f For more information www.linear.com/LT8714 LT8714 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN = 12V, VBIAS = 12V, unless otherwise noted (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Power Good Indicator, PG PG Overvoltage Threshold, VFB – CTRL PG Undervoltage Threshold, VFB – CTRL VFB Rising, 0.1V ≤ CTRL ≤ 1.1V l 75 114 155 mV VFB Falling, 0.1V ≤ CTRL ≤ 1.1V l 20 60 100 mV VFB Rising, 0.1V ≤ CTRL ≤ 1.1V l –100 –60 –20 mV VFB Falling, 0.1V ≤ CTRL ≤ 1.1V l –155 –114 –75 PG Power Good Hysteresis for Overvoltage or Undervoltage 54 PG Output Voltage Low 100µA into PG Pin, VFB = 1.4V, CTRL = 1.1V PG Leakage Current VPG = 7V, VFB = 1.1V, CTRL = 1.1V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8714E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LT8714I is guaranteed over the full –40°C to 125°C operating junction temperature range. l mV mV 9 50 mV 0.01 1 μA Note 3: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. Note 5: Do not apply a positive or negative voltage or current source to the BG, TG, and INTVEE pins, otherwise permanent damage may occur. Note 6: Negative FB current is defined as current flowing out of the FB pin. Positive FB current is defined as current flowing into the FB pin. 8714f For more information www.linear.com/LT8714 5 LT8714 TYPICAL PERFORMANCE CHARACTERISTICS Max Current Limit vs Temperature (CSP – CSN) Temperature (CSP – CSN) –25 60 –30 55 –35 50 –40 45 –45 40 –50 35 –55 fOSC = 300kHz –60 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 0 –26 70 –28 68 –30 66 –32 64 –34 62 –36 60 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 8714 G01 0 48 –8 40 –16 32 –24 24 –32 –40 16 8 –38 125 CTRL = 1.1V 1.0 –56 0 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 SS (V) 8714 G03 FB Offset Voltage vs Temperature (VFB – CTRL) 10 CTRL = 1.1V 60 0.9 8 40 0.7 FB CURRENT (µA) 0.8 CTRL = 0.6V 0.6 0.5 0.4 0.3 20 CTRL = 0.6V 0 –20 –40 0.2 CTRL = 0.1V 0.1 0 –50 –25 0 25 50 75 TEMPERATURE (°C) –60 100 –25 8714 G04 100 0 –2 –6 –50 125 607 606 605 604 100 125 8714 G07 CTRL = 1.1V CTRL = 0.6V CTRL = 0.1V –25 0 25 50 75 TEMPERATURE (°C) 100 FB Voltage vs CTRL Voltage CTRL Voltage 7.28 1.40 7.27 1.20 7.26 1.00 7.25 7.24 7.23 0.80 0.60 0.40 7.22 0.20 7.21 0.00 7.20 –50 –25 0 25 50 75 TEMPERATURE (°C) 125 8714 G06 FB VOLTAGE (V) FB INTERNAL RESISTANCE (kΩ) 608 0 25 50 75 TEMPERATURE (°C) 2 FB Internal Resistance vs Temperature 609 –25 4 8714 G05 FB Internal Voltage vs Temperature Temperature 603 –50 0 25 50 75 TEMPERATURE (°C) 6 –4 CTRL = 0.1V –80 –50 125 –48 fOSC = 300kHz DUTY = 50% 80 1.1 FB VOLTAGE (V) 56 FB Regulation Current vs Temperature 1.2 FB INTERNAL VOLTAGE (mV) 8 8714 G02 FB Regulation Voltage vs Temperature 6 64 FB OFFSET VOLTAGE (mV) 30 CURRENT LIMIT FOR (QIII, QIV) (mV) 65 72 CURRENT LIMIT (QI, QII) (mV) –20 Max Current Limit vs Soft-Start (CSP (CSP –– CSN) CSN) CURRENT LIMIT FOR (QI, QII) (mV) 70 CURRENT LIMIT FOR QI, QII (mV) CURRENT LIMIT (QIII, QIV) (mV) vs Duty(CSP Cycle (CSP – CSN) Cycle - CSN) CURRENT LIMIT (QIII, QIV) (mV) Max Current Limit TA = 25°C, unless otherwise noted. 100 125 8714 G08 –0.20 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 CTRL VOLTAGE (V) 1.2 1.4 8714 G09 8714f For more information www.linear.com/LT8714 LT8714 TYPICAL PERFORMANCE CHARACTERISTICS CTRL Pin Current vs CTRL Pin Voltage Voltage (ISP – ISN and IMON) vs Temperature 1.36 1.34 4 0 –4 AVERAGE ISP–ISN (mV) 8 1.32 RISING 1.30 1.28 1.26 FALLING 1.24 0.2 0.4 0.6 0.8 1.0 CTRL PIN VOLTAGE (V) 1.2 1.4 1.20 –50 –25 0 25 50 75 TEMPERATURE (°C) 8714 G10 Output Current Sense Regulation 1.20 45 1.15 40 1.10 35 1.05 100 125 –25 0 25 50 75 TEMPERATURE (°C) 1.00 1.1 Power Good Thresholds vs CTRL) vs Temperature Temperature (V(VFBFB– –CTRL) –290 100 –60 90 –70 80 –80 70 –90 –295 –300 –305 –100 60 VOUT FALLING –315 50 –320 –50 40 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 –25 0 25 50 75 TEMPERATURE (°C) 80 800 70 RT = 46.4kΩ 600 500 400 300 10 200 5 RT = 357kΩ 100 0.25 0.5 0.75 1 1.25 1.5 1.75 EN/FBIN VOLTAGE (V) 2 8714 G16 0 –50 –120 125 100 BG and TG Transition Time 900 700 25 –110 8714 G15 Oscillator Frequency vs Temperature 15 –40 VOUT RISING 8714 G14 20 1.194 125 100 –50 fOSC (kHz) EN/FBIN PIN CURRENT (µA) 47 –50 110 –40°C 25°C 125°C 0 1.198 QIII, QIV –285 EN Pin Current (0V to 2V) vs Temperature 0 1.202 120 8714 G13 30 49 –280 FB (V) 35 1.206 TRANSITION TIME (ns) 1.0 50 8714 G12 –310 0.9 1.210 OVERVOLTAGE (mV) 50 ISP–ISN (mV) 1.25 0.8 51 UNDERVOLTAGE (mV) 55 IMON (V) 1.30 0.7 1.214 Valley Current Limit Thresholds (ISP – ISN)(ISP-ISN) Threshold 60 30 0.6 52 8714 G11 Voltage vs FBIMON) (ISP – ISN and IMON) (ISP-ISN and CTRL = 0.6V QIII, QIV 1.218 48 1.22 –8 –0.2 0.0 53 IMON (V) EN THRESHOLD RISING (V) 12 CTRL PIN CURRENT (µA) Output Current Sense Regulation EN CHIP Threshold vs Temperature THRESHOLDS 16 AVERAGE ISP–ISN (mV) TA = 25°C, unless otherwise noted. BG RISING BG FALLING TG RISING TG FALLING 60 50 40 30 20 10 –25 0 25 50 75 TEMPERATURE (°C) 100 125 8714 G17 0 0 2 4 6 CAP LOAD (nF) 8 10 8714 G18 8714f For more information www.linear.com/LT8714 7 LT8714 TYPICAL PERFORMANCE CHARACTERISTICS Minimum Operating Input Voltage 4.35 6.40 INTVCC vs Temperature 4.2 IINTVCC = 10mA 4.33 4.31 TA = 25°C, unless otherwise noted. 4.1 6.36 4.25 4.23 6.32 INTVCC (V) INTVCC (V) VIN (V) 4.27 6.28 4.21 6.24 4.15 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 6.20 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 8714 G19 INTVCC Current Limit vs VIN 450 100 400 50 25 30 40 50 60 INPUT VOLTAGE (V) 70 80 300 200 6.20 6.16 6.12 0 10 20 30 40 50 60 70 INTVCC LOAD CURRENT (mA) 80 6.08 –50 BIAS - INTVEE = 5V FALLING 3.2 3.1 60 100 125 –40°C 25°C 125°C 1.0 45 INTVEE (V) INTVEE CURRENT LIMIT (mA) 3.3 25 50 75 0 TEMPERATURE (°C) INTVEE Dropout (BIAS = 6V) 1.2 1.1 3.4 –25 8714 G24 INTVEE Current Limit vs BIAS 75 RISING 3.0 –50 IINTVEE = 10mA 8714 G23 INTVEE UVLO vs Temperature 125 6.24 350 3.6 3.5 100 INTVEE vs Temperature 250 20 0 25 50 75 TEMPERATURE (°C) 6.28 BIAS - INTVEE (V) 125 75 –25 8714 G21 INTVCC Dropout INTVCC > 3.5V 10 3.5 –50 125 500 VIN – INTVCC (V) INTVCC CURRENT LIMIT (mA) FALLING 8714 G20 8714 G22 BIAS - INTVEE (V) 3.8 3.6 4.17 30 0.9 0.8 0.7 0.6 15 0.5 –25 25 50 75 0 TEMPERATURE (°C) 100 125 8714 G25 8 3.9 3.7 4.19 0 RISING 4.0 4.29 150 INTVCC UVLO vs Temperature 0 10 20 30 40 50 BIAS (V) 60 70 80 8714 G26 0.4 0 40 10 20 30 INTVEE LOAD CURRENT (mA) 50 8714 G27 8714f For more information www.linear.com/LT8714 LT8714 PIN FUNCTIONS FB (Pin 1): Feedback Pin. For the four quadrant converter, tie a resistor from the FB pin to VOUT according to the following equation: V –V RFB = 7250Ω • OUT CTRL VCTRL – 0.6065 VC (Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. SS (Pin 3): Soft-Start Pin. Place a soft-start capacitor here that is greater than 5× the IMON capacitor. Upon start-up, the SS pin will be charged by a (nominally) 260k resistor to ~2.7V. During an overtemperature or UVLO condition, the SS pin will be quickly discharged to reset the part. Once these conditions are clear, the part will attempt to restart. PG (Pin 4): Power Good Pin. The PG pin functions as an active high Power Good pin. Power is good when VFB is within ±60mV of VCTRL. A pull-up resistor or some other form of pull-up network is needed on this pin to use this feature. See the Block Diagram and Applications section for more information. IMON (Pin 5): Output Current Sense Monitor Output Pin. Outputs a voltage that is proportional to the voltage seen across the ISP and ISN pins. VIMON = 12.14 • (VISP – ISN + 49.9mV) Since the voltage across the ISP and ISN pins is AC, a filtering capacitor is needed on the IMON pin to average out the ISP and ISN voltage. Recommended capacitor values range from 10nF to 100nF. A 49.9mV offset is added to the amplifier, so when the average ISP – ISN voltage is 0V, the IMON voltage is 606mV. When the average voltage across the ISP and ISN pins is 50mV, the IMON pin will output 1.208V. Do not resistively load down this pin. ISN and ISP (Pins 6 and 7): Output Current Sense Negative and Positive Input Pins Respectively. Kelvin connect ISN and ISP pins to a sense resistor to limit the output current. The commanded NFET current will limit the voltage difference across the sense resistor to 50mV (typical). BIAS (Pin 8): Top Gate Driver Supply Pin. The BIAS pin sets the top rail for the TG gate driver. Connect this pin to the converter’s input voltage source VIN and bypass locally. INTVEE (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2µF to BIAS. This pin sets the bottom rail for the TG gate driver. The TG gate driver can begin switching when BIAS – INTVEE exceeds 3.42V (typical). TG (Pin 10): PFET Gate Drive Pin. Low and high levels are BIAS – INTVEE and BIAS respectively. BG (Pin 11): NFET Gate Drive Pin. Low and high levels are GND and INTVCC respectively. INTVCC (Pin 12): 6.3V Input LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2µF to GND. A maximum of 5mA external load can connect to the INTVCC pin. The undervoltage lockout on INTVCC is 4V (typical). The gate driver, BG, can begin switching when INTVCC exceeds 4V (typical). VIN (Pin 13): Input Supply Pin. Must be locally bypassed. The minimum voltage for the part to operate is 4.5V (typical). CSN and CSP (Pins 14 and 15): NFET Current Sense Negative and Positive Input Pins Respectively. Kelvin connect these pins to a sense resistor to limit the NFET switch current. The maximum positive sense voltage at low duty cycle is 66mV (typical). The maximum negative sense voltage at low duty cycles is –32mV (typical). 8714f For more information www.linear.com/LT8714 9 LT8714 PIN FUNCTIONS EN (Pin 16): Enable Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/ disable the chip and restart the soft-start sequence. Drive below 0.3V to disable the chip with very low quiescent current. Drive above 1.3V (typical) to activate the chip and restart the soft-start sequence. See the Block Diagram and Applications section for more information. Do not float this pin. CTRL (Pin 17): Output Voltage Control Pin. The CTRL pin sets the regulation voltage for VFB. The CTRL pin accepts voltages from 0.1 to 1.1V. In the event that the CTRL pin is driven above 1.213V, the voltage at FB regulates to ≈1.213V. Likewise, if the CTRL pin is driven below 0V, the voltage at FB regulates to ≈0V. 10 RT (Pin 18): Timing Resistor Pin. Adjusts the LT8714’s switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free-running level. Do not float this pin. SYNC (Pin 19): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must be between 1.5V and 5V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free-running clock. See the Applications Information section for more information. GND (Pin 20 and Exposed Pad Pin 21): Ground. Must be soldered directly to local ground plane. 8714f For more information www.linear.com/LT8714 LT8714 BLOCK DIAGRAM RSENSE2 ISN ISP • CIN C1 TG L1 L2 • VIN MP VOUT COUT MN RSENSE1 TG CSP VIN BG CSN BIAS INTVCC DRIVER SWEN SR1 INTVCC 1.213V REFERENCE UVLO ISP ISN PG Q R S + A7 + CVCC SWEN INTVEE BIAS – 6.18V UVLO VIN CVEE LDO – 6.3V – +A5 BIAS TG DRIVER LEVEL SHIFT TG DRIVER DISABLE LDO RFB CTRL + 60mV – + 1.3V – – – DIE TEMP 175°C 7.25k + – SLOPE COMPENSATION SWEN EA1 ADJUSTABLE OSCILLATOR CSS GND 260k START-UP AND RESET LOGIC CTRL – SYNC BLOCK SS SOFT-START + + SS + – DRIVER DISABLE EA2 1.208V A6 – 2.7V 50mV 10.2k – – V1 606.5mV + + FB – 1.0V CTRL – 60mV R1 12.14k SYNC RT VC CC 1.213V ISN +– ISP 49.9mV IMON RC RT + 51.4k RIN2 + + – EN + RIN1 8714 BD CF CIMON 8714f For more information www.linear.com/LT8714 11 LT8714 STATE DIAGRAM EN < 1.3V (TYP) OR VIN < 4.5V (MAX) CHIP OFF • ALL SWITCHES DISABLED EN > 1.3V (TYP) AND VIN > 4.5V INITIALIZE • SS PULLED LOW • INTVCC CHARGES UP RESET EN > 1.3V AND VIN > 4.5V AND INTVCC > 4V (TYP) ACTIVE MODE • SS SLOWLY CHARGES UP • VC PULLED LOW RESET RESET DETECTED • SS DISCHARGES QUICKLY • SWITCHER DISABLED SOFT-START • SS MUST EXCEED 1.0V (TYP) FOR SWITCHING TO BEGIN SS < 50mV RESET RESET OVER • NO RESET CONDITIONS DETECTED SS > 1.0V (TYP) NORMAL OPERATION • BG AND TG SWITCH AT CONSTANT FREQUENCY • INDUCTOR CURRENT CAN REVERSE • IF ISP – ISN VOLTAGE GOES BELOW –300mV (TYP), PFET TURNS OFF SO INDUCTOR CURRENT GOES MORE POSITIVE REGULATION • VC COMMANDS PEAK INDUCTOR CURRENT TO MAINTAIN REGULATION RESET RESET RESET 8714 SD REGULATION = OUTPUT VOLTAGE (FB) OUTPUT CURRENT (ISP-ISN AND IMON) RESET = UVLO ON VIN ( < 4.5V (MAX)) UVLO ON INTVCC ( < 4V (TYP)) EN < 1.3V (TYP) OVERTEMPERATURE (TJ > 175°C (TYP)) 12 8714f For more information www.linear.com/LT8714 LT8714 OPERATION OPERATION – FOUR QUADRANT OVERVIEW Four quadrant operation means that a device can operate as a power source and as a load irrespective of the voltage polarity. To illustrate this concept, please refer to Figures 1 and 2. IOUT II LOAD VOUT IS LIMITED TO VIN I SOURCE VIN VOUT IV LOAD III SOURCE 8714 F01 From the graph and current flow diagrams, we can have positive output voltage and positive output current, positive output voltage and negative output current, negative output voltage and positive output current, and negative output voltage and negative output current. Quadrants I and III transfer power from VIN to VOUT. Quadrants II and IV transfer power from VOUT back to VIN. The maximum positive output voltage of the four quadrant converter is limited to VIN. OPERATION – LT8714 OVERVIEW The LT8714 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation for the four quadrant converter. The part’s undervoltage lockout (UVLO) function and soft-start provide a controlled start up sequence. In addition, synchronous switching makes high efficiency and high output current applications possible. Please refer to the Block Diagram and the State Diagram for the following description of the part’s operation. CAN REGULATE TO 0V WITH CURRENT DRIVE Figure 1. Four Quadrant Operation Overview L1 C1 COUT CIN L1 VIN IIN L1 C1 +VOUT +IOUT COUT b) QUADRANT I L1 VIN IIN C1 +VOUT –IOUT COUT CIN c) QUADRANT III L2 • –VOUT –IOUT • • • L2 COUT CIN L2 CIN a) QUADRANT II VIN IIN C1 • –VOUT +IOUT • L2 • • VIN IIN d) QUADRANT IV 8714 F02 Figure 2. Four Quadrant Topology Current Flow 8714f For more information www.linear.com/LT8714 13 LT8714 OPERATION OPERATION – START-UP Several functions are provided to enable a very clean start-up of the LT8714. Precise Turn-On Voltage The EN pin has a single voltage level for enabling the internal rails to operate the part. To activate a soft-start cycle and allow switching to commence, take the EN pin above 1.3V (typical). This comparator has 44mV of hysteresis to protect against glitches and slow ramping. Taking the EN pin below 0.3V shuts down the chip, resulting in extremely low quiescent current. See Figure 3 below that illustrates the different chip modes for different EN pin voltages. ACTIVE MODE (NORMAL OPERATION) 1.38V CHIP ENABLE THRESHOLD (HYSTERSIS AND TOLERANCE) 1.18V EN (V) LOCKOUT (SWITCH OFF, SS CAP DISCHARGED, INTVCC AND INTVEE DISABLED) 0.3V SHUTDOWN (LOW QUIESCENT CURRENT) 0V 8714 F03 Figure 3. Chip EN Thresholds Undervoltage-Lockout (UVLO) The LT8714 has internal UVLO circuitry that disables the chip when VIN < 4.5V (max) or INTVCC < 4V (typical). The EN pin can also be used to create a configurable UVLO. See the Applications section for more information. Soft-Start of Switch Current The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Commanded Switch Current vs. SS in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Once INTVCC comes out of UVLO (> 4V typical) and the chip is in active mode, an integrated 260k resistor pulls the SS pin to ~2.7V at a ramp rate set by the external capacitor connected to the 14 pin. Typical values for the soft-start capacitor range from 100nF to 1µF. The soft-start capacitor should also be at least 5× greater than the external capacitor connected to the IMON pin to avoid start-up issues. OPERATION – REGULATION Use the Block Diagram when stepping through the following description of the LT8714 operating in regulation. The LT8714 has 2 modes of regulation: 1.Output Voltage (via FB pin) 2.Output Current (via ISP, ISN, and IMON pins) Both of these regulation loops control the peak commanded current through the external NFET, MN. The output current regulation loop, however, regulates the peak NFET current in Quadrants III and IV. At the start of each oscillator cycle, the SR latch (SR1) is set, which first turns off the external PFET, MP, and then turns on the external NFET, MN. The NFET’s source current flows through an external current sense resistor (RSENSE1) generating a voltage proportional to the NFET switch current. This voltage is then amplified by A5 and added to a stabilizing ramp. The resulting sum is fed into the positive terminal of the PWM comparator A7. When the voltage on the positive input of A7 exceeds the voltage on the negative input (VC pin), the SR latch is reset, turning off the NFET and then turning on the PFET. The voltage on the VC pin is controlled by one or both regulation loops. For simplicity, each mode of regulation will be described independently so that only one of the modes of regulation is in command of the LT8714. Output Voltage Regulation A single external resistor is used to set the target output voltage. See the Pin Functions section for selecting the feedback resistor for a desired output voltage. The VC pin voltage (negative input of A7) is set by EA1, which is simply an amplified difference between the FB pin voltage and the CTRL pin voltage. In this manner, the error amplifier sets the correct peak current level to maintain output voltage regulation. 8714f For more information www.linear.com/LT8714 LT8714 OPERATION Output Current Regulation (Quadrants III and IV) OPERATION – POWER SWITCH CONTROL An external sense resistor connected between the ISP and ISN pins (RSENSE2) sets the maximum sinking output current of the converter when placed in the source of the PFET, MP. A built-in 49.9mV offset is added to the voltage seen across RSENSE2. The offset voltage and the sensed voltage are then amplified and is output to the IMON pin. An external capacitor must be placed from IMON to ground to filter the amplified chopped voltage that’s sensed across RSENSE2. The voltage at the IMON pin is fed into the negative input of the IMON error amplifier, EA3. The VC pin voltage is set by EA3, which is simply an amplified difference between the IMON pin voltage and the 1.208V reference voltage. In this manner, the IMON error amplifier sets the correct peak current level to maintain output sinking current regulation. The main power switch is the external NFET (MN in Block Diagram) and the synchronous power switch is the external PFET (MP in Block Diagram). A non-overlap time of ~140ns and ~90ns on the rising and falling edges respectively is added (see Electrical Characteristics) to prevent cross conduction. Figure 4 shows the BG and TG (BIAS – TG) signals. The LT8714 has 2 reset cases. When the part is in reset, the SS pin is pulled low and both power switches, MN and MP, are forced off. Once all of the reset conditions are gone, the part is allowed to begin a soft-start sequence and switching can commence. Each of the following events can cause the LT8714 to be in reset: a. VIN is < 4.5V (maximum) b. INTVCC < 4V (typical) 2. Die Temperature > 175°C 90ns BG ON TG ON 8714 F04 Figure 4. Synchronous Switching OPERATION – POWER GOOD (PG PIN) OPERATION – RESET CONDITIONS 1. UVLO 140ns The PG pin is an open-drain pin that functions as an active high Power Good pin. Power is good when the FB voltage is within ±60mV of the CTRL pin voltage. The PG comparators have 54mV of hysteresis to reject glitches. OPERATION – LDO REGULATORS (INTVCC AND INTVEE) The INTVCC LDO regulates to 6.3V (typical) and is used as the top rail for the BG gate driver. The INTVCC regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from damage if the pin is shorted to ground. The UVLO threshold on INTVCC is 4V (typical), and the LT8714 will be in reset until the LDO comes out of UVLO. The INTVEE regulator regulates to 6.18V (typical) below the BIAS pin voltage. The BIAS and INTVEE voltages are used for the top and bottom rails of the TG gate driver respectively. Just like the INTVCC regulator, the INTVEE regulator has a safety feature to limit the power dissipation in the internal pass device. 8714f For more information www.linear.com/LT8714 15 LT8714 APPLICATIONS INFORMATION FOUR QUADRANT CONVERTER COMPONENT SELECTION Table 1. Four Quadrant Converter Design Equations Parameters/Equations RSENSE2 6mΩ ISP L1 10µH TG CIN 22µF ×4 C1 22µF ×2 L2 10µH MN COUT 100µF ×4 RSENSE1 2.5mΩ BG CSN TG CSP VIN RIN1 51.1k EN RIN2 10k VOUT –5V TO 5V ±5A • • ISN VIN 10V TO 14V MP ISN ISP ISP 73.2k INTVCC VCTRL 0.1V TO 1V VIN BIAS 2.2µF INTVEE VC PG RT SYNC GND IMON SS 68nF Pick VIN, VOUT, IOUT, and f to calculate equations below. Step 2: DCMAX DCMAX = Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. Step 4: RSENSE1 RSENSE1+ = 0.63 • VIN(MIN) – VOUT(NEG) 2VIN(MIN) – VOUT(NEG) RSENSE1 – = 0.63 • CTRL 100k 178k ISN FB LT8714 2.2µF TG Step 1: Inputs 100pF 470nF 4.75k 10nF Step 5: RSENSE2 RSENSE2 = Step 6: L L TYP = Figure 5. Four Quadrant Converter—The Component Values Given are Typical Values for a 200kHz, –5V to 5V/±5A Output from a 10V to 14V Input Variable Definitions: VIN(MIN) = Minimum Input Voltage VIN(MAX) = Maximum Input Voltage VOUT(POS) = Max Positive Output Voltage VOUT(NEG) = Max Negative Output Voltage IOUT = Output Current of Converter ƒ = Switching Frequency DCMAX = Duty Cycle at VIN(MIN) and VOUT(NEG) DCMIN = Duty Cycle at VIN(MIN) and VOUT(POS) VCSPN+ = Current Limit Voltage at DCMAX VCSPN– = Current Limit Voltage at DCMIN 16 IOUT VCSPN – IOUT VIN(MIN) – VOUT(POS) 2VIN(MIN) – VOUT(POS) •(1 – DCMAX ) •(1 – DCMIN) RSENSE1 =MIN (RSENSE1+ , RSENSE1– ) 50m 1.6 • IOUT R SENSE1 • VIN(MIN) 12.5m • ƒ 8714 F05 For a desired output current and output voltage over a given input voltage range, Table 1 is a step-by-step set of equations to calculate component values for the LT8714 when operating as a four quadrant power supply. Refer to the Appendix section for further information on the design equations presented in Table 1. VCSPN+ , DCMIN = L MIN = – L MAX = • DCMAX R SENSE1 • VOUT(NEG) 40m • ƒ • DCMAX R SENSE1 • VIN(MI N) 3m • ƒ • DCMIN (1) (2) (3) • Solve equations 1, 2 and 3 for a range of L values. • The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX. • L = L1 = L2 for coupled inductors • L = L1 || L2 for uncoupled inductors Step 7: C1 (Note 2) Step 8: COUT C1 ≥ IOUT 0.05 • VIN(MIN) • DCMAX ,VRATING > VIN + | VOUT | ƒ 4 • VIN(MAX) COUT ≥ 8 •L • ƒ 2 • 0.005 • VOUT(NEG) Step 9: CIN CIN ≥ Step 10: CIMON CIMON ≥ Step 11: RFB RFB = 7250Ω • V IN(MAX) – VOUT(NEG) • 2 • VIN(MAX) – VOUT(NEG) IOUT •DCMAX 0.005 • VIN(MIN) • ƒ Step 12: RT 100µA • DCMAX 0.005• ƒ VOUT – VCTRL VCTRL – 0.6065 35,880 RT = – 1; ƒ in kHz and R T in kΩ + 83.7µA •RFB ƒV VCTRL = OUT (1 for + RCFBOUT / 7.25k) NOTE 1: The final values and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. NOTE 2: See the Appendix section for sizing C1 when using single inductors. 8714f For more information www.linear.com/LT8714 LT8714 APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE REGULATION VIN VIN The LT8714 output voltage is set by connecting an external resistor (RFB) from the converter’s output, VOUT, to the FB pin. The equation below determines RFB: RFB = 7250Ω • RIN1 EN 1.3V EN LOGIC ACTIVE MODE CHIP ENABLE 12.7µA AT 1.3V VOUT – VCTRL VCTRL – 0.6065 RIN2 (OPTIONAL) 51.4k GND VCTRL = VOUT + 83.7µA •RFB (1 + RFB / 7.25k) 8714 F06 Figure 6. Enable Threshold To set the output voltage, follow the three steps listed in the order below: SETTING THE MINIMUM START-UP VOLTAGE 1.Select the highest magnitude VOUT voltage (positive or negative) for the application. By connecting a resistor divider between VIN, EN, and GND, a minimum input startup voltage can be set. To set the minimum input voltage, use Figure 6 as a guide. 2.Select the desired CTRL pin voltage (0.1V to 1.1V) for the highest magnitude VOUT voltage. 3.Substitute the selected VOUT voltage and CTRL pin voltage into the equation above to size RFB. (Note that for negative values of RFB, the selected CTRL voltage needs to be reduced). The resistor RIN2 is optional, but it is recommended to increase the accuracy of the enable threshold. For increased accuracy, set RIN2 ≤ 10kΩ. To size RIN1 for a desired start up voltage, use the following equation below: Example 1: 10V to 14V Input → –5V to 5V Output 1.VOUT = –5V. 2.For negative output voltages, CTRL < 0.6065. Select CTRL = 0.1V. –5V – 0.1V = 73k; use 73.2k 3. RFB = 7250Ω • 0.1V – 0.6065V 4. VCTRL = 5 + 83.7µA • 73.2k = 1.003V for VOUT = 5V (1 + 73.2k/7.25k) Example 2: 10V to 14V Input → –1V to 6V Output 1.VOUT = 6V. 2.For positive output voltages, CTRL > 0.6065. Select CTRL = 1.1V. 6V – 1.1V = 72k; use 73.2k 3. RFB = 7250Ω • 1.1V – 0.6065V OUTPUT CURRENT MONITORING AND LIMITING (RSENSE2 AND ISP – ISN AND IMON PINS) The LT8714 has an output current monitor circuit that can be used to monitor and/or limit output current in Quadrants III and IV, but not in I or II. The current monitor circuit works as shown in Figure 7. If it is not desirable to monitor and limit the output current, simply connect the IMON pin to ground, tie ISP and ISN to VIN, and remove RSENSE2. The current through RSENSE2 is sensing the current through MP which is turning on and off every clock cycle. Since the current through RSENSE2 is chopped, a filter capacitor connected from the IMON pin to ground is needed to filter the voltage at the IMON pin before heading to EA3. Below is the equation to calculate the required IMON pin capacitor. –1 + 83.7µA • 73.2k = 0.462V for VOUT = – 1V 4. VCTRL = (1 + 73.2k/7.25k) R VIN_START-UP = 12.7µA • RIN1 +1.3V 1+ IN1 RIN2 CIMON > 100µA •DC 5mV • ƒ where DC is the duty cycle of the converter’s application, and f is the switching frequency. To prevent start-up issues, 8714f For more information www.linear.com/LT8714 17 LT8714 APPLICATIONS INFORMATION RSENSE2 MP TG As shown in Figure 7, IMON voltages exceeding 1.208V (typical) causes the VC voltage to reduce, thus limiting the inductor current. This voltage on IMON corresponds to an average voltage of 50mV across RSENSE2. Below is the equation for selecting the RSENSE2 resistor for limiting the sinking output current for Quadrants III and IV in steady state: ISN ISP – – + + 49.9mV Output Current Limiting (Quadrants III and IV) TO SYSTEM VIN 1mA/V A8 1.208V + EA2 – 12.14k GND VC IMON CIMON Figure 7. Output Current Monitor and Control the IMON capacitor should charge up faster than the SS capacitor. It is recommended to size the SS capacitor at least 5× greater than the IMON capacitor. Output Current Monitoring The voltage at the IMON pin is an amplified version of the voltage seen across the ISP and ISN pins. Below are the equations relating the RSENSE2 current to the IMON pin voltage. Assume the current through RSENSE2 is steady state and that its time average current is approximately equal to the converter’s sinking output current: VIMON =12.14 • (IRSENSE2(AVE) •R SENSE2 + 49.9mV ) 18 50mV IOUT(LIMIT) If it is not desirable to limit the output current in Quadrants III and IV, size RSENSE2 by setting IOUT(LIMIT) ~60% higher than the maximum output current of the converter. SWITCH CURRENT LIMIT (RSENSE1 AND CSP – CSN PINS) 8714 F07 VIMON – 49.9mV 12.14 IOUT ≈IRSENSE2(AVE) = RSENSE2 R SENSE2 = The external current sense resistor (RSENSE1) sets the maximum peak current though the external NFET switch (MN). The maximum voltage across RSENSE1 is 66mV (typical) and minimum voltage is –32mV at very low switch duty cycles. The use of internal slope-compensation decreases the current limit as the duty cycle increases (see the Max Current Limit vs. Duty Cycle (CSP – CSN) plot in the Typical Performance Characteristics). The equations below give the positive and negative switch current limits for a given duty cycle and current sense resistor (find VCSPN+ and VCSPN– in the operating duty cycle in the plot mentioned): ISW + = VCSPN + RSENSE1 ISW – = VCSPN – RSENSE1 To provide a desired load current for any given application, RSENSE1 must be sized appropriately. The switch current will be at its highest when the input voltage is at the lowest 8714f For more information www.linear.com/LT8714 LT8714 APPLICATIONS INFORMATION of its range. The equations below calculates RSENSE1 for four quadrant operation: RSENSE1+ i 0.74 • VCSPN + • 1 – RIPPLE 2 = IOUT | VOUT • IOUT | 1 • – 1 1 – DC + VIN η RSENSE1– i 0.74 • VCSPN– • 1 – RIPPLE 2 = IOUT | VOUT • IOUT | 1 • – 1 1 – DC + VIN η 5.1Ω RSENSE1, RSENSE2 5.1Ω CSP OR ISP 2.2nF LT8714 CSN OR ISN 8714 F08 Figure 8. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins 5.1Ω CSP OR ISP 4.7nF LT8714 RSENSE1, RSENSE2 4.7nF 5.1Ω CSN OR ISN 8714 F09 where: η = Converter Efficiency (assume ~90% for Quadrants I and IV and ~80% for Quadrants II and III) VCSPN+ = Max Positive Current Limit Voltage (see Max Current Limit vs. Duty Cycle (CSP – CSN) plot in the Typical Performance Characteristics) VCSPN– = Max Negative Current Limit Voltage (see Max Current Limit vs. Duty Cycle (CSP – CSN) plot in the Typical Performance Characteristics) IOUT = Converter Output Current DCMAX = Switching Duty Cycle at Minimum VIN and most negative VOUT DCMIN = Switching Duty Cycle at Minimum VIN and most positive VOUT iRIPPLE = Peak-to-Peak Inductor Ripple Current Percentage at Minimum VIN (recommended to use 25%) CURRENT SENSE FILTERING Certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across RSENSE1 and/or RSENSE2. Higher operating voltages, higher values of RSENSE, and more capacitive MOSFETs will all contribute additional noise across RSENSE when MOSFETs transition. The CSP/CSN and/or the ISP/ISN sense signals can be filtered by adding one of the RC networks shown below in Figures 8 and 9. Figure 9. Differential and Common Mode RC Filter on CSP/CSN and/or ISP/ISN Pins The filter shown in Figure 8 filters out differential noise, whereas the filter in Figure 9 filters out the differential and common mode noise at the expense of an additional capacitor and approximately twice the capacitance value. It is recommended to Kelvin the ground connection directly to the paddle of the LT8714 if using the filter in Figure 9. The filter network should be placed as close as possible to the LT8714. Resistors greater than 10Ω should be avoided as this can increase the offset voltages at the CSP/CSN and ISP/ISN pins. The RC product should be kept less than 30ns, which is simply the total series R (5.1Ω + 5.1Ω in this case) times the equivalent capacitance seen across the sense pins (2.2nF for Figure 8 and 2.35nF for Figure 9). SWITCHING FREQUENCY The LT8714 uses a constant frequency architecture between 100kHz and 750kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. The switching frequency can be set by placing an 8714f For more information www.linear.com/LT8714 19 LT8714 APPLICATIONS INFORMATION appropriate resistor from the RT pin to ground and tying the SYNC pin low. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following sections provide more details. Oscillator Timing Resistor (RT) The operating frequency of the LT8714 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. The oscillator frequency is calculated using the following formula: ƒ= 35,880 (RT +1) where f is in kHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in kHz) using: RT = 35,880 –1 ƒ Clock Synchronization An external source can set the operating frequency of the LT8714 by providing a digital clock signal into the SYNC pin (RT resistor still required). The LT8714 will operate at the SYNC clock frequency. The LT8714 will revert to its internal free-running oscillator clock when the SYNC pin is driven below 0.4V for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT8714 will stop. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1.SYNC may not toggle outside the frequency range of 100kHz to 750kHz unless it is stopped below 0.4V to enable the free-running oscillator. 2.The SYNC frequency can always be higher than the freerunning oscillator frequency (as set by the RT resistor), fOSC, but should not be less than 25% below fOSC. 20 After SYNC begins toggling, it is recommended that switching activity is stopped before the SYNC pin stops toggling. Excess negative inductor current can result when SYNC stops toggling as the LT8714 transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving the EN pin low. LDO REGULATORS The LT8714 has two linear regulators to run the BG and TG gate drivers. The INTVCC LDO regulates 6.3V (typical) above ground, and the INTVEE regulator regulates 6.18V (typical) below the BIAS pin. INTVCC LDO Regulator The INTVCC LDO is used as the top rail for the BG gate driver. An external capacitor greater than 2.2µF must be placed from the INTVCC pin to ground. The UVLO threshold on INTVCC is 4V (typical), and the LT8714 will be in reset until the LDO comes out of UVLO. Overcurrent protection circuitry typically limits the maximum current draw from the LDO to 125mA. When INTVCC is below ~3.5V during start-up or an overload condition, the typical current limit is reduced to 25mA. If VIN is greater than 20V (typical), then the current limit of the LDO reduces linearly with VIN to limit the maximum power in the INTVCC pass device. See the INTVCC Current Limit vs. VIN plot in the Typical Performance Characteristics. If the die temperature exceeds 175°C (typical), the current limit of the LDO drops to 0. Power dissipated in the INTVCC LDO should be minimized to improve efficiency and prevent overheating of the LT8714. The current limit reduction with input voltage circuit helps prevent the part from overheating, but these guidelines should be followed. The maximum current drawn through the INTVCC LDO occurs under the following conditions: 1.Large (capacitive) MOSFETs being driven at high frequencies. 2.The converter’s switch voltage (2•VIN – VOUT) is high, thus requiring more charge to turn the MOSFET gates on and off. 8714f For more information www.linear.com/LT8714 LT8714 APPLICATIONS INFORMATION In general, use appropriately sized MOSFETs and lower the switching frequency for higher voltage applications to keep the INTVCC current at a minimum. INTVEE LDO Regulator The BIAS and INTVEE voltages are used for the top and bottom rails of the TG gate driver respectively. An external capacitor greater than 2.2µF must be placed between the BIAS and INTVEE pins. The TG pin can begin switching after the INTVEE regulator comes out of UVLO. Overcurrent protection circuitry typically limits the maximum current draw from the regulator to 65mA. If BIAS is greater than 20V (typical), then the current limit of the regulator reduces linearly with BIAS to limit the maximum power in the INTVEE pass device. See the INTVEE Current Limit vs. BIAS plot in the Typical Performance Characteristics. Four Quadrant Topology Specific Layout Guidelines Keep the length of high speed switching path governing CIN, RSENSE1, MN, C1, MP, RSENSE2, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. C1 L2 MP L1 MN RSENSE2 VIN GND n n n n n To optimize thermal performance, solder the exposed pad of the LT8714 to the ground plane with multiple vias around the pad connecting to additional ground planes. High speed switching path (see specific topology below for more information) must be kept as short as possible. The FB, VC, IMON, and RT components should be placed as close to the LT8714 as possible, while being far away as practically possible from switching nodes. The ground for these components should be separated from the switch current path. 8714 F10 Figure 10: Suggested Component Placement for the Four Quadrant Converter Current Sense Resistor Layout Guidelines n n Route the CSP/CSN and ISP/ISN lines differentially (close together) from the chip to the current sense resistor as shown in Figure 11. For the most accurate current sensing, make an inner cut out in the sense resistor foot print so that the kelvin connection does not introduce any additional offset on the CSP – CSN or ISP – ISN pins. RSENSE1, 2 Place bypass capacitors for the VIN and BIAS pins (CVIN and CBIAS) as close as possible to the LT8714. Place bypass capacitors for the INTVCC and INTVEE pins (CVCC and CVEE) as close as possible to the LT8714. The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. GND COUT LT8714 CIRCUIT LAYOUT GUIDELINES FOR THE FOUR QUADRANT CONVERTER n VOUT RSENSE1 The same thermal guidelines from the INTVCC LDO Regulator section apply to the INTVEE regulator as well. General Layout Guidelines CIN TO CURRENT SENSE PINS 8714 F11 Figure 11: Suggested Routing and Connections of CSP/CSN and ISP/ISN Lines 8714f For more information www.linear.com/LT8714 21 LT8714 APPLICATIONS INFORMATION THERMAL CONSIDERATIONS Overview The primary components on the board that dissipate the most power and produce the most heat are the power switches, MN and MP, the power inductor, sense resistors, and the LT8714 IC. It is imperative that a good thermal path be provided for these components to dissipate the heat generated within the packages. This can be accomplished by taking advantage of the thermal pads on the underside of the packages. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from each of these components and into a copper plane with as much area as possible. For the case of the power switches, the copper area of the drain connections shouldn’t be too big as to create a large EMI surface that can radiate noise around the board. Power MOSFET Loss and Thermal Calculations The LT8714 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. Important parameters for estimating the power dissipation in the MOSFETs are: inductor current flows through the body diode of either the NFET or PFET, depending on the polarity of IOUT. Below are the equations for the power loss in MN and MP. For Quadrants I and II: PMOSFET =PI2R +PSWITCHING PMP =IP 2 •RDSON + VDS •IP • ƒ • tRF I PMN =IN 2 •RDSON +VBD• PK + IVY • ƒ •140ns 1.6 iRIPPLE iRIPPLE ; IVY =ISW – IPK =ISW + 2 2 2 i IN = DC • ISW2 + RIPPLE 12 2 i IP = (1–DC)• ISW2 + RIPPLE 12 PRR – N ≈ VDS •QRR-N • ƒ For Quadrants III and IV: PMOSFET =PI2R +PSWITCHING PMN =IN2 •RDSON + VDS •IN • ƒ • tRF I PMP =IP2 •RDSON +VBD• PK + IVY • ƒ • 140ns 1.6 iRIPPLE iRIPPLE ; IVY =ISW – IPK =ISW + 2 2 2 i IN = DC • ISW2 + RIPPLE 12 2 i IP = (1–DC)• ISW2 + RIPPLE 12 PRR – P ≈ VDS •QRR-P • ƒ 1.On-Resistance (RDSON) 2.Gate-to-Drain Charge (QGD) 3.Body Diode Forward Voltage (VBD) 4.VDS of the FETs during their “Off-Time” 5.Switch Current (ISW) 6.Switching Frequency (ƒ) The power loss in each power switch has a DC and AC term. The DC term is when the power switch is fully on, and the AC term is when the power switch is transitioning from on-off or off-on. The following applies for both the NFET and PFET power switches. For the four quadrant topology, the average current through each MOSFET (ISW) during its on-time is: I |V •I | ISW ≈ OUT + OUT OUT (1–DC) 4VIN where: ƒ = Switching Frequency IN = NFET RMS Current IP = PFET RMS Current The |VDS| voltage during the off-time is approximately 2VIN – VOUT. During the non-overlap time of the gate drivers, the 22 tRF = Average of the rise and fall times of the NFET’s drain voltage 8714f For more information www.linear.com/LT8714 LT8714 APPLICATIONS INFORMATION IPK = Peak inductor current for both the BG and TG gate drivers. Below are the chip power equations for the four quadrant converter: IVY = Valley inductor current iRIPPLE = Inductor ripple current DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) VBD = NFET or PFET body diode forward voltage at PVCC = 1.04 • QMN • f • VIN PVEE1 = QMP • ƒ • VIN PVEE2 = 3.15mA • (1 – DC) • VIN PQ = 4mA • VIN where: ISW = Switch current in the NFET or PFET Switching frequency ƒ= PRR-N = NFET body diode reverse recovery power loss PRR-P=PFET body diode reverse recovery power loss Switch duty cycle (see Power Switch Duty Cycle DC= section in Appendix) QRR-N = Reverse recovery charge stored in the junction capacitance of the NFET body diode QMN=Total gate charge of NFET power switch (MN) at 6.3VGS QRR-P = Reverse recovery charge stored in the junction capacitance of the PFET body diode QMP=Total gate charge of PFET power switch (MP) at 6.18VSG Typical values for tRF are 10 to 40ns depending upon the MOSFET capacitance and drain voltage. In general, the lower the QGD of the MOSFET, the faster the rise and fall times of its drain voltage. For best calculations, measure the rise and fall times in the application. Body diode reverse recovery power loss is dependent on many factors and can be difficult to quantify in an application. In general, this power loss is split between the NFET and PFET by a ratio and increases with higher VDS and/or higher switching frequency. Chip Power and Thermal Calculations Power dissipation in the LT8714 chip comes from three primary sources: INTVCC and INTVEE LDOs providing gate drive to the BG and TG pins and additional input quiescent current. The average current through each LDO is determined by the gate charge of the power switches, MN and MP, and the switching frequency. Below are the equations for calculating the chip power loss followed by an example. For the four quadrant converter, BIAS is always tied to VIN, so all of the chip power comes from VIN. VIN primarily supplies the chip Q current, and power Chip Power Calculations Example Table 2 calculates the power dissipation of the LT8714 for a 200kHz, 10V to 14V to ±5V/±5A application when VIN is 12V. From PCHIP in Table 2, the die junction temperature can be calculated using the appropriate thermal resistance and worst-case ambient temperature: TJ = TA + θJA • PCHIP where TJ = die junction temperature, TA = ambient temperature and θJA is the thermal resistance from the silicon junction to the ambient air. The published θJA value is 38°C/W for the TSSOP Exposed Pad package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section. For instance, a θJA value of ~22°C/W was consistently achieved when board layout was optimized as per the suggestions in the Layout Guidelines section. THERMAL LOCKOUT If the die temperature reaches ~175°C, the part will go into reset, so the power switches turn off and the soft-start capacitor will be discharged. The LT8714 will come out of reset when the die temperature drops by ~5°C (typical). 8714f For more information www.linear.com/LT8714 23 LT8714 APPLICATIONS INFORMATION Table 2. Power Calculations Example for a 200kHz, 10V to 14V to ±5V/±5A. (VIN = 12V, VOUT = –5V, MN = BSC093N04LSG and MP = STL60P4LLF6 ×2) DEFINITION OF VARIABLES DC = Switch Duty Cycle PVCC = INTVCC LDO Power Driving the BG Gate Driver EQUATION DC ≅ VIN – VOUT 2VIN – VOUT DESIGN EXAMPLE DC ≅ 12V – (–5V) 2 •12V – (–5V) VALUE DC ≅ 58.6% PVCC = 1.04 • QMN • ƒ • VIN PVCC = 1.04 • 12nC • 200kHz • 12V PVCC = 30mW PVEE1 = QMP • ƒ • VIN PVEE1 = 2•44nC • 200kHz • 12V PVEE1 = 211.2mW PVEE2 = 3.15mA • (1 – DC) • VIN PVEE2 = 3.15mA • (1– 0.586) • 12V PVEE2 = 15.65mW PQ = 4mA • VIN PQ = 4mA • 12V PQ = 48mW QMN = NFET Total Gate Charge at VGS = 6.3V ƒ = Switching Frequency PVEE1 = INTVEE LDO Power Driving the TG Gate Driver QMP = PFET Total Gate Charge at VSG = 6.18V PVEE2 = Additional TG Gate Driver Power Loss PQ = Chip Bias Loss PCHIP = 304.85mW 24 8714f For more information www.linear.com/LT8714 LT8714 APPENDIX POWER SWITCH DUTY CYCLE In order to maintain loop stability and deliver adequate current to the load, the external power NFET (MN in the Block Diagram) cannot remain “on” or “off” for 100% of each clock cycle. For Quadrants I and II, the maximum allowable duty cycle is given by: T –MinOnTime TG DC MAX = P •100% TP The minimum duty cycle is given by: MinOffTime TG •100% TP Where MinOffTimeTG = 770ns. For Quadrants III and IV, the maximum allowable duty cycle is given by: For the four quadrant converter: DC ≅ where TP is the clock period and MinOnTimeTG (found in the Electrical Characteristics) is a max of 150ns. DC MIN = The duty cycle equation for the four quadrant converter is given below where VON_MP is the voltage drop across the external power PFET (MP) when it is “on”, and VON_MN is the voltage drop across the external power NFET (MN) when it is “on”. T –MinOffTimeBG DC MAX = P •100% TP VIN – VOUT + VON_MP 2VIN – VOUT + VON_MP – VON_MN INDUCTOR SELECTION For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturating. Molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5A to 15A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 3 for a list of inductor manufacturers. Table 3. Inductor Manufacturers where TP is the clock period and MinOffTimeBG (found in the Electrical Characteristics) is a max of 480ns. Coilcraft MSS1278, XAL1010, MSD1583 and MSD1278 Series www.coilcraft.com The minimum duty cycle is given by: Cooper Bussmann DR127, DRQ127, and HCM1104 Series www.cooperbussmann.com Vishay IHLP Series www.vishay.com Wurth WE-DCT Series WE-CFWI Series 6.8µH, 74485540680 8.2µH,74485540820 10µH, 74485540101 www.we-online.com DC MIN = MinOnTimeBG •100% TP where TP is the clock period and MinOnTimeBG (found in the Electrical Characteristics) is a max of 420ns. The application should be designed such that the operating duty cycle is between DCMIN and DCMAX for both positive and negative output voltages. Minimum Inductance Although there can be a trade-off between efficiency and size, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance: (1) providing adequate load current, (2) avoiding subharmonic oscillation, and (3) supplying minimum ripple current to avoid false tripping of the current comparator. 8714f For more information www.linear.com/LT8714 25 LT8714 APPENDIX Adequate Load Current where: Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: L≥ VIN •DC V | V •I | I 2 • ƒ • CSPN – OUT – OUT OUT 4VIN RSENSE1 (1 – DC) where: LMIN=L1 = L2 for coupled inductors LMIN=L1 || L2 for uncoupled inductors Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A5 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: L1 || L2 for uncoupled inductors L= V •R • DC L MAX ≤ IN SENSE1 3m• ƒ Switch duty cycle (see previous section) DC= where: L1 = L2 for coupled inductors L= Current limit voltage at the operating switch VCSPN= duty cycle (see Max Current Limit vs Duty Cycle (CSP – CSN) plot in the Typical Performance Characteristics) RSENSE1=Current sense resistor connected across the CSP – CSN pins (see Block Diagram) Switching frequency ƒ= Maximum output current IOUT= LMAX=L1 = L2 for coupled inductors LMAX=L1 || L2 for uncoupled inductors Inductor Current Rating The inductor(s) must have a rating greater than their peak operating current to prevent inductor saturation, which would result in efficiency losses. The maximum inductor current (considering start-up and steady-state conditions) is given by: Negative values of L indicate that the output load current, IOUT, exceeds the switch current limit capability of the converter. Decrease RSENSE1 to increase the switch current limit. Avoiding Sub-Harmonic Oscillations The LT8714’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: L MIN ≥ – 26 RSENSE1 •V 40m• ƒ • DC OUT IL_PK_POS = 66mV – 16mV •DC2 VIN • 100ns + RSENSE1 L IL_VY_NEG = –32mV – 16mV •DC2 VIN •190ns VIN •DC + – RSENSE1 L L• ƒ IL1,MAX =IL _ MAX – IL2,MAX IL2,MAX =IL _ MAX •(1–DC) where: IL_PK_POS = Sum of the peak inductor currents for Quadrants III and IV IL_VY_NEG = Sum of the peak inductor currents for Quadrants I and II 8714f For more information www.linear.com/LT8714 LT8714 APPENDIX 3. Calculate RDAMP IL_MAX = Peak or valley current in L1 + L2 IL1_MAX = Peak or valley current in L1 L1+L2 C1 RDAMP ≈ IL2_MAX = Peak or valley current in L2 Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, and if the SS capacitor is sized appropriately to limit inductor currents at start-up. It should be noted that the value calculated for C1 is a starting point. The value of C1 is a trade-off between transient stability and power dissipation in RDAMP. As C1 increases, the power dissipated in RDAMP reduces, but transient performance may be worse. The application should be evaluated and C1 may need to be adjusted to achieve optimal performance. Coupling Network for Tightly Coupled Inductors The capacitor C1 that is connected between the two inductor windings is called the DC link or flying capacitor. Its purpose is to serve as a floating voltage source that virtually connects the input side and output side of the converter. The most optimal value for C1 is given in the equation: An RC damp network maybe required even if using coupled inductors to damp out the resonance between the leakage inductances of L1 and L2, and capacitor C1. In this case, calculate CDAMP as before for single inductors. To calculate RDAMP, replace L1 and L2 with LLK1 and LLK2, which can be found in the manufacture’s data sheet IOUT DC C1≥ • MAX 0.05 • VIN(MIN) ƒ Coupling Network for Loosely Coupled Inductors No RC damping network is needed across C1. 1. Size the flying capacitor C1 according to the equation: C1≥ IOUT DC • MAX 0.25 • VIN(MIN) ƒ L2 LLK2 8714 F13 or contacting the inductor's manufacturer. 1. Size the flying capacitor C1 according to the equation: IOUT DC • MAX 0.25 • VIN(MIN) ƒ 2. Calculate CDAMP CDAMP > 2 •C1 CDAMP RDAMP L1 C1 Figure 13. RC Damp Network for Coupled Inductors C1≥ 2. Calculate CDAMP • Coupling Network for Single Inductors L1 • LLK1 Two discrete inductors shown in Figure 12 maybe used instead of a coupled inductor with a few requirements. CDAMP RDAMP C1 CDAMP > 2 •C1 3. Calculate RDAMP L2 8714 F12 Figure 12. RC Damp Network for Discrete Inductors RDAMP ≈ LLK1 +LLK2 C1 8714f For more information www.linear.com/LT8714 27 LT8714 APPENDIX It should be noted that the value calculated for C1 is a starting point. The value of C1 is a trade-off between transient stability and power dissipation in RDAMP. As C1 increases, the power dissipated in RDAMP reduces, but transient performance may be worse. The application should be evaluated and C1 may need to be adjusted to achieve optimal performance. INPUT AND OUTPUT CAPACITOR SELECTION Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching noise. A minimum 1µF ceramic capacitor should also be placed from VIN to GND and from BIAS to GND as close to the LT8714 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. Input Capacitor, CIN The input capacitor, CIN, carries the high frequency chopped current and must be sized appropriately. Below is the equation for calculating the capacitance of CIN for 0.5% input voltage ripple: CIN ≥ 28 IOUT • DC 0.005 • VIN • ƒ where: DC=Switch duty cycle (see Power Switch Duty Cycle section) Switching frequency ƒ= The worst case for the input capacitor (largest capacitance needed) is when the input voltage is at its lowest because the duty cycle is the highest. Keep in mind that the voltage rating of the input capacitor needs to be greater than the maximum input voltage. This equation calculates the capacitance value during steady-state operation and may need to be adjusted for desired transient response. Also, this assumes no ESR, so the input capacitance may need to be larger depending on the equivalent ESR of the input capacitor(s). Output Capacitor, COUT The output capacitor, COUT, sees the inductor ripple current. Below is the equation for calculating the capacitance of COUT for 0.5% output voltage ripple: COUT ≥ VIN • DC 8 •L • ƒ 2 • 0.005 • VOUT where: DC= Switch duty cycle (see Power Switch Duty Cycle section) L= Inductance Value Switching frequency ƒ= The worst case for the output capacitor (largest capacitance needed) is when the output regulation voltage is at its most negative value. This equation calculates the capacitance value during steady-state operation and may need to be adjusted for desired transient response. Also, this assumes no ESR, so the output capacitance may need to be larger depending on the equivalent ESR of the output capacitor(s). See Table 4 for a list of ceramic capacitor manufacturers. 8714f For more information www.linear.com/LT8714 LT8714 APPENDIX put a Schottky diode in parallel with both FET’s to shunt the internal body diodes. Note that the Schottky diode forward drop must be smaller than the body diode forward voltage. Table 4. Ceramic Capacitor Manufacturers TDK www.tdk.com Murata www.murata.com Taiyo Yuden www.t-yuden.com POWER MOSFET SELECTION The LT8714 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. It is important to select MOSFETs for optimizing efficiency. For choosing an NFET and PFET, the important device parameters are: 1. Breakdown Voltage (BVDSS) 2. Gate Threshold Voltage (VGSTH) 3. On-Resistance (RDSON) 4. Total Gate Charge (QG) 5. Turn-Off Delay Time (tD(OFF)) 6. Package has Exposed Paddle The drain-to-source breakdown voltage of the NFET and PFET power MOSFETs must exceed: BVDSS > 2VIN – VOUT If operating close to the BVDSS rating of the MOSFET, check the leakage specifications on the MOSFET because leakage can decrease the efficiency of the converter. The gate to source voltage affects the on-resistance and total gate charge of the FETs. In general, power MOSFET on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher total gate charge. Choose MOSFETs with an on-resistance to give a voltage drop to be less than 300mV at the peak current. At the same time, choose MOSFETs with a lower total gate charge to reduce LT8714 power dissipation and MOSFET switching losses. It should be noted that for high input to output voltage applications, reverse recovery loss can be a noticeable power loss term in both FETs due to four quadrant operation of the LT8714. In these applications, it may be beneficial to The turn-off delay time (tD(OFF)) of available NFETs is generally smaller than that of available PFETs. However, the delay time of both FETs should be checked for a given application due to four quadrant operation of the LT8714. The turn-off delay time of the PFET as specified by the data sheet must be less than ~140ns. The turn-off delay time of the NFET as specified by the data sheet must be less than ~90ns. If the turn-off delay times as specified by the data sheets of both FETs are longer than the respective non-overlap times, the FETs may still be good to use. To verify, measure the NFET and PFET turn-off delay times directly at the gate pin of both FETs. The NFET and PFET gate-to-source drive is approximately 6.3V and 6.18V respectively, so logic level MOSFETs are required. The BG gate driver can begin switching when the INTVCC voltage exceeds ~4V. To prevent possible damage to the NFET, ensure that the selected NFET is in the triode region of operation with 4V of gate-to-source drive. The TG gate driver can begin switching when the BIAS to INTVEE voltage exceeds ~3.45V, so it is optimal that the PFET be in the linear mode of operation with 3.45V of gate-to-source drive. Finally, both the NFET and PFET power MOSFETs should be in a package with an exposed paddle for the drain connection to be able to dissipate heat. The on-resistance of MOSFETs is proportional to temperature, so it’s more efficient if the MOSFETs are running “cool” with the help of the exposed paddle. See Table 5 for a list of power MOSFET manufacturers and Table 6 for a list of recommended PFET’s. Table 5. Power MOSFET (NFET and PFET) Manufacturers Fairchild Semiconductor www.fairchildsemi.com On-Semiconductor www.onsemi.com Vishay www.vishay.com Diodes Inc. www.diodes.com Infineon www.infineon.com ST Microelectronics www.st.com 8714f For more information www.linear.com/LT8714 29 LT8714 APPENDIX Table 6. Recommended PFETs 20V SI7635DP, SI7633DP www.vishay.com 30V SI7101DN, SI7143DP www.vishay.com 40V FDD4141, SI7463ADP, SIS443DN, SI7611DN www.fairchildsemi.com, www.vishay.com STL604PLLF6 www.st.com 60V SI7465DP, SUD19P06-60, SUD50P06-15 STL42P6LLF6 100V FDMC86139P, SI7113DN www.vishay.com www.st.com ILOAD 2A/DIV VOUT 500mV/DIV AC-COUPLED IL1 + IL2 3.5A/DIV RC = 1.04k CC = 10nF www.fairchildsemi.com, www.vishay.com 500μsec/DIV 8714 F14 Figure 14: Transient Response Shows Excessive Ringing COMPENSATION – ADJUSTMENT To compensate the feedback loop of the LT8714, a series resistor-capacitor network in parallel with an optional single capacitor should be connected from the VC pin to GND. For most applications, choose a series capacitor in the range of 1nF to 10nF with 4.7nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 220pF with 100pF being a good starting value. The compensation resistor, RC, is usually in the range of 5kΩ to 50kΩ. A good technique to compensate a new application is to use a 100kΩ potentiometer in place of the series resistor RC. With the series and parallel capacitors at 4.7nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be found. The series capacitor can be reduced or increased from 4.7nF to speed up the converter or slow down the converter, respectively. For the circuit in Figure 5, a 10nF series cap was used. Figures 14 to 16 illustrate the process of tuning RC for the circuit of Figure 5 with a load current stepped between 1A and 3.5A with an input voltage of 10V. Figure 14 shows the transient response with RC equal to 1.04kΩ. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 15, the value of RC is increased to 2.74kΩ, which results in a more damped response. Figure 16 shows the results when RC is increased further to 4.75kΩ. The transient response is nicely damped and the compensation procedure is complete. ILOAD 2A/DIV VOUT 500mV/DIV AC-COUPLED IL1 + IL2 3.5A/DIV RC = 2.74k CC = 10nF 500μsec/DIV 8714 F15 Figure 15: Transient Response Is Improved ILOAD 2A/DIV VOUT 500mV/DIV AC-COUPLED IL1 + IL2 3A/DIV RC = 4.75k CC = 10nF 500μsec/DIV 8714 F16 Figure 16: Transient Response Is Well Damped Note the load transient plots shown are for Quadrant I. The RC value may need to be adjusted to find a balance to ensure stability in all four quadrants. 30 8714f For more information www.linear.com/LT8714 LT8714 TYPICAL APPLICATIONS 200kHz, 10V to 14V Input Generates a –5V to 5V Output that Delivers –5A to 5A of Output Current RSENSE2 6mΩ L1 ISP 10µH TG • ISN CIN 22µF ×4 C1 22µF ×2 L2 10µH VOUT –5V TO 5V ±5A MAX • VIN 10V TO 14V MP ×2 MN COUT 100µF ×4 RSENSE1 2.5mΩ TG BG CSN CSP TG VIN ISN ISN ISP ISP EN BIAS 51.1k 10k 2.2µF INTVCC 178k 73.2k VIN 2.2µF LT8714 INTVEE PG FB RT CTRL VC SYNC GND IMON VCTRL = SS 68nF 100pF 4.75k 0.1V FOR –5VOUT 0.55V FOR 0VOUT 1.0V FOR 5VOUT 100nF 10nF 470nF 8714 TA03a L1, L2: WURTH 10μH WE-CFWI 74485540101 MN: INFINEON BSC093N04LSG MP: STMICRO STL60P4LLF6 5 Power Loss in Each Quadrant (VIN = 12V) IN VCTRL Step from 0.1V to 1V to 0.1V (RLOAD = 1Ω) II 4 I VCTRL 500mV/DIV 3 LOAD CURRENT (A) CIN, C1: 22μF, 25V, 1812, X7R COUT: 100μF, 16V, 1210, X5R RSENSE1: 2.5mΩ, 2512 RSENSE2: 6mΩ, 2512 2 VOUT = –5V VOUT 5V/DIV VOUT = 5V 1 IL1 + IL2 20A/DIV 0 –1 –2 VOUT = –5V 1.2msec/DIV VOUT = 5V 8714 TA03c –3 –4 –5 III 8 IV 6 4 2 0 2 4 POWER LOSS (W) 6 8 8714 TA03b 8714f For more information www.linear.com/LT8714 31 LT8714 TYPICAL APPLICATIONS 300kHz, Bidirectional 1A Current Source RSENSE2 50mΩ L1 IOSP 22µH TG • IOSN CIN2 22µF ×3 C1 4.7µF ×2 L2 22µH RSENSE1 10mΩ CSN CSP TG VIN 115k ISP 118k INTVCC Q1 VIN 49.9k 47nF 0.47µF 2.2µF LT8714 INTVCC VIN 4.32k BIAS EN 2.2µF 24.9k Q2 ISN 51.1k VOUT COMPLIANCE: –8.2V AND 8.2V 49.9k 24.9k TG 10k COUT 10µF ×2 D1 MN BG IOUT –1A TO 1A –6V ≤ VOUT ≤ 6V • VIN 10V TO 20V MP INTVEE PG FB RT CTRL SYNC IOSP 10Ω 22nF 470nF VC GND IMON SS 100pF 220nF 47nF +IN 16.5k IOSN 22nF 10Ω V+ SHDN LT1999-20 VOUT –IN 4.7nF GND REF ICTRL = 1.5V FOR –1A OUT 2.5V FOR 0A OUT 3.5V FOR 1A OUT 422Ω 100Ω 0.1µF ICTRL 402Ω 2.2µF 8714 TA04a L1, L2: COILCRAFT 22μH MSD1278-223ML MN: FAIRCHILD FDMC86570L MP: STMICRO STL42P6LLF6 Q1: CENTRAL SEMI CMST3904 Q2: CENTRAL SEMI CMST3906 D1: CENTRAL SEMI CMDD4448 ICTRL Step from 1.5V to 3.5V to 1.5V at VIN = 12V (No Load) Output Current and Power Loss vs ICTRL(RLOAD = 6Ω) 1.00 vs ICTRL (RLOAD = 6Ω) 0.50 1.8 0.25 1.5 0 1.2 –0.25 0.9 –0.50 0.6 –0.75 0.3 –1.00 1.50 1.75 32 2 2.25 2.50 2.75 ICTRL (V) 3 ICTRL Step from 1.5V to 3.5V to 1.5V at VIN = 12V (RLOAD = 6Ω) IOUT VOUT 2.1 POWER LOSS (W) OUTPUT CURRENT (A) 0.75 2.4 VIN = 12V CIN: 22μF, 25V, 1812, X7R C1: 4.7μF, 50V, 1210, X7R COUT: 10μF, 16V, 1210, X7R RSENSE1: 10mΩ, 1206 RSENSE2: 50mΩ, 2512 IOUT 0.5A/DIV VOUT 5V/DIV 0V/0A VOUT 5V/DIV IOUT 0.5A/DIV IOUT ICTRL 2V/DIV 0V/0A VOUT ICTRL 2V/DIV 0.5msec/DIV 8714 TA04c 0.5msec/DIV 8714 TA04d 0 3.25 3.50 8714 TA04b 8714f For more information www.linear.com/LT8714 LT8714 TYPICAL APPLICATIONS 200kHz, 20V to 30V Input Generates a –15V to 15V Output that Delivers –1A to 1A of Output Current RSENSE2 30mΩ ISN VIN 20V TO 30V MP ISP TG 37.4Ω, 1206 L1 47µH + CIN2 10µF ×2 CIN1 47µF C2 4.7µF 37.4Ω, 1206 C1 0.47µF L2 120µH VOUT –15V TO 15V ±1A MAX MN COUT 22µF ×4 RSENSE1 10mΩ TG BG CSN CSP TG VIN ISN ISN ISP ISP EN BIAS 110k 10k 2.2µF 178k LT8714 INTVCC 215k VIN 2.2µF INTVEE PG FB RT CTRL VC SYNC GND IMON VCTRL = SS 68nF 100pF 14.7k 0.1V FOR –15VOUT 0.585V FOR 0VOUT 1.074V FOR 15VOUT 100nF 4.7nF 470nF 8714 TA05a L1: COILCRAFT 47μH MSS1278T-473KL L2: COILCRAFT 120μH MSS1278T-124KL MN: FAIRCHILD FDMC86102 MP: FAIRCHILD FDMC86139P CIN1: 47μF, 50V AVX TCJE476M035R0055 CIN2: 10μF, 50V, 1210, X7S C1: 0.47μF, 100V, 1812, X7R C2: 4.7μF, 100V, 1812, X7R COUT: 22μF, 25V, 1812, X7R RSENSE1: 10mΩ, 2512 RSENSE2: 30mΩ, 2512 Power Loss in Each Quadrant (VIN = 24V) 1.00 VCTRL Step from 0.1V to 1V to 0.1V at VIN = 24V (RLOAD = 20Ω) In Each Quadrant (VIN = 24V) II 0.80 ICTRL 1V/DIV I LOAD CURRENT (A) 0.60 VOUT 20V/DIV 0.40 VOUT = –15V 0.20 VOUT = 15V IL1 + IL2 5A/DIV 0.00 –0.20 VOUT = –15V –0.40 VOUT = 15V 1.2msec/DIV 8714 TA05c –0.60 –0.80 –1.00 III 4 IV 3 2 1 0 1 2 POWER LOSS (W) 3 4 8714 TA05b 8714f For more information www.linear.com/LT8714 33 LT8714 350kHz, Four Quadrant Converter, Drives a 3A TEC from a 10V to 14V Input RSENSE2 10mΩ • TG CIN 22µF ×4 C1 22µF L2 8.2µH VTEC –5V TO 5V • L1 ISP 8.2µH ISN VIN 10V TO 14V MP ±3A MAX MN COUT 100µF ×2 RSENSE1 4mΩ TG BG CSN CSP TG VIN 51.1k 2.2µF 102k ISN ISP ISP 73.2k VIN BIAS EN 10k ISN TEC LT8714 INTVCC 2.2µF INTVEE PG FB RT CTRL VC SYNC GND IMON VCTRL = SS 47nF 100pF 8.06k 0.1V FOR –5VTEC 0.55V FOR 0VTEC 1.0V FOR 5VTEC 100nF 4.7nF 220nF 8714 TA06a L1, L2: WURTH 8.2μH WE-CFWI 74485540820 CIN, C1: 22μF, 25V, 1812, X7R MN: INFINEON BSC093N04LSG COUT: 100μF, 6.3V, 1812, X5R RSENSE1: 4mΩ, 2012 MP: STMICRO STL60P4LLF6 RSENSE2: 10mΩ, 2512 Power Loss vs Load Current (VIN = 12V) 4.0 TEC Temp vs TEC Voltage (VIN = 12V)* VIN = 12V 10 VIN = 12V 3.5 POWER LOSS (W) TTEC – TAMBIENT (°C) 0 3.0 VTEC = –5V 2.5 2.0 1.5 VTEC = 5V 1.0 –10 –20 –30 0.5 0 0 0.5 1 1.5 2 LOAD CURRENT (A) 2.5 3 –40 –1 0 1 2 3 TEC VOLTAGE (V) 4 5 8714 TA06c 8714 TA06b *TEC = LAIRD DA-011-05-02-00-00 FAN DRIVE TO 5V 34 8714f For more information www.linear.com/LT8714 LT8714 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT8714#packaging for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CB DETAIL A 6.40 – 6.60* (.252 – .260) 3.86 (.152) 3.86 (.152) 0.60 (.024) REF 0.28 (.011) REF 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 DETAIL A 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0° – 8° 0.65 (.0256) BSC 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CB) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 8714f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LT8714 35 LT8714 TYPICAL APPLICATION 300kHz, 5V Input Generates a –2.5V to 2.5V Output that Delivers –5A to 5A of Output Current RSENSE2 6mΩ C1 22µF ×2 TG L2 2.9µH • L1 2.9µH + CIN2 100µF ×4 CIN1 560µF 5 VOUT –2.5V TO 2.5V ±5A MAX • VIN 4.5V TO 5.5V ISP MN COUT 100µF ×6 RSENSE1 2.5mΩ TG BG CSN CSP TG VIN 19.6k 2.2µF 118k ISN ISP ISP 37.4k LT8714 3 2 FB RT CTRL VC SYNC GND IMON 47nF –2 VOUT = 2.5V 100pF 9.09k 220nF III 5 IV 4 3 2 1 0 1 2 POWER LOSS (W) 100nF 4 5 1.5A to 4A Load Step (QI, VOUT = 2.5V) 6.8nF CIN2, COUT: 100μF, 6.3V, 1812, X5R C1: 22μF, 25V, 1812, X7R RSENSE1: 2.5mΩ, 2512 RSENSE2: 6mΩ, 2512 3 8714 TA02b 0.1V FOR –2.5VOUT 0.508V FOR 0VOUT 0.914V FOR 2.5VOUT 8714 TA02a L1, L2: WURTH 2.9μH WE-CFWI 74485540290 MN: VISHAY SiRA12DP MP: VISHAY Si7625DN CIN1: OSCON 560μF, 10V 10SEQP560M VOUT = –2.5V 0 –5 VCTRL = SS VOUT = 2.5V –1 INTVEE PG VOUT = –2.5V 1 –4 4.7µF INTVCC I II –3 VIN BIAS EN 10k ISN Power Loss vs Load Current in Each Quadrant (VIN =IN5V) 4 LOAD CURRENT (A) ISN MP ×2 VOUT 200mV/DIV AC-COUPLED IL1 + IL2 5A/DIV ISTEP 2A/DIV 200μsec/DIV 8714 TA02c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch 3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN LT3958 Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 84V Switch 5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN LT8705 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 2.8V ≤ VIN ≤ 80V, 100kHz to 400kHz Programmable Operating Frequency, 5mm × 7mm QFN-38 and TSSOP-38 LT8709 Negative Input Synchronous Multi-Topology DC/DC Control –80V ≤ VIN ≤ –4.5V, Up to 400kHz Programmable Operating Frequency, TSSOP-20 LT8710 Synchronous SEPIC/Inverting/Boost Controller with Output Current Control 4.5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency, TSSOP-20 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT8714 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT8714 8714f LT 1115 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015