LTC7812
Low IQ, 38V Synchronous
Boost+Buck Controller
Features
Description
Synchronous Boost and Buck Controllers
n When Cascaded, Allows V Above, Below or Equal
IN
to Regulated VOUT
n Output Remains in Regulation Through Input Dips
(e.g., Cold Crank) Down to 2.5V
n Wide Bias Input Voltage Range: 4.5V to 38V
n Low Input and Output Ripple
n Low EMI
n Fast Output Transient Response
n High Light Load Efficiency
n Low Operating I : 33µA (Both Channels On)
Q
n Low Operating I : 28µA (Buck Channel On)
Q
n R
or
Lossless
DCR Current Sensing
SENSE
n Buck Output Voltage Range: 0.8V ≤ V
OUT ≤ 24V
n Boost Output Voltage Up to 60V
n Phase-Lockable Frequency (75kHz to 850kHz)
n Small 32-Pin 5mm × 5mm QFN Package
The LTC®7812 is a high performance synchronous
Boost+Buck DC/DC switching regulator controller that
drives all N-channel power MOSFET stages. It contains
independent step-up (boost) and step-down (buck) controllers that can regulate two separate outputs or be cascaded
to regulate an output voltage from an input voltage that
can be above, below or equal to the output voltage. The
LTC7812 operates from a wide 4.5V to 38V input supply
range. When biased from the output of the boost regulator,
the LTC7812 can operate from an input supply as low as
2.5V after start-up. The 33μA no-load quiescent current
extends operating run time in battery-powered systems.
n
Unlike conventional buck-boost regulators, the LTC7812’s
cascaded Boost+Buck solution has continuous, nonpulsating, input and output currents, substantially reducing
voltage ripple and EMI. The LTC7812 has independent
feedback and compensation points for the boost and buck
regulation loops, enabling a fast output transient response
that can be easily optimized externally.
Applications
Automotive and Industrial Power Systems
High Power Battery Operated Systems
n
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP and µModule are registered trademarks and
No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
n
Typical Application
Wide Input Range to 12V/8A Low IQ, Cascaded Boost+Buck Regulator
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
2mΩ
+
33µF
1µH
VMID, 14V**
6.8µF
6.8µF
+
33µF
4.7µH
3mΩ
499k
499k
46.4k
35.7k
22µF
+
VOUT
12V
8A*
47µF
4.7µF
0.1µF
0.1µF
SENSE2+ SENSE2– BG2 SW2 BOOST2
TG2
INTVCC
PGND
VFB2 VBIAS
TG1 BOOST1
ITH2
ITH1
TRACK/SS1
SS2
FREQ
SENSE1+ SENSE1– VFB1
EXTVCC
LTC7812
RUN1 RUN2
SW1 BG1
PLLIN/MODE SGND
0.1µF
15k
4.7nF
100pF
1.86k
6.8nF
820pF
0.01µF
* WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
** VMID = 14V WHEN VIN < 14V
VMID FOLLOWS VIN WHEN VIN > 14V
7812 TA01a
7812fa
For more information www.linear.com/LTC7812
1
LTC7812
Order Information
EXTVCC
VBIAS
BG2
BOOST2
TG2
SW2
BG1
TOP VIEW
BOOST1
32 31 30 29 28 27 26 25
SW1 1
24 INTVCC
TG1 2
23 NC
22 OV2
PGOOD1 3
TRACK/SS1 4
21 SGND
33
PGND
ITH1 5
20 SGND
VFB1 6
19 RUN2
SENSE1+ 7
18 SGND
SENSE1– 8
17 RUN1
SGND
ITH2
VFB2
SENSE2–
SENSE2+
9 10 11 12 13 14 15 16
SS2
Bias Input Supply Voltage (VBIAS)............... –0.3V to 40V
Buck Top Side Driver Voltage (BOOST1)..... –0.3V to 46V
Boost Top Side Driver Voltage (BOOST2)..... –0.3V to 76V
Buck Switch Voltage (SW1) .......................... –5V to 40V
Boost Switch Voltage (SW2) ......................... –5V to 70V
INTVCC, (BOOST1–SW1),
(BOOST2–SW2)....................................... –0.3V to 6V
RUN1, RUN2 ................................................ –0.3V to 8V
Maximum Current Sourced Into Pin
from Source >8V...............................................100µA
BG1, BG2, TG1, TG2............................................ (Note 8)
SENSE1+, SENSE1– Voltages....................... –0.3V to 28V
SENSE2+, SENSE2– Voltages...................... –0.3V to 40V
FREQ Voltage.........................................–0.3V to INTVCC
EXTVCC....................................................... –0.3V to 14V
ITH1, ITH2, VFB1, VFB2, Voltages..................... –0.3V to 6V
PLLIN/MODE, PGOOD1, OV2 Voltages ......... –0.3V to 6V
TRACK/SS1, SS2 Voltages ........................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC7812E, LTC7812I........................... –40°C to 125°C
LTC7812H........................................... –40°C to 150°C
Storage Temperature Range............... –65°C to 150°C
Pin Configuration
PLLIN/MODE
(Note 1)
FREQ–
Absolute Maximum Ratings
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 150°C, qJA = 44°C/W
EXPOSED PAD (PIN 33) IS PGND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC7812#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7812EUH#PBF
LTC7812EUH#TRPBF
7812
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7812IUH#PBF
LTC7812IUH#TRPBF
7812
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7812HUH#PBF
LTC7812HUH#TRPBF
7812
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
7812fa
2
For more information www.linear.com/LTC7812
LTC7812
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VBIAS
Bias Input Supply Operating Voltage
Range
4.5
38
V
VOUT1
Buck Regulated Output Voltage Set Point
(SENSE1 Pins Common Mode Range)
0.8
24
V
VOUT2
Boost Regulated Output Voltage Set Point
60
V
38
V
SENSE2 Pins Common Mode Range
(BOOST Converter Input Supply Voltage)
VFB1
VFB2
IFB1,2
Buck Regulated Feedback Voltage
Boost Regulated Feedback Voltage
2.5
MAX
UNITS
(Note 4); ITH1 Voltage = 1.2V
0°C to 85°C, All Grades
LTC7812E, LTC7812I
LTC7812H
l
l
0.792
0.788
0.786
0.800
0.800
0.800
0.808
0.812
0.812
V
V
V
(Note 4); ITH2 Voltage = 1.2V
0°C to 85°C, All Grades
LTC7812E, LTC7812I
LTC7812H
l
l
1.183
1.181
1.176
1.200
1.200
1.200
1.214
1.218
1.218
V
V
V
–2
±50
nA
Feedback Current
(Note 4)
Reference Voltage Line Regulation
(Note 4); VIN = 4V to 38V
0.002
0.02
%/V
Output Voltage Load Regulation (Note 4)
Measured in Servo Loop;
DITH Voltage = 1.2V to 0.7V
l
0.01
0.1
%
Measured in Servo Loop;
DITH Voltage = 1.2V to 2V
l
–0.01
–0.1
%
gm1,2
Transconductance Amplifier gm
(Note 4); ITH1,2 = 1.2V;
Sink/Source 5µA
IQ
Input DC Supply Current
(Note 5)
Pulse-Skipping or
Forced Continuous Mode
(One Channel On)
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V
VFB1 ON = 0.83V (No Load)
VFB2 = 1.25V (No Load)
Pulse-Skipping or
Forced Continuous Mode
(Both Channels On)
RUN1,2 = 5V,
VFB1 = 0.83V (No Load)
VFB2 = 1.25V (No Load)
Sleep Mode
(One Channel On, Buck)
RUN1 = 5V and RUN2 = 0V
VFB1 = 0.83V (No Load)
Sleep Mode
(One Channel On, Boost)
UVLO
TYP
2
mmho
1.5
mA
3
mA
28
48
µA
RUN2 = 5V and RUN1 = 0V
VFB2 = 1.25V (No Load)
33
53
µA
Sleep Mode
(Both Channels On)
RUN1,2 = 5V
VFB1 = 0.83V (No Load)
VFB2 = 1.25V (No Load)
33
46
µA
Shutdown
RUN1,2 = 0V
10
20
µA
Undervoltage Lockout
INTVCC Ramping Up
l
INTVCC Ramping Down
l
Buck Feedback Overvoltage Protection
Measured at VFB1 Relative to
Regulated VFB1
l
4.15
4.5
V
3.5
3.8
4.0
V
7
10
13
%
±1
µA
±2
µA
µA
SENSE1+ Pin Current
SENSE2+ Pin Current
170
SENSE1– Pin Current
VOUT1 < VINTVCC – 0.5V
VOUT1 > VINTVCC + 0.5V
SENSE2– Pin Current
VSENSE2+, VSENSE2– = 12V
700
µA
±1
µA
7812fa
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3
LTC7812
Electrical
Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
Maximum Duty Factor for TG
Buck (Channel 1) in Dropout, FREQ = 0V
Boost (Channel 2) in Overvoltage
Maximum Duty Factor for BG
Buck (Channel 1) in Overvoltage
Boost (Channel 2)
ITRACK/SS1
Soft-Start Charge Current
VTRACK/SS1 = 0V
3
5
8
µA
ISS2
Soft-Start Charge Current
VSS2 = 0V
3
5
8
µA
VRUN1 ON
VRUN2 ON
RUN1 Pin Threshold
RUN2 Pin Threshold
VRUN1 Rising
VRUN2 Rising
1.18
1.21
1.24
1.27
1.32
1.33
V
V
l
l
MIN
TYP
98
99
100
%
%
100
96
%
%
RUN Pin Hysteresis
VSENSE1,2,(MAX)
Maximum Current Sense Threshold
MAX
70
VFB1,2 = 0.7V, VSENSE1,2– = 3.3V
VFB2 = 1.1V, VSENSE2+ = 12V
l
43
50
UNITS
mV
57
mV
Gate Driver
TG1 Pull-Up On-Resistance
TG1 Pull-Down On-Resistance
2.5
1.5
Ω
Ω
BG1 Pull-Up On-Resistance
BG1 Pull-Down On-Resistance
2.4
1.1
Ω
Ω
TG2 Pull-Up On-Resistance
TG2 Pull-Down On-Resistance
1.2
1.0
Ω
Ω
BG2 Pull-Up On-Resistance
BG2 Pull-Down On-Resistance
1.2
1.0
Ω
Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
16
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
28
13
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver Buck (Channel 1)
Boost (Channel 2)
30
70
ns
ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver Buck (Channel 1)
Boost (Channel 2)
30
70
ns
ns
tON(MIN)1
Buck Minimum On-Time
(Note 7)
95
ns
tON(MIN)2
Boost Minimum On-Time
(Note 7)
120
ns
INTVCC Linear Regulator
Internal VCC Voltage
6V < VBIAS < 38V, VEXTVCC = 0V, IINTVCC = 0mA
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 0V
Internal VCC Voltage
6V < VEXTVCC < 13V, IINTVCC = 0mA
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 8.5V
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
5.0
5.0
4.5
5.4
5.6
V
0.7
2
%
5.4
5.6
V
0.7
2
%
4.7
V
200
mV
RFREQ = 25k; PLLIN/MODE = DC Voltage
115
kHz
RFREQ = 65k; PLLIN/MODE = DC Voltage
440
kHz
EXTVCC Hysteresis
Oscillator and Phase-Locked Loop
Programmable Frequency
RFREQ = 105k; PLLIN/MODE = DC Voltage
Low Fixed Frequency
VFREQ = 0V PLLIN/MODE = DC Voltage
835
320
350
kHz
380
kHz
7812fa
4
For more information www.linear.com/LTC7812
LTC7812
Electrical
Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
High Fixed Frequency
VFREQ = INTVCC; PLLIN/MODE = DC Voltage
485
535
585
kHz
Synchronizable Frequency
PLLIN/MODE = External Clock
850
kHz
PGOOD1 Voltage Low
IPGOOD1 = 2mA
0.4
V
±1
µA
l
75
PGOOD1 Output
0.2
PGOOD1 Leakage Current
VPGOOD1 = 5V
PGOOD1 Trip Level
VFB1 with Respect to Set Regulated Voltage
VFB1 Ramping Negative
–13
Hysteresis
–10
–7
2.5
VFB1 Ramping Positive
7
Hysteresis
Delay For Reporting a Fault
10
%
%
13
%
2.5
%
40
µs
OV2 Boost Overvoltage Indicator Output
OV2 Voltage Low
IOV2 = 2mA
OV2 Leakage Current
VOV2 = 5V
OV2 Trip Level
VFB2 Ramping Positive with Respect to Set
Regulated Voltage
6
0.2
0.4
V
±1
µA
10
13
%
Hysteresis
1.5
%
VBOOST2 = 16V; VSW2 = 12V;
Forced Continuous Mode
65
µA
BOOST2 Charge Pump
BOOST2 Charge Pump Available Output
Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7812 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC7812E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC7812I is guaranteed
over the –40°C to 125°C operating junction temperature range and the
LTC7812H is guaranteed over the –40°C to 150°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors. TJ is calculated from the ambient temperature
TA and power dissipation PD according to the following formula: TJ = TA +
(PD • θJA), where θJA = 44°C/W.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC7812 is tested in a feedback loop that servos VITH1,2 to
a specified voltage and measures the resultant VFB. The specification at
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC7812E/LTC7812I, 150°C for the LTC7812H). For the LTC7812I
and LTC7812H, the specification at 0°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –40°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of IMAX (See the Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
7812fa
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5
LTC7812
Typical Performance Characteristics
90
60
50
PULSE-SKIPPING
MODE
40
30
20
FORCED
CONTINUOUS
MODE
80
70
70
Burst Mode
OPERATION
60
50
30
PULSE-SKIPPING
MODE
20
10
0
0.0001
1
9
FORCED
CONTINUOUS
MODE
40
0
0.0001
0.01
0.1
LOAD CURRENT (A)
90
80
10
0.001
100
FIGURE 9 CIRCUIT
VOUT = 12V
10
10
FORCED CONTINUOUS MODE
1
POWER LOSS (W)
0.001
0.01
0.1
LOAD CURRENT (A)
1
0.001
0.01
0.1
LOAD CURRENT (A)
1
9
97
95
93
92
90
0
5
10
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
7812 G07
0.001
0.01
0.1
LOAD CURRENT (A)
1
PULSE-SKIPPING
MODE
FORCED CONTINUOUS MODE
PULSE-SKIPPING
MODE
0.1
Burst Mode
OPERATION
0.01
0.001
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1
0.001
0.0001
9
0.001
0.01
0.1
LOAD CURRENT (A)
7812 G05
808
806
804
802
800
798
796
794
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G08
1
9
7812 G06
Buck Regulated Feedback Voltage
vs Temperature
792
–75 –50 –25
9
FIGURE 9 CIRCUIT
VOUT = 12V
1
Burst Mode
OPERATION
REGULATED FEEDBACK VOLTAGE (mV)
EFFICIENCY (%)
98
IOUT = 4A
IOUT = 8A
PULSE-SKIPPING
MODE
Power Loss vs Load Current
VIN = 18V
FORCED CONTINUOUS MODE
0.1
Efficiency vs Input Voltage
FIGURE 9 CIRCUIT
VOUT = 12V
30
7812 G03
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G04
100
40
0
0.0001
9
0.01
FIGURE 9 CIRCUIT
VOUT = 12V
0.001
0.0001
FORCED
CONTINUOUS
MODE
50
20
1.212
REGULATED FEEDBACK VOLTAGE (V)
POWER LOSS (W)
1
0.01
Burst Mode
OPERATION
60
Power Loss vs Load Current
VIN = 14V
Burst Mode
OPERATION
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G02
Power Loss vs Load Current
VIN = 9V
PULSE-SKIPPING
MODE
Efficiency vs Load Current
VIN = 18V
10
7812 G01
0.1
EFFICIENCY (%)
Burst Mode
OPERATION
70
Efficiency vs Load Current
VIN = 14V
POWER LOSS (W)
80
EFFICIENCY (%)
100
FIGURE 9 CIRCUIT
VOUT = 12V
90
EFFICIENCY (%)
100
Efficiency vs Load Current
VIN = 9V
Boost Regulated Feedback
Voltage vs Temperature
1.209
1.206
1.203
1.200
1.197
1.194
1.191
1.188
–75 –50 –25
0 25 50 75 100 120 150
TEMPERATURE (°C)
7812 G09
7812fa
6
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LTC7812
Typical Performance Characteristics
Load Step at VIN = 9V
Burst Mode Operation
Load Step at VIN = 14V
Burst Mode Operation
Load Step at VIN = 18V
Burst Mode Operation
VOUT
1V/DIV
ACCOUPLED
VOUT
1V/DIV
ACCOUPLED
VOUT
1V/DIV
ACCOUPLED
IL1
2A/DIV
IL1
2A/DIV
IL1
2A/DIV
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G10
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
Load Step at VIN = 9V
Pulse-Skipping Mode
7812 G11
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
Load Step at VIN = 14V
Pulse-Skipping Mode
Load Step at VIN = 18V
Pulse-Skipping Mode
VOUT
500mV/DIV
ACCOUPLED
VOUT
500mV/DIV
ACCOUPLED
VOUT
500mV/DIV
ACCOUPLED
IL1
2A/DIV
IL1
2A/DIV
IL1
2A/DIV
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G13
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
Load Step at VIN = 9V
Forced Continuous Mode
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G14
VOUT
500mV/DIV
ACCOUPLED
VOUT
500mV/DIV
ACCOUPLED
IL1
2A/DIV
IL1
2A/DIV
IL1
2A/DIV
7812 G16
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G15
Load Step at VIN = 18V
Forced Continuous Mode
Load Step at VIN = 14V
Forced Continuous Mode
VOUT
500mV/DIV
ACCOUPLED
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G12
7812 G17
200µs/DIV
FIGURE 9 CIRCUIT
VOUT = 12V
7812 G18
7812fa
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7
LTC7812
Typical Performance Characteristics
Buck Inductor Current at Light
Load
Boost Inductor Current at Light
Load
FORCED CONTINUOUS MODE
FORCED CONTINUOUS MODE
IL2
5A/DIV
7812 G19
7812 G20
5µs/DIV
INTVCC Line Regulation
INTVCC and EXTVCC
vs Load Current
EXTVCC Switchover and INTVCC
Voltages vs Temperature
5.6
6.0
EXTVCC = 0V
5.1
5.8
EXTVCC AND INTVCC VOLTAGE (V)
INTVCC VOLTAGE (V)
5.2
EXTVCC = 8.5V
5.2
5.0
4.8
EXTVCC = 5V
4.6
4.4
4.2
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
0
20
SENSE1– CURRENT (µA)
SENSE CURRENT (µA)
SENSE1 PIN
500
400
300
200
SENSE2 PIN
100
5
10 15 20 25 30 35
VSENSE COMMON MODE VOLTAGE (V)
5.0
40
7812 G25
EXTVCC RISING
4.8
4.6
EXTVCC FALLING
4.4
60
80
40
LOAD CURRENT (mA)
4.0
–75 –50 –25
100
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G24
Boost SENSE Pin Total Input
Current vs Temperature
900
200
800
180
700
VOUT > INTVCC + 0.5V
500
400
300
200
0
–75 –50 –25
VIN = 12V
160
600
100
0
5.2
Buck SENSE1– Pin Input Bias
Current vs Temperature
600
INTVCC
5.4
7812 G23
SENSE Pins Total Input Current
vs VSENSE Voltage
700
5.6
4.2
VBIAS = 12V
SENSE CURRENT (µA)
0
4.0
7812 G22
0
7812 G21
FIGURE 9 CIRCUIT
VIN = 8V
VOUT = 12V
IOUT = 0mA
5.3
800
5µs/DIV
FIGURE 9 CIRCUIT
VIN = 8V
VOUT = 12V
IOUT = 1mA
5.4
5.0
2V/DIV
FIGURE 9 CIRCUIT
VIN = 18V
VOUT = 12V
IOUT = 1mA
5.4
INTVCC VOLTAGE (V)
RUN PINS
PULSE-SKIPPING MODE
PULSE-SKIPPING MODE
5.5
2V/DIV
VOUT
Burst Mode
OPERATION
Burst Mode OPERATION
IL1
2A/DIV
5µs/DIV
Start-Up
SENSE2+ PIN
140
120
100
80
60
40
VOUT < INTVCC – 0.5V
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G26
20
0
–75 –50 –25
SENSE2– PIN
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G27
7812fa
8
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LTC7812
Typical Performance Characteristics
70
60
BOOST
50
BUCK
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
Maximum Current Sense
Threshold vs ITH Voltage
60
6.00
DUTY CYCLE = 10%
50
5.75
40
30
20
10
0
–10
PULSE-SKIPPING
FORCED CONTINUOUS
Burst Mode OPERATION
–20
–30
0
0.2
0.4
7812 G28
0.6 0.8
ITH (V)
1
1.2
5.50
5.25
5.00
4.75
4.50
4.25
1.4
4.00
–75 –50 –25
7812 G29
Quiescent Current vs Temperature
25
VBIAS = 12V
80
70
16
14
12
10
8
20
QUIESCENT CURRENT (µA)
SHUTDOWN CURRENT (µA)
18
15
10
5
6
60
50
40
BOTH CHANNELS ON
30
20
CHANNEL 1 ON
10
4
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
0
5
7812 G31
10
15
20
25
30
VBIAS INPUT VOLTAGE (V)
35
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G32
7812 G33
600
550
FREQUENCY (kHz)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
40
Oscillator Frequency
vs Temperature
Buck Foldback Current Limit
MAXIMUM CURRENT SENSE VOLTAGE (mV)
SHUTDOWN CURRENT (µA)
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G30
Shutdown Current
vs Input Voltage
Shutdown Current vs Temperature
20
TRACK/SS1 and SS2 Pull-Up Current
vs Temperature
TRACK/SS CURRENT (µA)
80
MAXIMUM CURRENT SENSE VOLTAGE (mV)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Maximum Current Sense
Threshold vs Duty Cycle
500
450
400
350
0
100 200 300 400 500 600 700 800
VFB1 FEEDBACK VOLTAGE (mV)
FREQ = INTVCC
300
–75 –50 –25
7812 G34
FREQ = GND
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G35
7812fa
For more information www.linear.com/LTC7812
9
LTC7812
Typical Performance Characteristics
Undervoltage Lockout Threshold
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
1.40
4.4
4.3
RUN PIN VOLTAGE (V)
INTVCC VOLTAGE (V)
1.35
RISING
4.2
4.1
4.0
3.9
FALLING
3.8
3.7
3.6
1.30
RUN2 RISING
RUN1 RISING
1.25
1.20
RUN2 FALLING
1.15
RUN1 FALLING
1.10
1.05
3.5
3.4
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1.00
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7812 G37
7812 G36
Charge Pump Charging Current
vs Operating Frequency
Charge Pump Charging Current
vs Switch Voltage
100
VBOOST2 = 16V
90 VSW2 = 12V
–55°C
80
70
CHARGE PUMP CHARGING CURRENT (µA)
CHARGE PUMP CHARGING CURRENT (µA)
100
25°C
60
50
40
150°C
30
20
10
0
100
200 300 400 500 600 700
OPERATING FREQUENCY (kHz)
800
VBOOST2 – VSW2 = 4V
90
FREQ = 0V
80
70
FREQ = INTVCC
60
50
40
30
20
10
0
5
7812 G38
10
15
20
25
30
SWITCH VOLTAGE (V)
35
40
7812 G39
7812fa
10
For more information www.linear.com/LTC7812
LTC7812
Pin Functions
SW1, SW2 (Pins 1, 30): Switch Node Connections to
Inductors.
TG1, TG2, (Pins 2, 29): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTVCC superimposed
on the switch node voltage SW.
PGOOD1 (Pin 3): Open-Drain Logic Output. PGOOD1 is
pulled to ground when the voltage on the VFB1 pin is not
within ±10% of its set point.
TRACK/SS1, SS2 (Pins 4,11): External Tracking and SoftStart Input. For the buck channel, the LTC7812 regulates
the VFB1 voltage to the smaller of 0.8V or the voltage on
the TRACK/SS1 pin. For the boost channel, the LTC7812
regulates the VFB2 voltage to the smaller of 1.2V or the
voltage on the SS2 pin. An internal 5µA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time to final regulated output voltage.
Alternatively, a resistor divider on another voltage supply
connected to the TRACK/SS1 pin allow the LTC7812 buck
output to track another supply during start-up.
ITH1, ITH2 (Pins 5, 15): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associated
channel’s current comparator trip point increases with
this control voltage.
VFB1, VFB2 (Pins 6, 14): Receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SENSE1+, SENSE2+ (Pins 7, 12): The (+) Input to the
Differential Current Comparators. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins
in conjunction with RSENSE set the current trip threshold.
For the boost channel, the SENSE2+ pin supplies current
to the current comparator.
SENSE1–, SENSE2– (Pins 8, 13): The (–) Input to the Differential Current Comparators. When SENSE1– is greater
than INTVCC, then SENSE1– pin supplies current to the
current comparator for the buck channel.
FREQ (Pin 9): The Frequency Control Pin for the Internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz.
Other frequencies between 50kHz and 900kHz can be
programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
PLLIN/MODE (Pin 10): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 and BG2 signals to be synchronized with the rising edge of the external clock, and
the regulators operate in forced continuous mode. When
not synchronizing to an external clock, this input, which
acts on both controllers, determines how the LTC7812
operates at light loads. Pulling this pin to ground selects
Burst Mode operation. An internal 100k resistor to ground
also invokes Burst Mode operation when the pin is floated.
Tying this pin to INTVCC forces continuous inductor current
operation. Tying this pin to a voltage greater than 1.2V and
less than INTVCC – 1.3V selects pulse-skipping operation.
This can be done by connecting a 100k resistor from this
pin to INTVCC.
SGND (Pins 16, 18, 20, 21): Small Signal Ground common to both controllers. All four pins must be tied together
near the LTC7812 and must be routed separately from
high current grounds to the common (–) terminals of the
CIN capacitors.
RUN1, RUN2 (Pins 17, 19): Run Control Inputs for Each
Controller. Forcing RUN1 below 1.17V and RUN2 below
1.20V shuts down that controller. Forcing both of these
pins below 0.7V shuts down the entire LTC7812, reducing
quiescent current to approximately 10µA.
7812fa
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11
LTC7812
Pin Functions
OV2 (Pin 22): Overvoltage Open-Drain Logic Output for
the Boost Regulator. OV2 is pulled to ground when the
voltage on the VFB2 pin is under 110% of its set point, and
becomes high impedance when VFB2 goes over 110% of
its set point.
VBIAS (Pin 26): Main Bias Input Supply Pin. A bypass capacitor should be tied between this pin and the SGND pins.
NC (Pin 23): No Connect. No external connection is required. This pin may be left floating or tied to another node.
BOOST1, BOOST2 (Pins 32, 28): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTVCC pins. Voltage swing
at the BOOST1 pin is from INTVCC to (VIN + INTVCC) and
at the BOOST2 pin is from INTVCC to (VOUT + INTVCC).
INTVCC (Pin 24): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered
from this voltage source. Must be decoupled to PGND
with a minimum of 4.7µF ceramic or tantalum capacitor.
EXTVCC (Pin 25): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VBIAS whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in the
Applications Information section. Do not float or exceed
14V on this pin.
BG1, BG2 (Pins 31, 27): High Current Gate Drives for
Bottom N-Channel MOSFETs. Voltage swing at these pins
is from ground to INTVCC.
PGND (Exposed Pad Pin 33): Driver Power Ground. Connects to the sources of bottom N-channel MOSFETs and the
(–) terminal(s) of CIN. The exposed pad must be soldered
to the PCB for rated electrical and thermal performance.
7812fa
12
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For more information www.linear.com/LTC7812
4.7V
EXTVCC
VBIAS
+
–
PLLIN/MODE
FREQ
LDO
LDO
EN
5.4V
SGND
SYNC
DET
CLP
VCO
5.4V
EN
100k
20µA
+
–
+
–
CLK
INTVCC
PFD
0.72V
VFB1
0.88V
6.8V
RUN1
Q
R
11V
7µA
SHDN
RST
2(VFB)
+
–
BOT
FOLDBACK
SLEEP
SHDN
TOPON
+
– –+
ICMP
Q
S
DROPOUT
DET
SLOPE COMP
2.8V
0.65V
BUCK CHANNEL 1
3mV
–+
PGOOD1
OV
+
–
SHDN
+
–
–
EA +
+
IR
SWITCHING
LOGIC
5µA
0.88V
PGND
BG1
SW1
TG1
3859al FDa
TRACK/SS1
ITH1
VFB1
SENSE1–
SENSE1+
INTVCC
0.80V
TRACK/SS
BOT
TOP
BOOST1
CSS
CB
DB
INTVCC
L
RB
D
CC2
CC
RA
VIN1
RC
RSENSE
COUT
CIN
VOUT1
LTC7812
Functional Diagram
7812fa
13
14
OV2
+
–
VFB2
1.32V
PLLIN/MODE
CLK
RUN2
Q
For more information www.linear.com/LTC7812
11V
160nA
SHDN
+
–
SNSLO
5µA
OV
+
–
2mV
1.32V
+
–
3859al FDb
SS2
ITH2
VFB2
SENSE2+
SENSE2–
PGND
BG2
SW2
TG2
BOOST2
INTVCC
1.2V
SS2
BOT
TOP
–
EA +
+
2V
IR
SWITCHING
LOGIC
+
+– –
SLEEP
SHDN
BOTON
SNSLO
+
– –+
ICMP
0.425V
Q
S
R
SLOPE COMP
2.8V
0.7V
BOOST CHANNEL 2
CSS
CB
DB
INTVCC
L
RB
CC2
CC
RA
VOUT2
RC
RSENSE
CIN
COUT
VOUT2
VIN2
LTC7812
functional diagram
7812fa
LTC7812
Operation
(Refer to Functional Diagram)
Main Control Loop
The LTC7812 uses a constant frequency, current mode
control architecture. Channel 1 is a buck (step-down)
controller and channel 2 is a boost (step-up) controller. During normal operation, the external top MOSFET
for the buck channel (the external bottom MOSFET for
the boost channel) is turned on when the clock for that
channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin, (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground) to
the internal 0.800V reference voltage for the buck (1.2V
reference voltage for the boost). When the load current
increases, it causes a slight decrease in VFB relative to
the reference, which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
After the top MOSFET for the buck (the bottom MOSFET
for the boost) is turned off each cycle, the bottom MOSFET
is turned on (the top MOSFET for the boost) until either
the inductor current starts to reverse, as indicated by the
current comparator IR, or the beginning of the next clock
cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, the VBIAS LDO (low dropout linear regulator)
supplies 5.4V from VBIAS to INTVCC. If EXTVCC is taken
above 4.7V, the VBIAS LDO is turned off and an EXTVCC
LDO is turned on. Once enabled, the EXTVCC LDO supplies
5.4V from EXTVCC to INTVCC. Using the EXTVCC pin allows
the INTVCC power to be derived from a high efficiency
external source such as one of the LTC7812 switching
regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each
cycle through an external diode when the switch voltage
goes low.
For buck channel 1 if the buck’s input voltage decreases to
a voltage close to its output, the loop may enter dropout
and attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one twelfth of the clock period every tenth
cycle to allow CB to recharge. This gives TG1 an effective
duty cycle of 99% in dropout.
Shutdown and Start-Up (RUN1, RUN2, and TRACK/SS1,
SS2 Pins)
The two channels of the LTC7812 can be independently
shut down using the RUN1 and RUN2 pins. Pulling RUN1
below 1.17V or RUN2 below 1.20V shuts down the main
control loop for that channel. Pulling both pins below
0.7V disables both controllers and most internal circuits,
including the INTVCC LDOs. In this state, the LTC7812
draws only 10µA of quiescent current.
Releasing a RUN pin allows a small internal current to pull
up the pin to enable that controller. The RUN1 pin has a 7µA
pull-up current while the RUN2 pin has a smaller 160nA.
The 7µA current on RUN1 is designed to be large enough
so that the RUN1 pin can be safely floated (to always enable the controller) without worry of condensation or other
small board leakage pulling the pin down. This is ideal for
always-on applications where one or both controllers are
enabled continuously and never shut down. If it is desired
that both channels remain on always, RUN2 can be tied
to RUN1 with the connection floated.
Each RUN pin may also be externally pulled up or driven
directly by logic. When driving a RUN pin with a low impedance source, do not exceed the absolute maximum rating
of 8V. Each RUN pin has an internal 11V voltage clamp
that allows the RUN pin to be connected through a resistor
to a higher voltage (for example, VBIAS), so long as the
maximum current in the RUN pin does not exceed 100µA.
The start-up of each channel’s output voltage VOUT is controlled by the voltage on the TRACK/SS pin (TRACK/SS1
for channel 1, SS2 for channel 2). When the voltage on
7812fa
For more information www.linear.com/LTC7812
15
LTC7812
operation
the TRACK/SS pin is less than the 0.8V internal reference
for the buck and the 1.2V internal reference for the boost,
the LTC7812 regulates the VFB voltage to the TRACK/SS
pin voltage instead of the corresponding reference voltage.
This allows the TRACK/SS pin to be used to program a softstart by connecting an external capacitor from the TRACK/
SS pin to SGND. An internal 5µA pull-up current charges
this capacitor creating a voltage ramp on the TRACK/SS
pin. As the TRACK/SS voltage rises linearly from 0V to
0.8V/1.2V (and beyond up to INTVCC), the output voltage
VOUT rises smoothly from zero to its final value.
Alternatively the TRACK/SS pin for buck channel 1 can be
used to cause the start-up of VOUT to track that of another
supply. Typically, this requires connecting to the TRACK/
SS pin an external resistor divider from the other supply to
ground (see the Applications Information section).
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Forced Continuous Conduction)
(PLLIN/MODE Pin)
The LTC7812 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/ MODE
pin to ground. To select forced continuous operation, tie
the PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTVCC – 1.3V.
When a controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage (30% for the
boost) even though the voltage on the ITH pin indicates a
lower value. If the average inductor current is higher than
the load current, the error amplifier EA will decrease the
voltage on the ITH pin. When the ITH voltage drops below
0.425V, the internal sleep signal goes high (enabling sleep
mode) and both external MOSFETs are turned off. The ITH
pin is then disconnected from the output of the EA and
parked at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7812 draws. If
the buck channel 1 is in sleep mode and the boost channel
2 is shut down, the LTC7812 draws only 28µA of quiescent current. If both channels are in sleep mode, it draws
only 33µA of quiescent current. In sleep mode, the load
current is supplied by the output capacitor. As the output
voltage decreases, the EA’s output begins to rise. When the
output voltage drops enough, the ITH pin is reconnected
to the output of the EA, the sleep signal goes low, and the
controller resumes normal operation by turning on the top
external MOSFET on the next cycle of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET (the top external MOSFET for the boost) just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the controller
operates in discontinuous operation.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
the Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantage of lower output
voltage ripple and less interference to audio circuitry. In
forced continuous mode, the output ripple is independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC7812 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
7812fa
16
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LTC7812
Operation
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC7812’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTVCC, or programmed through an external resistor.
Tying FREQ to SGND selects 350kHz while tying FREQ to
INTVCC selects 535kHz. Placing a resistor between FREQ
and SGND allows the frequency to be programmed between
50kHz and 900kHz as shown in Figure 7.
A phase-locked loop (PLL) is available on the LTC7812
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC7812’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of TG1 and BG2 to the rising edge of the synchronizing signal.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop filter allows the PLL to lock in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC7812’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guarantee over all manufacturing variations to be between
75kHz and 850kHz. In other words, the LTC7812’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Boost Controller Operation When VIN > VOUT
When the input voltage to the boost channel rises above
its regulated VOUT voltage, the controller can behave differently depending on the mode, inductor current and
VIN voltage. In forced continuous mode, the loop works
to keep the top MOSFET on continuously once VIN rises
above VOUT. An internal charge pump delivers current to
the boost capacitor from the BOOST2 pin to maintain a
sufficiently high TG voltage. (The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.)
In pulse-skipping mode, if VIN is between 100% and 110%
of the regulated VOUT voltage, TG2 turns on if the inductor
current rises above approximately 3% of the programmed
ILIM current. If the part is programmed in Burst Mode
operation under this same VIN window, then TG2 turns
on at the same threshold current as long as the chip is
awake (the buck channel is awake and switching). If the
buck channel is asleep or shut down in this VIN window,
then TG2 will remain off regardless of the inductor current.
If VIN rises above 110% of the regulated VOUT voltage in
any mode, the controller turns on TG2 regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the entire chip is asleep
(the buck channel is asleep or shut down). With the charge
pump off, there would be nothing to prevent the boost
capacitor from discharging, resulting in an insufficient
TG2 voltage needed to keep the top MOSFET completely
on. The charge pump turns back on when the chip wakes
up, and it remains on as long as one of the buck channels
is actively switching.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
directly from the SENSE2+ pin and can operate to voltages
as low as 2.5V. Since this is lower than the VBIAS UVLO of
the chip, VBIAS can be connected to the output of the boost
controller, as illustrated in the typical application circuit
in Figure 12. This allows the boost controller to handle
input voltage transients down to 2.5V while maintaining
output voltage regulation. If the SENSE2+ rises back
above 2.5V, the SS2 pin will be released initiating a new
soft-start sequence.
7812fa
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17
LTC7812
operation
Buck Controller Output Overvoltage Protection
Boost Overvoltage Indicator (OV2)
The buck channel has an overvoltage comparator that
guards against transient overshoots as well as other more
serious conditions that may overvoltage its output. When
the VFB1 pin rises by more than 10% above its regulation
point of 0.800V, the top MOSFET is turned off and the
bottom MOSFET is turned on until the overvoltage condition is cleared.
The OV2 pin is an overvoltage indicator that signals whether
the output voltage of the channel 2 boost controller goes
over its programmed regulated voltage. The pin is connected to an open drain of an internal N-channel MOSFET.
The MOSFET turns on and pulls the OV2 pin low when the
VFB2 pin voltage is less than 110% of the 1.2V reference
voltage for the boost channel. The OV2 pin is also pulled
low when the RUN2 pin is low (shut down). When the VFB2
pin voltage goes higher than 110% of the 1.2V reference,
the MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V.
Buck Power Good (PGOOD1)
Channel 1 has a PGOOD1 pin that is connected to an open
drain of an internal N-channel MOSFET. The MOSFET
turns on and pulls the PGOOD1 pin low when the VFB1 pin
voltage is not within ±10% of the 0.8V reference voltage
for the buck channel. The PGOOD1 pin is also pulled low
when the RUN1 pin is low (shut down). When the VFB1
pin voltage is within the ±10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
Buck Foldback Current
When the buck output voltage falls to less than 70% of
its nominal level, foldback current limiting is activated,
progressively lowering the peak current limit in proportion
to the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB1 voltage is keeping up with the
TRACK/SS1 voltage). There is no foldback current limiting
for the boost channel.
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Applications Information
Cascaded Boost+Buck Regulator
SENSE+ and SENSE– Pins
The LTC7812 can be configured to regulate two separate,
completely independent outputs, one boost and one buck.
Or, it can be configured as a cascaded Boost+Buck single
output converter that regulates an output voltage from
an input voltage that can be above, below, or equal to the
output voltage. When cascaded, the input voltage feeds
the boost regulator, which generates an intermediate node
supply (VMID) that then serves as the input to the buck
regulator, which then regulates the output voltage.
The SENSE+ and SENSE– pins are the inputs to the current comparators.
When used as a cascaded Boost+Buck regulator, the
LTC7812 has distinct advantages compared to traditional
single inductor buck-boost regulators. Even though it
requires two inductors, these inductors are individually
smaller and provide inherent filtering at the input and
output, substantially reducing conducted EMI and voltage ripple, thereby requiring less input and output filtering. Even though they are cascaded, the boost and buck
regulators are independently optimized and compensated.
The buck regulator on the output provides a very fast
transient response compared to a buck-boost regulator,
further reducing the amount of output capacitance that is
required. The LTC7812 also features a very low quiescent
current Burst Mode operation which dramatically reduces
power loss and increases efficiency at light loads. Thus,
for those applications that require low EMI, low ripple,
fast transient response, low quiescent current, and/or high
light load efficiency, the LTC7812 cascaded Boost+Buck
regulator provides an excellent solution.
The Typical Application on the first page is a basic LTC7812
application circuit. LTC7812 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption, and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs are selected. Finally, input and output
capacitors are selected.
Buck Controller (SENSE1+/SENSE1–): The common mode
voltage range on these pins is 0V to 28V (absolute maximum), enabling the LTC7812 to regulate a buck output
voltage up to a nominal 24V set point (allowing margin
for tolerances and transients). The SENSE1+ pin is high
impedance over the full common mode range, drawing
at most ±1µA. This high impedance allows the current
comparators to be used in inductor DCR sensing. The
impedance of the SENSE1– pin changes depending on
the common mode voltage. When SENSE1– is less than
INTVCC –0.5V, a small current of less than 1µA flows out
of the pin. When SENSE1– is above INTVCC +0.5V, a higher
current (≈700µA) flows into the pin. Between INTVCC –0.5V
and INTVCC +0.5V, the current transitions from the smaller
current to the higher current.
Boost Controller (SENSE2+/SENSE2–): The common mode
input range for these pins is 2.5V to 38V, allowing the boost
converter to operate from inputs over this full range. The
SENSE2+ pin also provides power to the current comparator and draws about 170µA during normal operation (when
not shut down or asleep in Burst Mode operation). There is
a small bias current of less than 1µA that flows out of the
SENSE2– pin. This high impedance on the SENSE2– pin allows
the current comparator to be used in inductor DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC7812, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing curTO SENSE FILTER
NEXT TO THE CONTROLLER
CURRENT FLOW
INDUCTOR OR RSENSE
7812 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
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LTC7812
Applications Information
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
The current comparators have a maximum threshold
VSENSE(MAX) of 50mV. The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current, IMAX, equal to the peak value less
half the peak-to-peak ripple current, DIL. To calculate the
sense resistor value, use the equation:
RSENSE =
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
VIN1
(VOUT2)
INTVCC
BOOST
LTC7812
TG
RSENSE
SW
VOUT1
(VIN2)
BG
SENSE1+
(SENSE2–)
SENSE1–
(SENSE2+)
CAP
PLACED NEAR SENSE PINS
For applications requiring the highest possible efficiency
at high load currents, the LTC7812 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost several points of efficiency compared to DCR sensing.
7812 F02a
2a. Using a Resistor to Sense Current
VIN1
(VOUT2)
INTVCC
BOOST
INDUCTOR
TG
L
SW
DCR
BG
SENSE1+
(SENSE2–)
SENSE1–
(SENSE2+)
When using the controller in very high duty cycle conditions, the maximum output current level will be reduced
due to the internal compensation required to meet stability criterion for switching regulators operating at greater
than 50% duty factor. A curve is provided in the Typical
Performance Characteristics section to estimate this reduction in peak output current level depending upon the
operating duty factor.
Inductor DCR Sensing
SGND
LTC7812
VSENSE(MAX)
DI
IMAX + L
2
R1
C1*
R2
SGND
7812 F02b
*PLACE C1 NEAR SENSE PINS
(R1||R2) • C1 = L/DCR
RSENSE(EQ) = DCR(R2/(R1+R2))
VOUT1
(VIN2)
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
2b. Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
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Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
R(EQUIV) =
VSENSE(MAX)
DI
IMAX + L
2
To ensure that the application will deliver full load current over the full operating temperature range, determine
RSENSE(EQUIV), keeping in mind that the maximum current
sense threshold (VSENSE(MAX)) for the LTC7812 is fixed
at 50mV.
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1||R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1µA current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1 R2 =
(DCR at 20°C) • C1
The sense resistor values are:
R1
(VOUT(MAX) − VIN ) • VIN
R1
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current DIL decreases with higher
inductance or frequency. For the buck controller, DIL
increases with higher VIN:
DIL =
V
1
VOUT 1− OUT
(f)(L)
VIN
For the boost controller, the inductor ripple current DIL
increases with higher VOUT:
The maximum power loss in R1 is related to duty cycle.
For the buck controllers, the maximum power loss will
occur in continuous mode at the maximum input voltage:
(VIN(MAX) − VOUT ) • VOUT
PLOSS R1=
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
R1 R2
R1• RD
R1=
; R2 =
RD
1− RD
PLOSS R1=
For the boost controller, the maximum power loss in R1
will occur in continuous mode at VIN = 1/2•VOUT :
DIL =
1
V
VIN 1− IN
(f)(L) VOUT
Accepting larger values of DIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is DIL = 0.3(IMAX). The maximum
DIL occurs at the maximum input voltage for the buck and
VIN = 1/2•VOUT for the boost.
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The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit (30% for the boost) determined
by RSENSE. Lower inductor values (higher DIL) will cause
this to occur at lower load currents, which can cause a dip
in efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7812: one N-channel MOSFET for the
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the buck).
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Buck Main Switch Duty Cycle =
VIN − VOUT
VIN
−V
V
Boost Main Switch Duty Cycle = OUT IN
VOUT
Buck Sync Switch Duty Cycle =
Boost Sync Switch Duty Cycle =
22
VIN
VOUT
The MOSFET power dissipations at maximum output
current are given by:
PMAIN _ BUCK =
VOUT
IOUT(MAX)
VIN
(
2
) (1+ δ)RDS(ON) +
IOUT(MAX)
(VIN )2
(RDR )(CMILLER ) •
2
1
1
+
(f)
VINTVCC − VTHMIN VTHMIN
V −V
PSYNC _ BUCK = IN OUT IOUT(MAX)
VIN
(
PMAIN _ BOOST =
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5.4V during start-up (see EXTVCC
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. Pay close
attention to the BVDSS specification for the MOSFETs as
well; many of the logic level MOSFETs are limited to 30V
or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
VOUT
VIN
( VOUT − VIN ) VOUT
(1+ δ )RDS(ON) +
VIN
2
2
) (1+ δ)RDS(ON)
(IOUT(MAX) )
2
•
VOUT3 IOUT(MAX)
•
VIN
2
1
1
+
(f)
INTVCC − VTHMIN VTHMIN
2
V
= IN IOUT(MAX) (1+ δ )RDS(ON)
VOUT
(RDR )(CMILLER ) • V
PSYNC _ BOOST
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)
7812fa
LTC7812
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where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N-channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest at
high input voltages for the buck and low input voltages for
the boost. For VIN < 20V (high VIN for the boost) the high
current efficiency generally improves with larger MOSFETs,
while for VIN > 20V (low VIN for the boost) the transition
losses rapidly increase to the point that the use of a higher
RDS(ON) device with lower CMILLER actually provides higher
efficiency. The synchronous MOSFET losses for the buck
controller are greatest at high input voltage when the top
switch duty factor is low or during a short-circuit when
the synchronous switch is on close to 100% of the period.
The synchronous MOSFET losses for the boost controller are greatest when the input voltage approaches the
output voltage or during an overvoltage event when the
synchronous switch is on 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Boost CIN, COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The boost input capacitor CIN
voltage rating should comfortably exceed the maximum
input voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input voltage
for any possible overvoltage transients that could apply
excess stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher the
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current,
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance) and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple due to charging and discharging the bulk
capacitance is given by:
Ripple =
(
IOUT(MAX) • VOUT − VIN(MIN)
COUT • VOUT • f
)V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
DVESR = IL(MAX) • ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
Buck CIN and COUT Selection
The selection of CIN is usually based off the worst-case RMS
input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
IMAX
VIN
( VOUT ) ( VIN − VOUT )1/2
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
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LTC7812
Applications Information
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC7812, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC7812, is also
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
To improve the frequency response, a feedforward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Tracking and Soft-Start (TRACK/SS1, SS2 Pins)
The start-up of each VOUT is controlled by the voltage on
the respective TRACK/SS pin (TRACK/SS1 for channel 1,
SS2 for channel 2). When the voltage on the TRACK/SS
pin is less than the internal 0.8V reference (1.2V reference
for the boost channel), the LTC7812 regulates the VFB pin
voltage to the voltage on the TRACK/SS pin instead of the
internal reference. Likewise, the TRACK/SS1 pin for the
buck channel can be used to program an external softstart function or to allow VOUT to track another supply
during start-up.
1
DVOUT ≈ DIL ESR +
8 • f • COUT
LTC7812
TRACK/SS
where f is the operating frequency, COUT is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
CSS
SGND
7812 F04
Figure 4. Using the TRACK/SS Pin to Program Soft-Start
Setting Output Voltage
The LTC7812 output voltages are each set by an external
feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltages
are determined by:
R
VOUT, BUCK = 0.8V 1+ B
RA
R
VOUT, BOOST = 1.2V 1+ B
RA
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 4.
An internal 5µA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC7812 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
VOUT
1/2 LTC7812
RB
0.8V
5µA
1.2V
= CSS •
5µA
tSS _ BUCK = CSS •
CFF
tSS _ BOOST
VFB
7812 F03
RA
Figure 3. Setting Output Voltage
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VOUT
VX(MASTER)
LTC7812
OUTPUT (VOUT)
RB
VFB1
VOUT(SLAVE)
RA
VX
RTRACKB
TIME
TRACK/SS1
7812 F05a
5a. Coincident Tracking
RTRACKA
7812 F06
OUTPUT (VOUT)
VX(MASTER)
VOUT(SLAVE)
TIME
7812 F05b
5b. Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
Alternatively, the TRACK/SS1 pin for the buck controller can
be used to track another supply during start-up, as shown
qualitatively in Figures 5a and 5b. To do this, a resistor
divider should be connected from the master supply (VX)
to the TRACK/SS pin of the slave supply (VOUT), as shown
in Figure 6. During start-up VOUT will track VX according
to the ratio set by the resistor divider:
R
+ RTRACKB
VX
RA
=
• TRACKA
VOUT RTRACKA
RA + RB
For coincident tracking (VOUT = VX during start-up),
RA = RTRACKA
RB = RTRACKB
Figure 6. Using the TRACK/SS Pin for Tracking
INTVCC Regulators
The LTC7812 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the INTVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connection of the EXTVCC
pin. INTVCC powers the gate drivers and much of the
LTC7812’s internal circuitry. The VBIAS LDO and the EXTVCC LDO regulate INTVCC to 5.4V. Each of these must
be bypassed to ground with a minimum of 4.7µF ceramic
capacitor. No matter what type of bulk capacitor is used, an
additional 1µF ceramic capacitor placed directly adjacent
to the INTVCC and PGND IC pins is highly recommended.
Good bypassing is needed to supply the high transient
currents required by the MOSFET gate drivers and to
prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7812 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.7V, the VBIAS LDO is enabled. Power
dissipation for the IC in this case is highest and is equal to
VBIAS • IINTVCC. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated
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LTC7812
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by using the equations given in Note 2 of the Electrical
Characteristics. For example, the LTC7812 INTVCC current
is limited to less than 33mA from a 38V supply when not
using the EXTVCC supply at a 70°C ambient temperature
in the QFN package:
The following list summarizes the four possible connections for EXTVCC:
TJ = 70°C + (33mA)(38V)(44°C/W) = 125°C
2.EXTVCC connected directly to the output voltage of one
of the buck regulators. This is the normal connection
for a 5V to 14V regulator and provides the highest efficiency.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VBIAS LDO is turned off and the EXTVCC LDO is enabled.
The EXTVCC LDO remains on as long as the voltage applied
to EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.4V, so while EXTVCC
is less than 5.4V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.4V, up to an absolute maximum of 14V,
INTVCC is regulated to 5.4V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC7812’s
switching regulator outputs (4.7V ≤ VOUT ≤ 14V) during normal operation and from the VBIAS LDO when the
output is out of regulation (e.g., startup, short-circuit). If
more current is required through the EXTVCC LDO than
is specified, an external Schottky diode can be added
between the EXTVCC and INTVCC pins. In this case, do
not apply more than 6V to the EXTVCC pin and make sure
that EXTVCC ≤ VBIAS.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the buck output, since the VIN
current resulting from the driver and control currents will
be scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
a 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (33mA)(8.5V)(44°C/W) = 82°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
1.EXTVCC grounded. This will cause INTVCC to be powered
from the internal 5.4V regulator resulting in an efficiency
penalty of up to 10% at high input voltages.
3.EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC ≤ VBIAS.
4.EXTVCC connected to an output-derived boost network
off one of the buck regulators. For 3.3V and other low
voltage buck regulators, efficiency gains can still be
realized by connecting EXTVCC to an output-derived
voltage that has been boosted to greater than 4.7V.
Ensure that EXTVCC ≤ VBIAS.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFETs is to be turned
on, the driver places the CB voltage across the gate-source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage,
SW, rises to VIN for the buck channel (VOUT for the boost
channel) and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC (VBOOST = VOUT + VINTVCC for the
boost controller). The value of the boost capacitor CB
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX) for
the buck channels and VOUT(MAX) for the boost channel.
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The external diode DB can be a Schottky diode or silicon
diode, but in either case it should have low leakage and fast
recovery. Pay close attention to the reverse leakage at high
temperatures where it generally increases substantially.
The topside MOSFET driver for the boost channel includes
an internal charge pump that delivers current to the
bootstrap capacitor from the BOOST2 pin. This charge
current maintains the bias voltage required to keep the
top MOSFET on continuously during dropout/overvoltage conditions. The Schottky/silicon diode selected for
the boost topside driver should have a reverse leakage
less than the available output current the charge pump
can supply. Curves displaying the available charge pump
current under different operating conditions can be found
in the Typical Performance Characteristics section.
A leaky diode DB in the boost converter can not only
prevent the top MOSFET from fully turning on but it can
also completely discharge the bootstrap capacitor CB and
create a current path from the input voltage to the BOOST2
pin to INTVCC. This can cause INTVCC to rise if the diode
leakage exceeds the current consumption on INTVCC . This
is particularly a concern in Burst Mode operation where
the load on INTVCC can be very small. There is an internal
voltage clamp on INTVCC that prevents the INTVCC voltage
from running away, but this clamp should be regarded
as a failsafe only. The external Schottky or silicon diode
should be carefully chosen such that INTVCC never gets
charged up much higher than its normal regulation voltage.
Care should also be taken when choosing the external
diode DB for the buck controller. A leaky diode not only
increases the quiescent current of the buck converter, but
it can also cause a similar leakage path to INTVCC from
VOUT for applications with output voltages greater than
the INTVCC voltage (~5.4V).
Fault Conditions: Buck Current Limit and Current
Foldback
The LTC7812 includes current foldback for the buck
channels to help limit load current when the output is
shorted to ground. If the buck output falls below 70% of
its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 40% of its
maximum selected value. Under short-circuit conditions
with very low duty cycles, the buck channel will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time tON(MIN) of the LTC7812 (≈95ns), the input voltage
and inductor value:
DIL(SC) = tON(MIN) (VIN/L)
The resulting average short-circuit current is:
1
I = 40% • I
LIM(MAX) − DIL(SC)
SC
2
Fault Conditions: Buck Overvoltage Protection
(Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the buck regulator rises much higher than nominal levels. The crowbar
causes huge currents to flow, that blow the fuse to protect
against a shorted top MOSFET if the short occurs while
the controller is operating.
A comparator monitors the buck output for overvoltage
conditions. The comparator detects faults greater than
10% above the nominal output voltage. When this condition is sensed, the top MOSFET of the buck controller is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared. The bottom MOSFET
remains on continuously for as long as the overvoltage
condition persists; if VOUT returns to a safe level, normal
operation automatically resumes.
A shorted top MOSFET for the buck channel will result in
a high current condition which will open the system fuse.
The switching regulator will regulate properly with a leaky
top MOSFET by altering the duty cycle to accommodate
the leakage.
Fault Conditions: Over Temperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
(such as INTVCC short to ground), the over temperature
shutdown circuitry will shut down the LTC7812. When the
junction temperature exceeds approximately 170°C, the
over temperature circuitry disables the INTVCC LDO, causing the INTVCC supply to collapse and effectively shutting
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down the entire LTC7812 chip. Once the junction temperature drops back to approximately 155°C, the INTVCC LDO
turns back on. Long term overstress (TJ > 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks.
Phase-Locked Loop and Frequency Synchronization
Table 1
Table 1 summarizes the different states in which the FREQ
pin can be used.
The LTC7812 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the TG1 and BG1 to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE
pin. The phase detector is an edge sensitive digital type
that provides nearly zero degrees phase shift between
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
Note that the LTC7812 can only be synchronized to an
external clock whose frequency is within range of the
LTC7812’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency correspond to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase-lock
and synchronization. Although it is not required that the
28
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
INTVCC
DC Voltage
535kHz
Resistor to SGND
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase-Locked to
External Clock
1000
900
800
FREQUENCY (kHz)
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage at the VCO input is adjusted until
the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase
detector output is high impedance and the internal filter
capacitor, holds the voltage at the VCO input.
FREQ PIN
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
7812 F07
Figure 7. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC7812 is capable of turning on the top MOSFET
(bottom MOSFET for the boost controller). It is determined
by internal timing delays and the gate charge required to
turn on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that
tON(MIN)_ BUCK <
VOUT
VIN (f)
tON(MIN)_ BOOST <
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VOUT − VIN
VOUT (f)
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If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC7812 is approximately
95ns for the buck and 120ns for the boost. However, as
the peak sense voltage decreases the minimum on-time
gradually increases up to about 130ns. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7812 circuits: 1) IC VBIAS current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1.The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
2.INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTVCC from an output-derived source power
through EXTVCC will scale the VIN current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of INTVCC current results in approximately 2.5mA
of VIN current. This reduces the mid-current loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3.I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For
example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
= 10mΩ and RESR = 40mΩ (sum of both input and
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4.Transition losses apply only to the top MOSFET(s) (bottom MOSFET for the boost), and become significant only
when operating at high input voltages (typically 15V or
greater). Transition losses can be estimated from:
Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
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CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including diode conduction losses during deadtime and inductor core losses generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to DILOAD(ESR), where ESR is the effective
series resistance of COUT. DILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in Figure 9 will provide an
adequate starting point for most applications.
The ITH series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing R and
the bandwidth of the loop will be increased by decreasing
C. If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Buck Design Example
As a design example for the buck channel, assume VIN =
12V(NOMINAL), VIN = 22V(MAX), VOUT = 3.3V, IMAX = 6A,
VSENSE(MAX) = 50mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
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to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
DIL =
VOUT
VOUT
1−
(f)(L) VIN(NOMINAL)
2
PSYNC = (2.23A) (1.125)(0.022Ω) = 233mW
which is less than under full-load conditions.
A 3.9µH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 6.88A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
VOUT
VIN(MAX)(f)
=
3.3V
= 429ns
22V(350kHz)
The RSENSE resistor value can be calculated by using the
minimum value for the maximum current sense threshold
(43mV):
RSENSE ≤
43mV
= 0.006Ω
6.88A
Choosing 1% resistors: RA = 25k and RB = 80.6k yields
an output voltage of 3.33V.
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
3.3V
(6A)2 {1+ (0.005)(50°C − 25°C)}
22V
5A
(0.035Ω) + (22V)2 6 (2.5Ω)(215pF) •
2
1
1
+
(350kHz) = 433mW
5V − 2.3V 2.3V
PMAIN =
A short-circuit to ground will result in a folded back current of:
ISC =
with a typical value of RDS(ON) and z = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
20 mV 1 95ns(22V)
−
= 3.07A
0.006Ω 2 3.9µH
The input capacitor to the buck regulator CIN is chosen
for an RMS current rating of at least 3A at temperature
assuming only this channel is on. COUT is chosen with an
ESR of 0.02Ω for low output ripple. The output ripple in
continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately:
VORIPPLE = RESR (DIL) = 0.02Ω(1.75A) = 35mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 8 illustrates the current waveforms present in
the various branches of the synchronous boost and buck
regulators operating in the continuous mode. Check the
following in your layout:
1.Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The path formed by the top N-channel MOSFET, bottom
N-channel MOSFET and the CIN capacitor should have
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
2.Do the LTC7812 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
3.Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
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4.Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time.
5.Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC7812 and occupy minimum
PC trace area.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
6.Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pins of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the
internal oscillator and probe the actual output voltage as
well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 25% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
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RSENSE1
VIN
L1
SW1
VOUT1
RIN
COUT1
RL1
V
7812 F08a
BOLD LINES INDICATE HIGH SWITCHING CURRENT.
KEEP LINES TO A MINIMUM LENGTH.
Figure 8a. Branch Current Waveforms for Boost Regulator
SW
VIN
RIN
CIN
L
RSENSE
VOUT
COUT
RL
7812 08b
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 8b. Branch Current Waveforms for Buck Regulator
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Compensation and VMID Capacitance in a Cascaded
Boost+Buck Regulator
Choosing the VMID Voltage in a Cascaded Boost+Buck
Regulator
When using the LTC7812 as a cascaded Boost+Buck
regulator, the boost and buck regulator control loops are
compensated individually. While this may seem more
complicated, this is actually advantageous, as the inherently fast buck loop can be designed to handle the output
load transient, while the boost loop is less important and
can be slower.
There are many performance tradeoffs when considering
where to set the VMID (boost output) regulation voltage
(VMID_REG) relative to the input voltage (VIN) range and
output (buck) regulation voltage (VOUT_REG). These tradeoffs include efficiency, quiescent current, switching noise/
EMI, and voltage ripple.
The amount of capacitance needed on the intermediate VMID
node (boost output) and the buck output VOUT depends on
a number of factors, including the input voltage, output
voltage, load current and the nature of any transients,
and the mode of operation (Burst Mode operation, forced
continuous mode, or pulse-skipping mode).
In general, the buck regulator should be designed to
handle any output load transients and provide sufficiently
low output ripple.
The boost regulator does not need to respond as fast, as
the VMID node can tolerate relatively high ripple and/or
transient dips and therefore does not necessarily need a
lot of capacitance. The VMID node capacitance needs to
be able to handle the input ripple current from the buck
regulator. It also needs to be large enough that the boost
regulator’s voltage ripple and/or transient dips do not appear as significant input line steps to the buck regulator
and feed through to the buck regulator’s output.
The ripple on the VMID node is higher in Burst Mode operation and pulse-skipping mode than in forced continuous
mode, especially at light loads and/or if the input voltage
is slightly below the regulated boost output (VMID) voltage. Thus, Burst Mode and pulse-skipping mode generally
require more VMID capacitance than in forced continuous
mode to maintain a similar amount of ripple.
The capacitance on the VMID node can be all ceramic, or
some combination of ceramic and polarized (tantalum,
electrolytic, etc.) capacitors.
Remember that VMID will follow VIN if VIN > VMID_REG (see
the Boost Controller Operation when VIN > VOUT section
in the OPERATION section.) If VIN < VMID_REG, VMID is
regulated to VMID_REG.
Consider as an example an automotive application that
requires a regulated 12V output voltage generated from a
vehicle battery. The battery spends most of its operating
lifetime in a normal range of 10V to 16V, but may dip to
as low as 2.5V during engine start and rise as high as 38V
during high voltage transients.
We can designate the minimum normal operating voltage
as VIN_MIN_OP = 10V, and the maximum normal operating
voltage as VIN_MAX_OP = 16V. So what voltage should we
choose for VMID_REG?
REGULATED OUTPUT VOLTAGE
In this example, note that we want a tightly regulated output
(VOUT_REG = 12V), which is within our normal operating
range (VIN_MIN_OP < VOUT_REG < VIN_MAX_OP). We want
VMID_REG > VOUT_REG to provide headroom for the buck
regulator, but we have a choice of whether to set VMID_REG
above or below VIN_MAX_OP.
OPTION A: VMID_REG > VOUT_REG and VMID_REG >
VIN_MAX_OP
In this option, we set VMID_REG > VIN_MAX_OP (e.g.,
VMID_REG = 18V). Both the boost regulator and the buck
regulator are switching (at full, constant frequency if in
forced continuous mode) over the full 10V to 16V normal operating range. Since the boost regulator is always
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switching, the efficiency is lower and the input ripple and
EMI, while predictable and still low, are higher than other
potential options.
OPTION B: VIN_MIN_OP < VOUT_REG < VMID_REG <
VIN_MAX_OP
This is similar to option A, but VMID_REG is set within the
normal operating input voltage range (e.g., VMID_REG =
14V). When VIN is well below VMID_REG, this option is
like Option A. But as VIN approaches VMID_REG, the boost
controller will gradually begin skipping cycles (even in
forced continuous mode) once it reaches minimum-ontime. If VIN > VMID_REG, then VMID follows VIN. In this
region, OPTION B is more efficient than OPTION A since
the boost is not switching. But this is at the expense of
the cycle-skipping (non-constant frequency ripple) when
VIN is slightly below VMID_REG.
LOOSELY REGULATED OUTPUT (Pass-Through
Regulator)
In some applications, it is not critical that VOUT be tightly
regulated, but rather that it remains within a certain voltage
range. Suppose, in our example, that it is only important
that VOUT be maintained within the normal battery operating
voltage range of 10V to 16V. We can consider a third option:
OPTION C: VMID_REG = VIN_MIN_OP and VOUT_REG =
VIN_MAX_OP
Here we set VMID_REG = VIN_MIN_OP = 10V and VOUT_REG
= VIN_MAX_OP =16V. So the boost regulator only boosts
when VIN < 10V and the buck regulator only bucks when
VIN >16V. When VIN is between 10V to 16V, the circuit is
in a pass-through or wire mode where there is very little
switching. The boost regulator is not boosting (TG2 is on
100% in forced continuous mode) and the buck regulator is
operating in dropout (with TG1 on at an effective 99%duty
cycle.) This makes the circuit very efficient, especially at
heavy loads, with extremely low input and output ripple
and EMI. Note that in this pass-through mode, the circuit
does not benefit from the LTC7812’s ultralow quiescent
current of 33µA in Burst Mode since the buck regulator
does not go to sleep because VOUT < VOUT_REG = 16V.
REGULATED OUTPUT VOLTAGE BELOW NORMAL
INPUT VOLTAGE OPERATING RANGE
In some applications, the desired output voltage might
be less than the minimum normal operating voltage, but
still higher than the worst-case minimum input voltage.
Consider our previous example, but instead suppose we
want VOUT= 5V. In this case, we can set our VMID_REG
such that:
OPTION D: VIN_MIN_OP > VMID_REG > VOUT_REG
So we might set VMID_REG just below 10V, so that the
boost regulator never switches within the normal operating
range and only needs to boost during the input voltage
dips below 10V. The buck controller always regulates the
VOUT to 5V, and the boost regulator’s inductor and VMID
capacitance create a filter that substantially reduces any
input ripple and results in very little conducted EMI on
the input.
Table 1 summarizes some of the performance trade-offs
of these four potential ways to set the VMID regulation
voltage in an LTC7812 cascaded Boost+Buck regulator.
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35
LTC7812
Applications Information
Table 1. Summary of Trade-Offs in Determining the VMID Voltage in a Cascaded Boost+Buck Regulator
A
B
C
D
Option
VMID_REG > VOUT_REG and
VMID_REG > VIN_MAX_OP
VIN_MIN_OP < VOUT_REG <
VMID_REG < VIN_MAX_OP
VMID_REG = VIN_MIN_OP and
VOUT_REG = VIN_MAX_OP
(Pass-Through /Wire Mode)
VIN_MIN_OP > VMID_REG >
VOUT_REG
Example for Normal Input
Operating Range of 10V – 16V
(VIN_MIN_OP = 10V
VIN_MAX_OP = 16) with a Full
Range of 2.5V – 38V
VMID_REG = 18V
VOUT = VOUT_REG = 12V
VMID_REG =14V
VOUT = VOUT_REG = 12V
VMID_REG = 10V
VOUT_REG = 16V
VOUT = 10V – 16V
VMID_REG = 10V
VOUT = VOUT_REG = 5V
Boost Boosting in Normal
Operating Range?
Yes, Over Full Range
Yes, When VIN < VMID_REG
No
No
Buck Bucking in Normal
Operating Range?
Yes, Over Full Range
Yes, Over Full Range
No, in Dropout
Yes, Over Full Range
LTC7812 No-Load Quiescent
Current in
Burst Mode Operation
33µA
33µA
~3mA
33µA
Heavy Load Efficiency
Slightly Lower
High When Not Boosting;
Slightly Lower When Boosting
Highest
High
Input Ripple
Low
Low When Boosting; Very
Low When Not Boosting;
Some Cycle-Skipping During
Transition
Extremely Low
Very Low
Output Ripple
Low
Low
Extremely Low
Low
EMI in Normal Operating
Range
Low
Very Low When Not Boosting;
Low When Boosting
Extremely Low
Very Low
Example for Normal Operating
Range: VIN_MIN_OP = 10V –
VIN_MAX_OP = 16V
VMID_REG = 18V
VOUT = VOUT_REG = 12V
Figure 10
VMID_REG =14V
VOUT = VOUT_REG = 12V
Figure 9
VMID_REG = 10V
VOUT_REG = 16V
VOUT = 10V – 16V
Figure 11
VMID_REG = 10V
VOUT = VOUT_REG = 5V
Figure 12
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36
For more information www.linear.com/LTC7812
LTC7812
Typical Applications
RSENSE2
2mΩ
+
CIN1
33µF
L2, 1µH
MTOP2
CIN2,3
6.8µF
VMID, 14V**
+
MBOT2
CMID5
33µF
CMID1,2,3,4
6.8µF
L1, 4.7µH
MTOP1
RB2
499k
RSENSE1
3mΩ
RB1
499k
MBOT1
RA2
46.4k
+
COUT3
47µF
VOUT
12V
8A*
RA1
35.7k
4.7µF
1000pF
CB2
0.1µF
SENSE2+ SENSE2– BG2
DB2
TG2
SW2 BOOST2
CB1
0.1µF
DB1
PGND
INTVCC
VFB2 VBIAS
TG1 BOOST1
RUN1 RUN2
ITH2
ITH1
TRACK/SS1
SS2
FREQ
COUT1,2
22µF
SW1
BG1
INTVCC
SENSE1+ SENSE1– VFB1
1M
EXTVCC
LTC7812
PGOOD1
PGOOD1
OV2
OV2
PLLIN/MODE SGND
1M
7812 F09a
4.75k
100pF
4.7nF
1k
820pF
CSS1
0.1µF
CSS2
0.01µF
6.8nF
MTOP1, MTOP2, MBOT1, MBOT2: INFINEON BSC027N04LS
L1: WURTH 7443320470
L2: WURTH 7443320100
CIN1, CMID5: KEMET T521X336M050ATE075
COUT3: KEMET T521V476M020ATE055
DB1, DB2: CENTRAL SEMI CMDSH-4E
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
**VMID = 14V WHEN VIN < 14V
VMID FOLLOWS VIN WHEN VIN > 14V
100
100
AMPLITUDE (dBµV)
AMPLITUDE (dBµV)
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
50
0
0
15
FREQUENCY (MHz)
CISPR-25 CONDUCTED EMI MEASUREMENT
VIN = 13.5V, IOUT = 8A
30
7812 F09b
50
0
0
15
FREQUENCY (MHz)
30
CISPR-25 CONDUCTED EMI MEASUREMENT
WITH ADDITIONAL INPUT FILTER (L = 240nH, C = 33µF)
VIN = 13.5V, IOUT = 8A
7812 F09c
Figure 9. Wide Input Range to 12V/8A Low IQ, Cascaded Boost+Buck Regulator (VMID Boosted to 14V)
7812fa
For more information www.linear.com/LTC7812
37
LTC7812
Typical Applications
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
RSENSE2
2mΩ
+
CIN1
33µF
L2, 1µH
MTOP2
CIN2,3
6.8µF
VMID, 16V**
MBOT2
+
CMID5
33µF
CMID1,2,3,4
6.8µF
DB2
SENSE2+ SENSE2– BG2 SW2 BOOST2
RB2
499k
TG2
RA2
40.2k
TRACK/SS1
SS2
VFB2 VBIAS
FREQ
COUT3
47µF
COUT1,2
22µF
CB1
0.1µF
PGND
+
VOUT
12V
8A*
RA1
35.7k
DB1
INTVCC
ITH2
ITH1
RB1
499k
MBOT1
TG1 BOOST1
SW1
BG1
PGOOD1
PLLIN/MODE SGND
INTVCC
SENSE1+ SENSE1– VFB1
EXTVCC
LTC7812
RUN1 RUN2
RSENSE1
3mΩ
4.7µF
CB2
0.1µF
1000pF
L1, 4.7µH
MTOP1
OV2
1M
1M
PGOOD1
OV2
7812 F10
4.75k
4.7nF
100pF
1k
820pF
CSS1
0.1µF
CSS2
0.01µF
6.8nF
MTOP1, MTOP2, MBOT1, MBOT2: INFINEON BSC027N04LS
L1: WURTH 7443320470
L2: WURTH 7443320100
CIN1, CMID5: KEMET T521X336M050ATE075
COUT3: KEMET T521V476M020ATE055
DB1, DB2: CENTRAL SEMI CMDSH-4E
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
**VMID = 16V WHEN VIN < 16V
VMID FOLLOWS VIN WHEN VIN > 16V
Figure 10. Wide Input Range to 12V/8A Low IQ, Cascaded Boost+Buck Regulator (VMID = 16V)
7812fa
38
For more information www.linear.com/LTC7812
LTC7812
Typical Applications
RSENSE2
2mΩ
+
CIN1
33µF
L2, 1µH
MTOP2
CIN2,3
6.8µF
VMID, 10V***
MBOT2
+
CMID5
33µF
CMID1,2,3,4
6.8µF
L1, 4.7µH
MTOP1
RB2
499k
RSENSE1
3mΩ
CB2
0.1µF
1000pF
SENSE2+ SENSE2– BG2
DB2
MBOT1
RA2
68.1k
RA1
26.1k
SW2 BOOST2 TG2
INTVCC
PGND
VFB2 VBIAS
TG1 BOOST1
SW1
BG1
ITH2
ITH1
TRACK/SS1
SS2
FREQ
COUT3
47µF
INTVCC
SENSE1+ SENSE1– VFB1
EXTVCC
LTC7812
RUN1 RUN2
+
COUT1,2
22µF
CB1
0.1µF
DB1
VOUT
10V TO 16V*
8A**
RB1
499k
4.7µF
PGOOD1
OV2
PLLIN/MODE SGND
1M
1M
PGOOD1
OV2
7812 F11a
4.75k
4.7nF
100pF
1k
820pF
CSS1
0.1µF
CSS2
0.01µF
6.8nF
MTOP1, MTOP2, MBOT1, MBOT2: INFINEON BSC027N04LS
L1: WURTH 7443320470
L2: WURTH 7443320100
CIN1, CMID5: KEMET T521X336M050ATE075
COUT3: KEMET T521V476M020ATE055
DB1, DB2: CENTRAL SEMI CMDSH-4E
*VOUT = 10V WHEN VIN < 10V
VOUT = 16V WHEN VIN > 16V
VOUT FOLLOWS VIN WHEN VIN IS 10V TO 16V
**WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
***VMID = 10V WHEN VIN < 10V
VMID FOLLOWS VIN WHEN VIN > 10V
100
AMPLITUDE (dBµV)
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
50
0
0
15
FREQUENCY (MHz)
CISPR-25 CONDUCTED EMI MEASUREMENT
VIN = 13.5V, IOUT = 8A
30
7812 F11b
Figure 11. Wide Input Range Pass-Through Cascaded Boost+Buck Regulator
7812fa
For more information www.linear.com/LTC7812
39
LTC7812
typical Applications
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
RSENSE2
2mΩ
+
L2, 1.2µH
MTOP2
CIN1
220µF
VMID, 10V*
MBOT2
+
L1, 4.9µH
MTOP1
RB2
499k
CMID1
220µF
RSENSE1
6mΩ
RB1
375k
MBOT1
RA2
68.1k
+
COUT1
220µF
VOUT
5V
5A
RA1
68.1k
4.7µF
CB2
0.1µF
1000pF
SENSE2+ SENSE2– BG2
DB2
TG2
SW2 BOOST2
CB1
0.1µF
DB1
INTVCC
PGND
VFB2 VBIAS
TG1 BOOST1
SW1
ITH2
ITH1
TRACK/SS1
SS2
FREQ
PGOOD1
OV2
PLLIN/MODE SGND
INTVCC
SENSE1+ SENSE1– VFB1
EXTVCC
LTC7812
RUN1 RUN2
BG1
1M
1M
PGOOD1
OV2
7812 F12a
15k
100pF
1.5nF
3.6k
820pF
CSS1
0.1µF
CSS2
0.01µF
10nF
MTOP1, MBOT1: INFINEON BSZ097N04LS
MTOP2, MBOT2: INFINEON BSC027N04LS
L1: WURTH 744314490
L2: WURTH 744325120
CIN1, CMID1: SUNCON 50CE220LX
COUT1: SANYO 6TPB220ML
DB1, DB2: CENTRAL SEMI CMDSH-4E
*VMID = 10V WHEN VIN < 10V
VMID FOLLOWS VIN WHEN VIN > 10V
AMPLITUDE (dBµV)
100
50
0
0
15
FREQUENCY (MHz)
CISPR-25 CONDUCTED EMI MEASUREMENT
VIN = 13.5V, IOUT = 8A
30
7812 F12b
Figure 12. Wide Input Range to 5V/5A Low IQ Cascaded Boost + Buck Regulator (VMID Boosted to 10V)
7812fa
40
For more information www.linear.com/LTC7812
LTC7812
typical Applications
820pF
SENSE2+
15k
ITH1
SENSE2–
COUT3,4,5,6
22µF
C7
1000pF
+
VOUT2
24V
5A*
COUT7
220µF
150pF
MTOP2
TG2
15nF
L2, 3.5µH
SW2
8.66k
CB2, 0.1µF
ITH2
RSENSE2
BOOST2
220pF
VIN
5V TO 24V
4mΩ
CIN2,3
6.8µF
+
CIN1
33µF
LTC7812
MBOT2
BG2
CSS1, 0.1µF
TRACK/SS1
VFB2
CSS2, 0.1µF
SS2
RB2
232k
DB2
RA2
12.1k
INTVCC
DB1
FREQ
4.7µF
PGND
PLLIN/MODE
VBIAS
EXTVCC
MTOP1
TG1
SGND
BOOST1
CB1, 0.1µF
PGOOD1
PGOOD1
L1
3.3µH
SW1
RSENSE1
6mΩ
1M
BG1
OV2
OV2
COUT1
100µF
MBOT1
+
VOUT1
3.3V
5A
COUT2
150µF
1M
INTVCC
SENSE1+
SENSE1–
RB1
215k
VFB1
RA1
68.1k
7812 F13
MTOP1, MBOT1: INFINEON BSZ097N04LS
MTOP2, MBOT2: INFINEON BSC027N04LS
L1: WURTH 744325330
L2: WURTH 7443556350
CIN1: KEMET T521X336M050ATE075
COUT2: KEMET T520B157M004ATE015
COUT7: SUNCON 50CE220LX
DB1, DB2: CENTRAL SEMI CMDSH-4E
PINS NOT USED IN THIS
CIRCUIT: RUN1, RUN2
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
Figure 13. High Efficiency, 5V to 24V, VIN to 24V/5A and 3.3V/5A DC/DC Regulator
7812fa
For more information www.linear.com/LTC7812
41
LTC7812
Package Description
Please refer to http://www.linear.com/product/LTC7812#packaging for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
7812fa
42
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC7812
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
LTC7812
Revision History
REV
DATE
DESCRIPTION
A
06/16
Changed graph, Efficiency vs Load Current, VIN = 18V
PAGE NUMBER
6
Corrected Figure 13
41
7812fa
For more information www.linear.com/LTC7812
43
LTC7812
Typical Application
Low EMI, Wide Input Range Pass-Through Cascaded Boost+Buck Regulator
VIN
5V TO 38V
DOWN TO
2.5V AFTER
START-UP
RSENSE2
2m
+
CIN1
33µF
L2, 1µH
MTOP2
CIN2,3
6.8µF
VMID, 10V***
MBOT2
+
L1, 4.7µH
MTOP1
RB2
499k
CMID5
33µF
CMID1,2,3,4
6.8µF
RSENSE1
3m
MBOT1
RA2
68.1k
RA1
26.1k
4.7µF
CB2
0.1µF
1000pF
SENSE2+ SENSE2– BG2
DB2
SW2 BOOST2 TG2
PGND
INTVCC
VFB2 VBIAS
TG1 BOOST1
SW1
BG1
ITH2
ITH1
TRACK/SS1
SS2
FREQ
COUT3
47µF
INTVCC
SENSE1+ SENSE1– VFB1
EXTVCC
LTC7812
RUN1 RUN2
+
COUT1,2
22µF
CB1
0.1µF
DB1
VOUT
10V TO 16V*
8A**
RB1
499k
1M
PGOOD1
PLLIN/MODE SGND
OV2
1M
PGOOD1
OV2
7812 TA02
4.75k
1k
100pF
4.7nF
820pF
CSS1
0.1µF
CSS2
0.01µF
6.8nF
MTOP1, MTOP2, MBOT1, MBOT2: INFINEON BSC027N04LS
L1: WURTH 7443320470
L2: WURTH 7443320100
CIN1, CMID5: KEMET T521X336M050ATE075
COUT3: KEMET T521V476M020ATE055
DB1, DB2: CENTRAL SEMI CMDSH-4E
*VOUT = 10V WHEN VIN < 10V
VOUT = 16V WHEN VIN > 16V
VOUT FOLLOWS VIN WHEN VIN IS 10V TO 16V
**WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
***VMID = 10V WHEN VIN < 10V
VMID FOLLOWS VIN WHEN VIN > 10V
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTM4609
36VIN, 34VOUT, Buck-Boost µModule Regulator
4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, Up to 4A, 15mm × 15mm LGA and
BGA Packages
LTM8056
58VIN, 48VOUT, Buck-Boost µModule Regulator
5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, Up to 5.4A, 15mm × 15mm × 4.92mm
BGA Package
LTC3789
High Efficiency Synchronous 4-Switch Buck-Boost
Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, 4mm × 5mm QFN-28, SSOP-28
LT3790
60V 4-Switch Synchronous Buck-Boost Controller
4.7V ≤ VIN ≤ 60V, 1.2V ≤ VOUT ≤ 60V, TSSOP-38
LT8705
80V VIN and VOUT Synchronous 4-Switch Buck-Boost
DC/DC Controller
2.8V ≤ VIN ≤ 80V, 1.3V ≤ VOUT ≤ 80V, Regulates VOUT, IOUT, VIN, IIN, 5mm
× 7mm QFN-38, Modified TSSOP Package for High Voltage
LTC3786
Low IQ Synchronous Step-Up DC/DC Controller
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, IQ = 55µA
PLL Fixed Frequency 50kHz to 900kHz, 3mm × 3mm QFN-16, MSOP-16E
LTC3787
Low IQ, Multiphase, Dual Channel Single Output
Synchronous Step-Up DC/DC Controller
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT up to 60V, PLL Fixed
Frequency 50kHz to 900kHz, IQ = 135µA
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC Controller
with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50µA
LTC3899
60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 29µA Burst Mode IQ
4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck
VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V
LTC3859AL
38V, Low IQ, Triple Output, Buck/Buck/Boost Synchronous
Controller with 28µA Burst Mode IQ
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, Buck
VOUT Range: 0.8V to 24V, Boost VOUT Up to 60V
LTC3892/
LTC3892-1
60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC 4.5V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, 5mm × 5mm QFN-32,
Controller with 29µA Burst Mode IQ
TSSOP-28 Packages
7812fa
44 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC7812
(408) 432-1900 ● FAX: (408) 434-0507
●
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LT 0616 REV A • PRINTED IN USA
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