® EL2072 UCT T PROD ACEMEN at E T L E r L P e E O t n OBS NDED R port Ce /tsc E p m M u o S c ECOM echnical .intersil. December 1995, Rev. E w NO R Data T Sheet w r u w o r ct Lo a I t S n o R c -INTE 1-888 FN7033 730MHz Closed Loop Buffer Features The EL2072 is a wide bandwidth, fast settling monolithic buffer built using an advanced complementary bipolar process. This buffer is closed loop to achieve lower output impedance and higher gain accuracy. Designed for closedloop unity gain, the EL2072 has a 730MHz -3dB bandwidth and 5ns settling to 0.2% while consuming only 15mA of supply current. • 730MHz -3dB bandwidth (0.5VPP) • 5ns settling to 0.2% • VS = ±5V @ 15mA • Low distortion: HD2, HD3 of -65dBc at 20MHz • Overload/short-circuit protected • Closed-loop, unity gain The EL2072 is an obvious high-performance solution for video distribution and line-driving applications. With low 15mA supply current and a 70mA output drive, performance in these areas is assured. • Low cost The EL2072's settling to 0.2% in 5ns, low distortion, and ability to drive capacitive loads make it an ideal flash A/D driver. The wide 730MHz bandwidth and extremely linear phase allow unmatched signal fidelity. • Video buffer The EL2072 can be used inside an amplifier loop or PLL as its wide bandwidth and fast rise time have minimal effect on loop dynamics. • High-speed A/D buffer Elantec products and facilities comply with MIL-I-45028A, and other applicable quality specifications. For information on Elantec's processing, see Elantec document QRA-1: Elantec's Processing, Monolithic Integrated Circuits. • Direct replacement for CLC110 Applications • Video distribution • HDTV buffer • Photodiode, CCD preamps • IF processors • High-speed communications Ordering Information PART NUMBER Pinout EL2072 (8-PIN PDIP SO) TOP VIEW TEMP. RANGE PACKAGE PKG. NO. EL2072CN -40°C to +85°C 8-Pin PDIP MDP0031 EL2072CS -40°C to +85°C 8-Pin SO MDP0027 Manufactured under U.S. Patent No. 4,893,091 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL2072 Absolute Maximum Ratings (TA = 25°C) Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7V Output Current Output is short-circuit protected to ground, however, maximum reliability is obtained if IOUT does not exceed 70mA. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . .θJA = 95°C/W PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA = 175°C/W SO Note: See EL2071/EL2171 for Thermal Impedance curves. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VOS TCVOS IB VS = ±5V, RL = 100Ω, RS = 50Ω unless otherwise specified DESCRIPTION TEST CONDITIONS Output Offset Voltage TEMP MIN TYP MAX UNITS 2.0 8.0 mV TMIN 16.0 mV TMAX 13.0 mV µV/°C 25°C Average Offset Voltage Drift Input Bias Current 25°C - TMAX 20.0 50.0 25°C - TMIN 20.0 100.0 25°C, TMAX 10.0 50.0 µA 100.0 µA nA/°C TMIN TCIB AV ILIN Average Input Bias Current Drift Small Signal Gain Integral End Point linearity PSRR Power Supply Rejection Ratio IS Supply Current—Quiescent RIN Input Resistance CIN RL = 100Ω ±2V F.S. 25°C - TMAX 200.0 300.0 25°C - TMIN 200.0 700.0 25°C 0.96 TMIN, TMAX 0.95 25°C Input Capacitance V/V 0.2 %F.S. TMIN 0.8 %F.S. TMAX 0.3 %F.S. 45.0 All 65.0 15.0 160.0 50.0 kΩ TMAX 200.0 kΩ 1.6 25°C VOUT Output Current Output Voltage Swing 2 RL = 100Ω mA TMIN 2.0 TMIN, TMAX IOUT 20.0 100.0 25°C Output Impedance (DC) dB 25°C TMIN, TMAX ROUT V/V 0.4 All No Load 0.98 25°C, TMAX 50.0 TMIN 45.0 25°C, TMAX ±3.2 TMIN ±3.0 70.0 kΩ 2.2 pF 2.5 pF 3.0 Ω 3.5 Ω mA mA ±4.0 V V EL2072 AC Electrical Specifications PARAMETER VS = ±5V, RL = 100Ω, RS = 50Ω unless otherwise specified DESCRIPTION TEST CONDITIONS TEMP MIN TYP MAX UNITS 25°C 400.0 730.0 TMIN 400.0 MHz TMAX 300.0 MHz 25°C 55.0 TMIN, TMAX 50.0 FREQUENCY RESPONSE SSBW LSBW -3dB Bandwidth (VOUT < 0.5VPP) -3dB Bandwidth (VOUT = 5.0VPP) MHz 90.0 MHz MHz GAIN FLATNESS GFPL GFR GDL Peaking VOUT < 0.5VPP Rolloff VOUT < 0.5VPP Group Delay < 200MHz < 200MHz < 200MHz 25°C 0.0 0.5 dB TMAX 0.6 dB TMIN 0.8 dB 0.8 dB TMIN 1.0 dB TMAX 1.2 dB 1.0 ns 1.2 ns 1.5 ° 2.0 ° 1.0 ns 1.4 ns 7.5 ns 8.5 ns 25°C 0.0 25°C, TMIN 0.75 TMAX LPD Linear Phase Deviation VOUT < 0.5VPP < 200MHz 25°C, TMIN 0.7 TMAX TIME-DOMAIN RESPONSE TR1, TF1 Rise Time, Fall Time Input Signal Rise/Fall = 300ps 0.5V Step Rise Time, Fall Time Input Signal Rise/Fall ð 1ns 5.0V Step TS1 Settling Time to 0.2% Input Signal Rise/Fall ð 1ns 2.0V Step All 5.0 10.0 ns OS Overshoot Input Signal Rise/Fall = 300ps 0.5V Step 25°C 0.0 10.0 % 15.0 % TR2, TF2 SR 25°C, TMIN 0.4 TMAX 25°C 4.5 TMIN, TMAX TMIN, TMAX Slew Rate 25°C 500.0 TMIN, TMAX 450.0 800.0 V/µs V/µs DISTORTION HD2 HD2A HD3 HD3A 2nd Harmonic Distortion at 20MHz 2VPP 2nd Harmonic Distortion at 50MHz 2VPP 3rd Harmonic Distortion at 20MHz 2VPP 3rd Harmonic Distortion at 50MHz 2VPP 3 25°C -50.0 dBc TMIN -48.0 dBc TMAX -55.0 dBc -45.0 dBc -40.0 dBc -55.0 dBc -55.0 dBc -50.0 dBc -45.0 dBc 25°C, TMAX -55.0 -50.0 TMIN 25°C -65.0 TMIN, TMAX 25°C, TMIN TMAX -60.0 EL2072 AC Electrical Specifications PARAMETER VS = ±5V, RL = 100Ω, RS = 50Ω unless otherwise specified (Continued) DESCRIPTION TEST CONDITIONS TEMP MIN TYP MAX UNITS -158.0 -155.0 dBm (1Hz) -154.0 dBm (1Hz) 57.0 µV 63.0 µV EQUIVALENT INPUT NOISE NF INV Noise Floor > 100kHz 25°C, TMIN Integrated Noise 100kHz to 200MHz 25°C, TMIN TMAX 4 TMAX 40.0 EL2072 Typical Performance Curves Forward Gain and Phase Gain Flatness & Deviation from Linear Phase Reverse Gain and phase Input Impedance Output Impedance Recommended RS vs Load Capacitance Integral Linearity Error Frequency Response vs RLOAD |S21| vs CLOAD with Recommended Rs Small Signal Pulse Response 2nd Harmonic Distortion 5 Large Signal Pulse Response 3rd Harmonic Distortion Long-Term Settling Time 2-Tone, 3rd Order Intermodulation Intercept EL2072 Burn-In Circuit Printed Circuit Layout As with any high-frequency device, good PCB layout is necessary for optimum performance. This is especially important for the EL2072, which has a typical bandwidth of 730MHz. Ground plane construction is a requirement, as is good power-supply bypassing close to the package. A closely-placed 0.01µF ceramic capacitor between each supply pin and the ground plane is usually sufficient decoupling. Pins 2, 3, 6, and 7 should be connected to the ground-plane to minimize capacitive feedthrough, and all input and output traces should be laid out as transmission lines and terminated as close to the EL2072 package as possible. Increasing capacitance on the output of the EL2072 will add phase shift, decreasing phase margin and increasing frequency-response peaking. A small series resistor before the capacitance decouples this effect, and should be used for large capacitance values. Please refer to the graphs for the appropriate resistor value to be used. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6