HA-5137 SPICE Operational Amplifier Macro-Model TM Application Note March 1997 MM5137 Introduction tle 5 ) - This application note describes the SPICE macro-model for the HA-5137, a wide bandwidth precision op amp. The model was designed to be compatible with the well known SPICE program developed by the University of California in hope that most simulation software venders follow this basic format and syntax. A schematic of the macro-model, the Spice net listing and various simulated performance curves are included. The macro-model schematic includes node numbers to help relate the SPICE listing to the schematic. The model is designed to emulate a typical rather than a worst case part. Most AC and DC parameters are simulated. Significant poles and zeros are included to give the most accurate AC and transient simulation with minimum complexity. 7 E RON Model Description DE tho The most significant singularities of the HA-5137 are modeled by RC networks. One pole-zero pair and four additional poles are used. Output Stage EX1, D1 and D2 model output current limiting. IH and IL are the power supply currents. DPH, DPL and GPS vary the supply currents based on the opamp’s output current. DL, DH, ECC and EEE provide voltage clamping on the output to simulate the typical output voltage swing. Some effects of output parasitics due to package capacitance and inductance are lumped with the poles. Parameters Not Modeled Input Stage PL R CR Poles and Zeros DP and DN represent the differential input resistance. Input bias currents are created by I1 and offset current is modeled with FA. Source VN represents the input offset voltage. C1 limits slew rate. No input parasitics due to package capacitance and lead inductance are included. Gain Stage To maintain a simple macro-model not all op amp parameters are modeled. Most of the parameters not modeled are listed below: • Temperature Effects • Differential Voltage Restrictions • Input Voltage and Current Noise • Common Mode Restrictions G2, R2, CC, GOL, and RD simulate open loop gain. CC is the macro-model dominant pole capacitor. • Tolerances for Monte Carlo Analysis • Power Supply Range ds rpon, ior) () CI 1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved Application Note MM5137 Spice Listing * *COPYRIGHT (C) 1992 INTERSIL CORPORATION *ALL RIGHTS RESERVED * *HA-5137 MACRO-MODEL *REV: 2-04-92 *BY: D.W. RIEMER * *PINOUT +IN -IN VCC VEE OUT * .SUBCKT HA5137 1 2 4 5 3 .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL DP DN DV D1 D2 DX D D D D D D IS=1E-14 IS=+8.5E-15 IS=+1.1746E-14 IS=1E-9 IS=1E-9 IS=1E-20 N=+6.6967E-01 N=+6.6967E-01 N=.2 N=1 N=+1.0 N=+30.0 *INPUT STAGE *VALUE OF SOURCE VN MODELS VIO AND *MAY BE ADJUSTED AS DESIRED. * VP VN I1 FA DP DN C1 FP FN GC GPP GPN IRX RT 1 2 8 2 6 7 8 9 0 0 9 9 0 9 6 7 0 0 8 8 0 0 9 9 0 0 9 0 0 +1.0E-05 +1.295E-08 VN +1.857E+00 DP DN +1.0792E-16 IC=-2.3157E-01 VP +3.0579E+04 VN +3.5975E+04 8 0 +1.2372E-08 4 0 +2.2123E-08 5 0 +2.2123E-08 +2.865E-09 1.0 * * POLES AND ZEROS EP1 10 0 9 0 1.0 RP1 10 11 +2.21E+02 RZ1 11 12 +1.77E+02 CP1 12 0 1E-10 EP2 13 0 11 0 1.0 RP2 13 14 +1.592E+01 CP2 14 0 1E-10 EP3 15 0 14 0 1.0 RP3 15 16 +1.0613E+01 CP3 16 0 1E-10 EP4 17 0 16 0 1.0 RP4 17 18 +9.0971 CP4 18 0 1E-10 EP5 19 0 18 0 1.0 RP5 19 20 +7.96 CP5 20 0 1E-10 * 2 * OUTPUT STAGE G2 0 21 20 0 1.0 R2 21 0 +6. 5577E+02 CC 21 22 +2.2E-11 GOL 22 0 21 0 +3. 6187E+03 RD 22 0 +5. 0809E+01 DH 22 23 DV DL 24 22 DV ECC 23 0 POLY 1 4 0 -2.7 1.0 EEE 24 0 POLY 1 5 0 +2.7 1.0 IH 4 0 +3.5E-03 IL 0 5 +3.5E-03 GPS 25 0 22 3 +8.5427E-02 DPH 4 25 DX DPL 25 5 DX D1 22 26 D1 D2 26 22 D2 EX1 26 0 POLY 2 22 0 3 0 0.0 -7.2888E-01 +1.7249 RO 22 3 +1.17059E+01 .ENDS HA5137 Application Note MM5137 Macro-Model Schematic +INPUT -INPUT VCC VEE 1 2 4 5 + - VP DP DN 8 VN - 7 9 + 6 C1 I1 9 + - 0 GPN + + + - - FP FA RT 0 10 RP1 GPP - RZ1 12 CP1 + - IRX GC 13 RP2 EP1 11 FN 15 RP3 16 14 EP2 CP2 + - 17 RP4 18 EP3 CP3 + - 19 RP5 20 EP4 + - CP4 EP5 CP5 22 D2 D1 24 CC 21 GOL 26 DPL 25 GPS + + R2 20 IL EEE + - DL - 5 ECC + 23 DH RD - + IH DPH 4 22 + - RO - EX1 3 G2 GND OUTPUT 3 Typical Performance Curves GAIN/PHASE RESPONSE vs FREQUENCY 200 GAIN 100 dB/Deg 0 PHASE -100 -200 101 102 103 10 4 10 5 HZ 3 106 107 10 8 Application Note MM5137 Typical Performance Curves (Continued) SMALL SIGNAL RESPONSE 100 mV 50 0 0 100 200 300 400 500 600 TIME (ns) LARGE SIGNAL RESPONSE 11 8 VOLTS 5 2 0 0.0 1.0 2.0 3.0 4.0 5.0 TIME (µs) All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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