ICs for TV AN5829S Sound multiplex decoder IC for the U.S. televisions ■ Overview 3 4 5 6 12 13 0.3 7.2±0.3 9.4±0.3 0.15 0.925 10 11 19 18 17 16 15 14 15.3±0.3 7 8 9 24 23 22 21 20 2.0±0.2 0.4±0.25 0.45 • Stereo demodulation, SAP demodulation, dbx noise reduction, AGC, external stereo input SW and I2C bus interface are integrated in a single chip • Bi-directional I2C bus makes it possible to monitor MPX input level, separation adjustment (3 places), mode changeover and receiving status. • Eliminated external parts (multi-sound block: 21 pieces → 14 pieces • Lower power dissipation (VCC = 5 V, ITOT = 18 mA) 1 2 1.27 ■ Features Unit: mm 0.1±0.1 The AN5829S is a multiplex sound demodulation IC dedicated to the U.S. television and incorporates a bidirectional I2C interface (adjustment, mode SW), an AGC circuit and external stereo input switches (2 systems). SOP024-P-0375A ■ Applications • Televisions and VCRs for the North American market 1 MPX in 14 GND VCC 2 7 Input VCA 17 SAP det. SAP out filter L−R demod SAP demod (L−R)/SAP switch Spectral RMS det. Spectral expand dbx De-emph. Wide band RMS det. Wide band expand Offset cancel 22 Noise det. L−R filter St. PLL Matrix AGC 1 Noise filter SAP filter Pilot cancel Pilot det. Offset cancel 4 Stereo filter 16 75 µs De-emph. 21 L+R filter L out L+R demod R out Out SW fH, 2fH Trap filter Spectral filter Wide band filter DAC I2C Decoder ZAP 9 10 11 6 8 5 3 2 23 24 19 18 20 AUX1 R AUX1 L AUX2 R AUX2 L SDA SCL PE AN5829S ICs for TV ■ Block Diagram 15 12 13 ICs for TV AN5829S ■ Pin Descriptions Pin No. Description Pin No. Description 1 AGC timing 13 SAP carrier detection 2 External input 1 L-ch 14 Composite input 3 External input 1 R-ch 15 Pilot signal detection 4 75 µs filter offset cancel 16 Stereo PLL filter 5 dbx offset cancel 17 GND 6 Wideband timing 18 SCL 7 VCC 19 SDA 8 Wideband level sensor input 20 PE for ZAP 9 Spectral filter 21 L-ch output 10 Spectral timing 22 R-ch output 11 Spectral level sensor input 23 External input 2 R-ch. 12 SAP noise level detection 24 External input 2 L-ch. ■ Absolute Maximum Ratings Parameter Symbol Rating Unit VCC 6.0 V ICC 25 mA PD 150 mW Topr −20 to +75 °C Tstg −55 to +125 °C Supply voltage Supply current Power dissipation *2 Operating ambient temperature Storage temperature *1 *1 Note) The use of this IC, which builds in dbx-TV noise reduction, requires a license agreement with THAT Corporation. *1: Except fot the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: Ta = 75°C ■ Recommended Operating Range Parameter Supply voltage Symbol Range Unit VCC 4.5 to 5.5 V 3 AN5829S ICs for TV ■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C Input level (at 100% modulation) L+R: 75 mV[rms] (pre-emphasis off) L−R: 150 mV[rms] (dbx noise reduction off) Pilot: 15 mV[rms] SAP: 45 mV[rms] (dbx noise reduction off) Parameter 4 Symbol Conditions Min Typ Max Unit No signal 11 18 25 mA 530 mV[rms] Total circuit current ICC Mono output level V0(MON) f = 1 kHz, (mono) 100%mod 430 480 Mono frequency characteristics-1 V1(MON) f = 300 Hz, (mono) 30%mod − 0.5 0 0.5 dB Mono frequency characteristics-2 V2(MON) f = 8 kHz, (mono) 30%mod −1.2 − 0.1 0.7 dB Mono distortion ratio THD(MON) f = 1 kHz, (mono) 100%mod 0.7 % Mono noise level VN(MON) Input short-circuit, BPF (A curve) −60 dBV 0.5 dB (L), (R) output voltage difference VLR(MON) f = 1 kHz, (mono) 100%mod − 0.5 0 Stereo output level V0(ST) f = 1 kHz, (L(R)-only) 100%mod 380 480 Stereo frequency characteristics-1 V1(ST) f = 300 Hz, (L(R)-only) 30%mod − 0.7 0 0.7 dB Stereo frequency characteristics-2 V2(ST) f = 3 kHz, (L(R)-only) 30%mod −1 0 1 dB Stereo frequency characteristics-3 V3(ST) f = 8 kHz, (L(R)-only) 30%mod −2.5 − 0.5 1.5 dB Stereo distortion ratio THD(ST) f = 1 kHz, (L(R)-only) 100%mod 1 % Stereo noise level VN(ST) f = 15.73 kHz, (fH), 15 mV[rms] fH, 2 fH Trap+BPF −60 dBV Stereo discrimination level VTH(ST) f = 15.73 kHz (fH) 4 8 13 mV[rms] Stereo discrimination hysteresis VHY(ST) f = 15.73 kHz (fH) 0.5 5 dB SAP output level V0(SAP) f = 1 kHz, (SAP) 100%mod 370 500 SAP frequency characteristics-1 V1(SAP) f = 300 Hz, (SAP) 30%mod −1 0 1 dB SAP frequency characteristics-2 V2(SAP) f = 3 kHz, (SAP) 30%mod −2.5 − 0.5 1 dB SAP distortion ratio f = 1 kHz, (SAP) 100% 1.5 % THD(SAP) 580 mV[rms] 680 mV[rms] SAP noise level VN(SAP) f = 78.7 kHz, (5fH),V= 45 mV[rms], BPF −70 dBV SAP discrimination level VTH(SAP) f = 78.7 kHz, (5fH) 11 26 mV[rms] SAP discrimination hysteresis VHY(SAP) f = 78.7 kHz, (5fH) 0.5 5 dB SAP → Stereo crosstalk CT1 (SAP)1 kHz, 100%mod (Stereo) pilot-signal −50 dB Stereo → SAP crosstalk CT2 (Stereo) 1 kHz, 100%mod (SAP) carrier-signal −50 dB SAP → Mono crosstalk CT3 (SAP) 1 kHz, 100%mod −50 dB Mono → SAP crosstalk CT4 (Mono) 1 kHz, 100%mod (SAP) carrier-signal −56 dB AUX 1, AUX 2 to INT crosstalk CT5 f = 1 kHz, VIN = 500 mV[rms] 50 dB INT, AUX 2 to AUX 1 crosstalk CT6 INT: (mono) 1 kHz, 100%mod EXT: f = 1 kHz, 500 mV[rms] 50 dB INT, AUX 1 to AUX 2 crosstalk CT7 INT: (mono) 1 kHz, 100%mod EXT: f = 1 kHz, 500 mV[rms] 50 dB ICs for TV AN5829S ■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued) Parameter AGC gain AGC gain 2 I2 Symbol 1*1 *1 Conditions Min Typ Max Unit VAGC1 f = 1 kHz, VIN(EXT) = 50 mV[rms] 67 100 140 mV[rms] VAGC2 f = 1 kHz, VIN(EXT) = 500 mV[rms] 180 270 390 mV[rms] 1 2 20 mA C interface Sink current at ACK IACK Maximum pin 2 sink current at ACK SCL, SDA signal input high level VIHI 3.5 5.0 V SCL, SDA signal input low level VILO 0 0.9 V Input available maximum frequency fImax 100 kbit/s Note) *1: 00H register: D7 = 0, D6 = 1 • Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit Stereo separation (100%)-1 Sep100-1 f = 300 Hz, (L(R)-only) 100%mod 20 35 dB Stereo separation (100%)-2 Sep100-2 f = 1 kHz, (L(R)-only) 100 %mod 17 28 dB Stereo separation (100%)-3 Sep100-3 f = 3 kHz, (L(R)-only) 100%mod 20 35 dB Stereo separation (100%)-4 Sep100-4 f = 8 kHz, (L(R)-only) 100%mod 10 18 dB Stereo separation (30%)-1 Sep30-1 f = 300 Hz, (L(R)-only) 30%mod 22 35 dB Stereo separation (30%)-2 Sep30-2 f = 1 kHz, (L(R)-only) 30%mod 20 35 dB Stereo separation (30%)-3 Sep30-3 f = 3 kHz, (L(R)-only) 30%mod 22 35 dB Stereo separation (30%)-4 Sep30-4 f = 8 kHz, (L(R)-only) 30%mod 14 22 dB Stereo separation (10%)-1 Sep10-1 f = 300 Hz, (L(R)-only) 10%mod 20 35 dB Stereo separation (10%)-2 Sep10-2 f = 1 kHz, (L(R)-only) 10%mod 20 35 dB Stereo separation (10%)-3 Sep10-3 f = 3 kHz, (L(R)-only) 10%mod 20 30 dB Stereo separation (10%)-4 Sep10-4 f = 8 kHz, (L(R)-only) 10%mod 14 22 dB I2 C interface tBUF 4.0 µs Start condition set-up time tSU.STA 4.0 µs Start condition hold time tHD.STA 4.0 µs Low period SCL, SDA tLO 4.0 µs High period SCL tHI 4.0 µs Rise time SCL, SDA tr 1.0 µs Fall time SCL, SDA tf 0.35 µs Data set-up time (write) tSU.DAT 0.25 µs Data hold time (write) tHD.DAT 0.3 µs Acknowledge set-up time tSU.ACK 3.5 µs Acknowledge hold time tHD.ACK 0 µs Stop condition set-up time tSU.STO 4.0 µs Bus free before start 5 AN5829S ICs for TV ■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued) Start condition Slave address Sub address ACK ACK Data byte Stop condition ACK SDA tBUF tLO tSU.STO tHD.DAT tSU.DAT SCL tSU.STA tHDSTA tr tf tHI tLO ■ Terminal Equivalent Circuits Pin No. Equivalent circuit 1 Description VCC 425 Ω AGC: AGC level sensor pin DC voltage (V) 0.5 to 2.0 51 kΩ 1 500 Ω GND 2 VCC 2 AUXIL: External input1 L-ch input pin 2.2 AUXIR: External input 1 R-ch input pin 2.2 20.7 kΩ 13.8 kΩ 2.2 V GND 3 VCC 3 20.7 kΩ 13.8 kΩ 2.2 V GND 6 ICs for TV AN5829S ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 4 Description VCC DC voltage (V) OFCAN1: 75 µs filter output Offset cancel pin 2.2 OFCAN2: dbx output Offset cancel pin 2.2 WBTIME: Wide expander effective value detection recovery time set-up pin 2.2 VCC: VCC pin VCC WBDET: RMS detection circuit input pin of wide band expander 2.2 524 Ω 4 80 kΩ 80 kΩ 2.2 V GND 5 VCC 524 Ω 5 80 kΩ 80 kΩ 2.2 V GND 6 VCC 7.5 µΑ 6 29 Ω 29 Ω 15 µΑ GND 7 8 VCC 8 14.4 kΩ 2.2 V GND 7 AN5829S ICs for TV ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 9 VCC 230 Ω Description DC voltage (V) SPEFIL: Variable de-emphasis level adjusting pin 2.2 SPETIME: RMS detection recovery time pin of variable de-emphasis 0.2 SPEDET: RMS detection circuit input pin of variable de-emphasis 2.2 NOISEDET: Noise detecting pin of SAP malfunction-prevention-circuit(Mute SAP demodulation at detecting noise.) VCC − 2 VBE 18 kΩ 9 230 Ω 18 kΩ 2.2 V GND 10 VCC 7.5 µΑ 10 29 Ω 29 Ω 15 µΑ GND 11 VCC 11 3.2 kΩ 2.2 V GND 12 VCC 141 kΩ 12 GND 8 ICs for TV AN5829S ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 13 VCC Description DC voltage (V) SAPDET: SAP signal carrier level detection pin VCC − 2 VBE 163 kΩ 13 GND 14 VCC 14 MPXIN: Composite signal input pin 2.2 524 Ω 54.4 kΩ 2.2 V GND 15 VCC PILOTDET: Stereo pilot signal detection pin 2.2VCC − 2 VBE 136 kΩ 15 GND 16 VCC PLL: Stereo PLL low pass filter connection pin VCC − 2 VBE 58 kΩ 16 GND 17 GND: GND pin 0 9 AN5829S ICs for TV ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 18 VCC DC voltage (V) SCL: I2C bus clock input pin SDA: I2C bus data input pin 2.2 PE: Current application input pin for ZAP at final test L-OUT: L-ch. line out output pin 2.2 51 kΩ 18 1.7 kΩ GND 19 VCC 51 kΩ 19 1.7 kΩ GND 20 20 GND 21 VCC 520 Ω 21 430 Ω 850 Ω 2.2 V GND 10 ICs for TV AN5829S ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 22 VCC DC voltage (V) R OUT: R-ch. line out output pin 2.2 AUX2R: External input 2 L-ch. input pin 2.2 AUX2L: External input 2 R-ch. input pin 2.2 520 Ω 22 430 Ω 850 Ω 2.2 V GND 23 VCC 23 20.7 kΩ 13.8 kΩ 2.2 V GND 24 VCC 24 20.7 kΩ 13.8 kΩ 2.2 V GND 11 AN5829S ICs for TV ■ Usage Notes 1. AGC set-up method By turning on AGC, the AGC performs 0 dB at a small signal input, Boost at a medium signal and gain reduction at a big signal. It can also control the I/O characteristics of AGC by I2C as shown below: AGC characteristics 1V "11" AGC = Off Output level (rms) "00" 100 mV AGC = On "10" "01" 10 mV 1 mV 1 mV Data of sub address 00H D7 D6 10 mV 100 mV 1V 10 V Input level (rms) 2. Guarantee of I2C operating temperature I2C bus control operation at an operating ambient temperature is theoretially guranteed based on IC design by means of the inspection using about 50% faster clock speed at the normal temperature (Ta = 25°C). Namely it is a theoretical value based on IC design, therefore it is not guranteed at the shipping inspection because the inspection under a high and low temperature is not conducted. 3. Electrostatic breakdown Pay attention to the following levels: Pin 6: 200 pF, 130 V Pin 10: 200 pF, 150 V Pin 22: 200 pF, 190 V 12 ICs for TV AN5829S ■ Technical Information [1] I2C bus 1. Receiving mode SDA SCL Start condition Slave address Acknowledge bit 1 0 1 1 0 1 1 0 B 6 Sub address Acknowledge bit 0 0 0 0 0 0 1 0 0 2 Data Acknowledge Stop bit condition 1 0 0 0 0 0 0 0 8 0 Transmission message As transfer messages, SCL and SDA are transfered synchronouslly and serially. SCL is a constant clock frequency and SDA is address data for controlling a receiving side and is sent in parallel by synchronizing with SCL. Data are in principle sent by 8-bit 3-octet (byte) and there exists an acknowledge bit per octet. The frame structure is mentioned below: 1) Start condition When SDA becomes from high to low at SCL = high, the receiver gets ready to receive. 2) Stop condition When SDA becomes from low to high at SCL = high, the receiver stops receiving. 3) Slave address Specified for each device. If any addresses of other devices are sent, receiving will be stopped. 4) Sub-address Specified for each function. 5) Data Data for controlling 6) Acknowledge bit This is the bit that informs the master of data reception every octet. The master sends the high signal and the receiver sends back the low signal as shown with the dotted line in the above figure, thus the master acknowledges reception on the receiver side. If the low signal is not sent back, the reception will be stopped. Except for the start and stop conditions, SDA does not change at SCL = high. 13 AN5829S ICs for TV ■ Technical Information [1] I2C bus (continued) 1. Receiving mode (continued) <I2C of this IC> 1) Enhances adjustment-free mechanism of the TV set thanks to DAC control 3 and 9 switches 2) Auto-increment function • Sub address 0 *: Auto-increment mode (Data sequential transfer leads to the sequential change of sub address, so that the data is inputted.) • Sub address 8 *: Data renewal mode (With sequential data transfer, data are inputted in the same sub address.) 2 3) I C bus protocol • Slave address • Format (normal) S Slave address W A Sub address A Data byte A P Acknowledge bit Write Mode: 0 Start condition Stop condition • Auto-increment mode/data renewal mode S Slave address W A Sub address A Data 1 A Data 2 A Data n A P 4) As the initial state of DAC is not guaranteed, never fail to input the following data in a power on mode. "06" register: "04" "00" register: adjustment data "01" register: adjustment data "02" register: "00" "05" register: adjustment data 2. Transmission mode (read mode) I2C bus protocol • Slave address: 10110111 (B7H) • Format S Slave address R A Read Mode: 1 14 Data byte A P ICs for TV AN5829S ■ Technical Information (continued) [1] I2C bus (continued) • Sub address byte and data byte format Write mode (slave add.: 10110110) Sub address Upper MSB D7 "02" D6 D5 D4 AGC adj. "00" "01" Data byte AUXselect 0: AUX1 1: AUX2 Adj.: 1 → On L:VGA out R:VCO fH Lower LSB D3 D2 D1 D0 Input level adjustment AUX SW 0: Off 1: On Mute: 1 → On AGC L: Mute R: Mute 1 → On High frequency separation adjustment 0 FMONO: 1 → On L: L+R R: L+R 0 St/SAP (L+R)/SAP 0 → SAP 0 → SAP "05" ∗ ∗ ∗ ∗ Low frequency separation adjustment "06" ∗ ∗ ∗ ∗ ∗ ∗ 0 0 ∗ = Don't care Read mode (slave add.: 10110111) Data byte Upper MSB D7 D6 Pilot det. SAP det. 1 → DET 1 → DET Lower LSB D5 D4 D3 D2 D1 D0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ = Don't care 15 AN5829S ICs for TV ■ Technical Information (continued) [2] Noise detecting operation in SAP receiving mode L−R filter Stereo filter MPX 14 in Input VCA SW1 a dbx Decoder b SAP out filter 5fH BPF SAP filter SAP det. 13 DC voltage comparater 150 kHz BPF Noise filter I2C Decoder SAP det. Noise det. 12 Noise det. SW2 a b c 75 µs De-emph. 21 L out Matrix a b c dbx Decoder Pin 14 input "02" register Pin 12, pin 13 SW1 SW2 22 R out I2C SAP det. Pin 21, pin 22 DC voltage 16 Noise: Small "00" V12 > V13 b c 3.5 V to 5 V SAP Noise: Large "00" V12 < V13 a a 0 V to 0.9 V L+R 14 17 7 Input VCA 0.047 µF 16 SAP det. SAP out filter L−R demod SAP demod (L−R)/SAP switch Spectral RMS det. Spectral expand dbx De-emph. Wide band RMS det. Wide band expand Offset cancel Matrix 4.7 µF 22 Noise det. L−R filter St. PLL AGC 1 Noise filter SAP filter Pilot cancel Pilot det. Offset cancel 2.2 µF 4 Stereo filter 0.1 µF fH, 2fH Trap filter Spectral filter Wide band filter DAC I2C Decoder 4.7 µF MPX in VCC 5V 4.7 µF 21 75 µs De-emph. L out Out SW R out L+R filter 180 kΩ L+R demod ZAP SDA SCL PE 9 11 10 6 8 0.022 µF 0.1 µF 3.3 µF(Ta) 10 µF(Ta) 0.33 µF 24 4.7 µF AUX2 L 23 4.7 µF AUX2 R 2 4.7 µF AUX1 L 3 4.7 µF AUX1 R 4.7 µF 5 19 18 20 ICs for TV AN5829S ■ Application Circuit Example 12 13 0.1 µF 0.1 µF 15 4.7 µF 17