ICs for TV
AN5095K
Single chip IC with I2C bus interface for PAL/NTSC color TV system
■ Overview
• Built- in video IF circuit, sound IF circuit, video
signal processing circuit, color signal processing
circuit, sync. signal processing circuit
• Suitable for PAL/NTSC/AV-NTSC/M-NTSC systems
• 6 dB improved sound S/N (compared with the
AN5195K-B/-C)
• Package: 64-SDIP, supply voltage: 5 V, 9 V
58.4±0.3
33
1
32
17.0±0.2
64
3.85±0.2
■ Features
Unit: mm
(1.641)
Seating plane
1.778
(1.0)
0.5+0.1
–0.05
(3.3)
0.7 min.
5.2 max.
The AN5095K is an IC in which PAL/NTSC
color television signal processing circuits are integrated into a single chip. Also, since the I2C bus
interface is built in the IC, the rationalization of set
production line can be realized.
19.05
0.25+0.1
–0.05
0° to 15°
SDIP064-P-0750B
■ Applications
• Television and televideo
1
G-Y
+/−
PN/S
SW
R-Y
demod.
*1-bit
Saturation *6-bit
Matrix
R, G, B SW
B-clamp
G-clamp
R-clamp
B-Y
demod.
Ver.
out
Shut
down
*6-bit
APC
Tint
H-OSC
H-VCO
AFC1
Hor.
reg.
System
SW
*1-bit
SCP
HVBLK
BGP
*3-bit
AFC2
1H
FF
(*6-bit)
ACC
amp.
Her.
count
down
50 Hz/60 Hz
detect
Ver.
count down
*2-bit
(50 Hz/
60 Hz)
Killer
ident
CW
generate
1-bit
ACC
det.
H-BLK
Hor.
lock det.
LPF
Hor.
sync. sep.
Ver.
sync. sep.
Black
expansion
CV
clamp
Y
clamp
SW
out
*6-bit
Y
contrast
Sharpness
DAC
out
I2C bus
interface
VCO
*7-bit
phase
shift
VIF
detect
APC1
IF
AGC
*9-bit
AFT
IF
amp.
*3-bit
Level
adjust
*6-bit
RF
AGC
Video SW
*1-bit
LPF
LImiter
SIF SW
*2-bit
SIF
detect
VCO
Deemphasis
*1-bit
Pre-amp.
*1-bit
SIF3 in/sharpness
ASW
33
SIF regulator filter
34
SIF2 in
35
SIF1 in
36
IF AGC
37
Int. Video1
38
SIF APC
39
Int. Video2
40
Det. out
41
APC1
42
V-OSC
43
Video out
44
Y-in
45
Sync. in
46
Ver. clamp
Chroma
VCO
R
G
B
• Drive 7-bit
• Drive 7-bit
• Cutoff 8-bit • Cutoff 8-bit • Cutoff 8-bit
32
De-coupling
31
Ext. video in
30
AFT
29
De-emphasis
28
Audio out
27
RF AGC
26
GND (VIF/SIF)
25
VIF2 in
24
VIF1 in
23
VCC3 (VIF/SIF)
22
SCL
21
SDA
20
ACL
18
Hor. lock det.
17
B-out
16
G-out
19
GND (R, G, B/DAC)
VCC3 (V, C, J)
47
C-in
48
GND (V, C, J)
49
FBP in
15
R-out
14
VCC1 (9 V)
Contrast
B-in
50
VCC2
51
AFC2
52
AFC1
G-in
13
53
12
54
11
R-in
X-ray protect
55
10
Ys-in
2-bit
BL det.
VOUT
58
H-out
56
9
57
8
3.58 MHz
6
APC
4
Killer
5
Killer out
50 Hz/60 Hz out
SECAM det. out
3
B-clamp filter
2
G-clamp filter
7
4.43 MHz
SECAM interface
59
-(B-Y) out
60
-(R-Y) out
61
SCP
62
-(B-Y) in
63
-(R-Y) in
64
1
R-clamp filter
Brightness
Killer,
*7-bit
50 Hz/60 Hz
SECAM det. SW
2
ICs for TV
AN5095K
■ Block Diagram
ICs for TV
AN5095K
■ Pin Descriptions
Pin No.
Description
Pin No.
Description
1
(R) clamp
33
SIF3 input/sharpness
2
(G) clamp
34
SIF regurator filter
3
(B) clamp
35
SIF2 input
4
Killer filter
36
SIF1 input
5
Killer out, 50 Hz/60 Hz out, SECAM det. out
37
IF AGC filter
6
Chroma APC filter
38
Internal videol input
7
Chroma VCO (4.43 MHz)
39
SIF APC filter
8
Chroma VCO (3.58 MHz)
40
Internal video2 input
9
Black level det./Blank off SW
41
VIF detect output
10
YS input (fast blanking)
42
VIF APC 1 filter
11
External R-input
43
VIF VCO (fP/2)
12
External G-input
44
Video output
13
External B-input
45
Y-input
14
VCC1
46
H, V sync. input
15
R-output
47
VCC3-2 (chroma/jungle/DAC)
16
G-output
48
Chroma input/black expansion start
17
B-output
49
GND (video/chroma/jungle)
18
Hor.lock detect
50
FBP input
51
VCC2 (hor. stability supply)
B/I2C/DAC)
19
GND (R, G,
20
ACL
52
AFC2 filter
21
SDA
53
AFC1 filter
22
SCL
54
Hor. VCO (32 fH)
23
VCC3-1 (VIF/SIF)
55
X-ray protection input
24
VIF1 input
56
Hor. pulse output
25
VIF2 input
57
Ver. sync. clamp
26
GND (VIF/SIF)
58
Ver. pulse output
27
RF AGC output
59
SECAM interface
28
Audio output
60
-(B-Y) output
29
De-emphasis
61
-(R-Y) output
30
AFT output
62
Sandcastle pulse output
31
External video input
63
-(B-Y) input
32
DC De-coupling filter
64
-(R-Y) input
3
AN5095K
ICs for TV
■ Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
VCC
Supply current
Unit
VCC1 (14)
10.5
V
VCC3 (23, 47)
6.0
I14
67
I23+47
126
I51
27
ICC
Power dissipation *2
Operating ambient temperature *1
Storage temperature
Rating
*1
mA
PD
1 480
mW
Topr
−20 to +70
°C
Tstg
−55 to +150
°C
Note) *1: Except for the operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.
*2: The power dissipation shown is for the IC package in free air at Ta = 70°C.
■ Recommended Operating Range
Parameter
Symbol
Range
Unit
VCC1
8.1 to 9.9
V
VCC3
4.5 to 5.5
V5
0 to 6
V10
0 to 6
V11
0 to 6
V12
0 to 6
V13
0 to 6
V21
0 to 6
V22
0 to 6
V27
0 to 10.5
V30
0 to 10.5
V48
0 to V14
V50
0 to V47
V55
0 to 2
V59
0 to V14
Supply current
I51
10 to 25
mA
Circuit current
I15
−3.2 to +0.6
mA
I16
−3.2 to +0.6
I17
−3.2 to +0.6
I41
− 0.8 to +0.8
I44
−1.1 to +0.4
I46
− 0.8 to +0.1
Supply voltage
Terminal voltage
4
V
ICs for TV
AN5095K
■ Recommended Operating Range (continued)
Parameter
Circuit current
Symbol
Range
Unit
I56
−6.4 to +0.1
mA
I58
− 0.8 to +0.1
I59
− 0.3 to +0.1
Note) Do not apply external currents or voltages to any pins not specifically mentioned.
For circuit currents, '+' denotes current flowing into the IC, and '−' denotes current flowing out of the IC.
■ Electrical Characteristics at Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power Supply
Supply current 1
I14
Current at V14 = 9 V
39
48
57
mA
Supply current 2
I23
Current at V23 = 5 V
7
10
13
mA
Supply current 3
I47
Current at V47 = 5 V
49
63
77
mA
Stabilized supply voltage
V51
Voltage at I51 = 15 mA
5.8
6.5
7.2
V
Stabilized supply current
I51
Current at V51 = 5 V
2
5
7
mA
Stabilized supply input resistance
R51
DC measurement, slant between at
I51 = 10 mA and 25 mA
1
5
10
Ω
1.7
2.1
2.5
V[p-p]
VIF circuit
Typical input; fP = 38.9 MHz, VIN = 90 dBµ, DAC data are typical
Video detection output (typ.)
VPO
Modulation m = 87.5%, data 0B = 44
Video detection output (max.)
VPOmax 0B = 74
1.9
2.6
3.3
V[p-p]
Video detection output (min.)
VPOmin 0B = 04
1.1
1.6
2.1
V[p-p]
Video detection outputfrequency characteristic
fPC
Frequency which becomes −3 dB for
1 MHz output
5.5
8
12
MHz
Synchronous peak value voltage
VSP
Synchronized peak value voltage at
V[p-0] measurement
1.6
2.0
2.4
V
APC high-level pull-in range
fPPH
High-pass side pull-in range
(difference from fP = 38.9 MHz)
1.0
2.0
MHz
APC low-level pull-in range
fPPL
Low-pass side pull-in range
(difference from fP = 38.9 MHz)
−2.0
−1.0
MHz
75
95
dBµ
RF AGC delay point adjustable
range *1
∆VRFDP Delay point in which data are 0A = 00
to 3F (input at V27 = approx. 6.5 V)
∆fP
Dispersion without VIN
V37 (IF AGC) = 0 V (measurement of
the difference from 38.9 MHz)
−1.2
0
1.2
MHz
RF AGC maximum sink current
IRFmax
Max. current IC can sink when pin 27
is low
1.5
3.0
mA
RF AGC minimum sink current
IRFmin
IC leak current at which pin 27 is high
− 50
0
50
µA
VCO free-running frequency
Note) *1 to *9: Refer to "Explanation of test methods".
5
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
VIF circuit (continued)
Symbol
Conditions
Typ
Max
Unit
Typical input; fP = 38.9 MHz, VIN = 90 dBµ, DAC data are typical
AFT discrimination sensitivity *2
µAFT
∆f = ±25 kHz
40
57
75
mV/kHz
AFT center voltage
VAFT
V30 at VIN without input
4.0
4.5
5.0
V
AFT maximum output voltage
VAFTmax V30 at f = fP −500 kHz
7.8
8.1
8.7
V
AFT minimum output voltage
VAFTmin V30 at f = fP +500 kHz
0.3
0.8
1.0
V
70
120
170
Ω
Detection output resistance
SIF circuit
RO41
DC measurement,
IO = − 0.4 V to −1.0 mA
Typical input; fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dBµ
Audio detection output
(PAL, SIF1)
VSOP36 ∆f = ±50 kHz
0B-D3 = 0
0.90
1.15
1.40
V[rms]
Audio detection output
(PAL, SIF2)
VSOP35 ∆f = ±50 kHz
0B-D3 = 0
0.90
1.15
1.40
V[rms]
Audio detection output
(PAL, SIF3)
VSOP33 ∆f = ±50 kHz
0B-D3 = 0
0.90
1.15
1.40
V[rms]
Audio detection output
NTSC/PAL
RSN/P
∆f = ±25 kHz
0B-D3 = 1, ratio to PAL (VSOP36)
−2.5
− 0.5
1.5
dB
Audio detection output
linearity
∆VSOP
fS = 5.5 MHz and 6.0 MHz
ratio to 6.5 MHz
−3
0
3
dB
SIF pull-in range
NTSC (4.5 MHz)
fSNH
(4.5M)
Pull-in range of high-pass side
4.8
5.0
MHz
SIF pull-in range
NTSC (4.5 MHz)
fSNL
(4.5M)
Pull-in range of low-pass side
4.0
4.2
MHz
SIF pull-in range
PAL (5.5 MHz)
fSPH
(5.5M)
Pull-in range of high-pass side
5.8
6.0
MHz
SIF pull-in range
PAL (5.5 MHz)
fSPL
(5.5M)
Pull-in range of low-pass side
5.0
5.2
MHz
SIF pull-in range
PAL (6.0 MHz)
fSPH
(6.0M)
Pull-in range of high-pass side
6.3
6.5
MHz
SIF pull-in range
PAL (6.0 MHz)
fSPL
(6.0M)
Pull-in range of low-pass side
5.5
5.7
MHz
SIF pull-in range
PAL (6.5 MHz)
fSPH
(6.5M)
Pull-in range of high-pass side
6.8
7.0
MHz
SIF pull-in range
PAL (6.5 MHz)
fSPL
(6.5M)
Pull-in range of low-pass side
6.0
6.2
MHz
De-emphasis terminal
output resistance (PAL)
R29P
Impedance of pin 29 at PAL
32
40
48
kΩ
De-emphasis terminal
output resistance (NTSC)
R29N
Impedance of pin 29 at NTSC
48
60
72
kΩ
Note) *1 to *9: Refer to "Explanation of test methods".
6
Min
ICs for TV
AN5095K
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
5.7
6.7
7.7
dB
8
10
MHz
AV SW circuit
Video SW voltage gain
GVSW
f = 1 MHz, VIN = 1 V[p-p]
Video SW-frequency
characteristic
fVSW
Frequency to become −3 dB from f =
1 MHz, VIN = 0.714 V[0-p]
Video SW external input terminal
voltage
V31
DC measurement
1.7
2.0
2.3
V
Video SW external output DC
voltage
V44E
DC measurement,
03-D7 = 1, 0B-D7 = 1
4.2
4.8
5.4
V
Video SW external input resistance
RI31
DC measurement
44
56
68
kΩ
Video SW output resistance
RO44
DC measurement,
IO = − 0.6 mA to −1.0 mA
110
150
190
Ω
Video SW internal clamp terminal V38, 40
voltage
DC measurement,
IIN = −1.0 mA
1.4
1.7
2.0
V
Video SW internal output DC
voltage
V44I
DC measurement
3.7
4.3
4.9
V
Audio SW voltage gain
GASW
Data 03-D7 = 1, 0B-D7 = 1,
(input from outside) f = 400 Hz,
VIN = 1 V[p-p]
−1
0
1
dB
Audio SW output DC voltage
V28
DC measurement
3.7
4.2
4.7
V
Audio SW output resistance
RO28
DC measurement
350
450
550
Ω
Video signal processing circuit
Video output (typ.)
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out
VYO
Data 03 = 20 (typ.) (contrast)
2.0
2.5
3.0
V[0-p]
Video output (max.)
VYOmax Data 03 = 3F (max.)
4.1
5.0
5.9
V[0-p]
Video output (min.)
VYOmin Data 03 = 00 (min.)
0.15
0.50
1.00
V[0-p]
15
20
25
dB
5.5
6.0
MHz
9
13
17
dB
2.0
2.5
3.0
V
2.75
3.35
V
Contrast variable range
Video frequency characteristic
Picture quality variable range
Pedestal level (typ.)
YCmax/min 03 = 3F
03 = 00
fYC
Pin 33 = 5 V (sharpness), frequency to
become −3 dB from f = 0.2 MHz
YSmax/min V33 = 7V
V33 = 5V
VPED
f = 3.8 MHz
Data 02 = 40 (typ.) (brightness)
Pedestal variable width
∆VPED
Difference between data 02 = 00 and 7F 2.15
Brightness control sensitivity
∆VBRT
Average amount of change per 1-step
between data 02 = 30 and 50
14
20
26
mV/Step
Video input clamp voltage
VYCLP
Pin 45 clamp voltage
3.2
3.7
4.2
V
ACL sensitivity
ACL
Amount of change of Y-out, when V20
= 3.0 V → 3.5 V
2.7
3.2
3.7
V/V
Blanking level
VYBL
Blanking pulse DC voltage
1.0
1.5
V
7
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Video signal processing circuit (continued)
Min
Typ
Max
Unit
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out
Service SW
threshold voltage
VSTH
Voltage at which vertical output stops
when pin 20 (ACL) voltage is decreased
0.3
V
DC restoration ratio
TDC
APL10% to 90%
∆AC − ∆DC
TDC =
× 100
∆AC
90
100
110
%
Video input clamp current
IYCLP
DC measurement; Sink current inside of IC
6
11
16
µA
Pedestal difference voltage
∆VIPL
Pedestal difference voltage of R, G, B-out − 0.2
0
0.2
V
Brightness voltage tracking
∆TBL
Ratio of R, G, B-out fluctuation level
for data 02 (bright) = 20 to 60
0.9
1.0
1.1
Time
Video voltage gain relative ratio
∆GYC
Output ratio of R, B-out against G-out
0.8
1.0
1.2
Time
∆TCONT Ratio of gain of R, G, B-out for data 03
(contrast) = 10 to 30
0.9
1.0
1.1
Time/
Time
2.9
3.7
4.5
V[p-p]
*
Video voltage gain tracking
Color signal processing circuit
Color-difference output (typ.)
Burst 150 mV[p-p] (PAL), reference is B-out
VCO
Input; Color bar
Data 00 = 20 (typ.), 03 = 20 (typ.)
Color-difference output (max.)
VCOmax Data 03 = 3F, amplitude of one side
03 = 20
2.6
3.3
V[0-p]
Color-difference output (min.)
VCOmin Data 00 = 00, 03 = 20
100
mV[p-p]
15
20
25
dB
Contrast adjustable range
CCmax/min 03 = 3F
03 = 00
00 = 20
ACC characteristic 1
ACC1
Burst 150 mV[p-p] → 300 mV[p-p]
0.9
1.0
1.2
Time
ACC characteristic 2
ACC2
Burst 150 mV[p-p] → 30 mV[p-p]
0.8
1.0
1.2
Time
NTSC tint center
∆θC
The difference from data 01 = 20 at
which tint is adjusted to center
−7
0
7
Step
NTSC tint adjustable range 1
∆θ1
Input; Rainbow data 01 = 3F
30
50
65
deg
NTSC tint adjustable range 2
∆θ2
Input; Rainbow data 01 = 00
− 65
− 50
− 30
deg
Color-difference output ratio (R)
R/B
Input; Rainbow for both PAL/NTSC
0.46
0.56
0.66
Time
Color-difference output ratio (G)
G/B
Input; Rainbow for both PAL/NTSC
0.28
0.34
0.40
Time
Color-difference output angle (R)
∠R
Input; Rainbow for both PAL/NTSC
78
90
102
deg
Color-difference output angle (G)
∠G
Input; Rainbow for both PAL/NTSC
224
236
248
deg
PAL color killer tolerance
VKILLP
0 dB = 150 mV[p-p]
− 57
− 44
− 34
dB
NTSC color killer tolerance
VKILLN 0 dB = 150 mV[p-p]
− 57
− 44
− 34
dB
Hz
APC high-lebel pull-in range
fCPH
Both PAL/NTSC
450
700
APC low-lebel pull-in range
fCPL
Both PAL/NTSC
−700 − 450
Color killer detection output
voltage (color)
VKC
V5 , killer out at which chroma input
data 0A-D6 = 0, 0A-D7 =1
4.5
5.0
Hz
V
Note) *: Since pin 20 is also used partly as service SW when used as ACL, a sufficient care must be taken so as not to become V20
< 0.9 V in carrying out set design.
8
ICs for TV
AN5095K
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Color signal processing circuit (continued)
Min
Typ
Max
Unit
Burst 150 mV[p-p] (PAL), reference is B-out
Color killer detection output
voltage (B & W)
VKBW
V5 , killer out at which chroma input
data 0A-D6 = 0, 0A-D7 =1
0
0.1
0.5
V
Demodulation output -(B-Y)
VDB
Input; Color bar measured at pin 60
for both PAL/NTSC
555
695
835
mV[p-p]
Demodulation output -(R-Y)
VDR
Input; Color bar measured at pin 61
for both PAL/NTSC
430
540
650
mV[p-p]
Demodulation output angle ∠(B-Y)
∠RDB
B-Y axis out of phase
−6
0
6
deg
Demodulation output angle ∠(R-Y)
∠RDR
B-Y axis phase difference
84
90
96
deg
*3
VCWP
AC component, when VCO is set at
4.43 MHz
250
350
450
mV[p-p]
CW output level (3.58 MHz) *3
VCWN
AC component, when VCO is set at
3.58 MHz
50
mV[p-p]
tCW
Period in which CW is outputted at
SECAM, PAL
1.31
1.41
1.51
ms
CW output level (4.43 MHz)
CW output level period
(SECAM) *3
SECAM judgment current
ISECAM
The minimum value to take out current
from pin 59 to discriminate as SECAM
50
100
150
µA
SECAM judgment output
VSE
V5 , det. out, when SECAM signal input
data 0A-D6 = 1, 0A-D7 = 0, SECAM
4.5
5.0
V
PAL/NTSC DC level
V59PN
V59 DC level at PAL/NTSC
0.8
1.3
1.65
V
SECAM DC level
V59S
V59 DC level at SECAM
4.1
4.6
5.1
V
5
6
7
dB
2.2
2.5
2.8
V
RGB processing circuit
DAC data are typicals
Drive adjusting range
Offset adjusting range
GDV
AC change amount for R, B-out between
drive adjustment max. and min.
VCUT-OFF DC change amount for R, G, B-out
between offset adjustment max. and min.
YS threshold voltage
VYSON
Minimum DC voltage at which YS
turns on
1.0
V
YS threshold voltage
VYSOF
Maximum DC voltage at which YS
turns off
0.4
V
External R, G, B pedestal
difference voltage
∆VEPL
YS = 1 V is applied
− 200
0
200
mV
Internal and external pedestal
difference voltage
∆VPL/IE Internal part external part
− 200
0
200
mV
External R, G, B output voltage
VERGB
Input 0.7 V[p-p], contrast 03 = 20 (typ.)
1.8
2.2
2.7
V[p-p]
External R, G, B output difference ∆VERGB Input 0.7 V[p-p], contrast 03 = 20 (typ.)
voltage
0.8
1.0
1.2
Time
External R, G, B contrast variable ECmax/min 03 = 3F
range
03 = 00
12
17
22
dB
Note) *1 to *9: Refer to "Explanation of test methods".
9
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
RGB processing circuit (continued)
External R, G, B frequency
characteristic
Internal and external R, G, B
output voltage ratio
Conditions
Min
Typ
Max
Unit
8
10
MHz
0.78
0.92
1.06
Time
15.33 15.63 15.93
kHz
DAC data are typicals
fRGBC
VE/I
Input 0.2 V[p-p]
External part 0.7 V[p-p]/internal part
0.6 V[p-p] input, contrast 03 = 20 (typ.)
Synchronizing signal processing circuit
Horizontal free run frequency
fHO
Without sync. signal input
Horizontal output pulse duty cycle
τHO
Upward pulse duty cycle
Horizontal pull-in range
fHP
Difference from fH = 15.625 kHz
31
37
± 500 ± 650
43
%
Hz
PAL horizontal free run frequency
fVO-P
Data 01-D7 = 1, 02-D7 = 0, forced
50 Hz mode, without sync. signal input
48
50
52
Hz
NTSC vertical free run frequency
fVO-N
Data 01-D7 = 1, 02-D7 = 1, forced
60 Hz mode, without sync. signal input
58
60
62
Hz
Vertical output pulse width
τVO
For both PAL/NTSC
9
10
11
1/fH
PAL vertical pull-in range
fVPP
fH = 15.625 kHz, forced 50 Hz mode
46
54
Hz
NTSC vertical pull-in range
fVPN
fH = 15.75 kHz, forced 60 Hz mode
56
64
Hz
Horizontal high-level output voltage
V56H
High-level DC voltage
2.8
3.1
3.4
V
Horizontal low-level output voltage
V56L
Low-level DC voltage
0.3
V
Vertical high-level output voltage
V58H
High-level DC voltage
3.9
4.2
4.5
V
Vertical low-level output voltage
V58L
Low-level DC voltage
0.3
V
Screen center variable range
∆THC
Change amount of phase difference between
sync. and H-out of data 0B = 40 to 47
2.6
3.2
4.4
µs
Overvoltage protection operation VX-RAY The pin 55 minimum voltage at which
voltage
H-out does not appear any longer
0.60
0.68
0.76
V
Vertical frequency
discrimination (50)
f50
Vertical frequency at which V5 becomes
low (< 0.5 V)
47
55
Hz
Vertical frequency
discrimination (60)
f60
Vertical frequency at which V5 becomes
high (> 4.5 V)
57
63
Hz
Synchronous signal clamp voltage
V46
V46 clamp voltage
1.1
1.4
1.7
V
Horizontal output start voltage
VfHS
The minimum V50 at f0 > 10 kHz
and horizontal oscillation output is
higher than 1 V[p-p]
3.4
4.2
5.0
V
Sink current when ACK
IACK
The maximum value of pin 21 sink
current at ACK
1.5
2.0
5.0
mA
SCL, SDA signal high level input
VIHI
3.1
V
SCL, SDA signal low level input
VILO
0.9
V
Allowable maximum input
frequency
fImax
100
kbit/s
I2C interface
10
ICs for TV
AN5095K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
VIF circuit
Symbol
Conditions
Min
Typ
Max
Unit
Typical input; fP = 38.9 MHz, VIN = 90 dBµ
Input sensitivity
Maximum allowable input
VPS
Input level at which VPO1 becomes −3 dB
45
dBµ
VPmax
Input level at which VPO1 becomes +1 dB
110
dBµ
SN ratio
SNP
50
dB
Differential gain
DGP
5
%
DPP
5
deg
Difference from sync. peak value
− 45
IRE
∆VBNC Difference from sync. peak value
45
IRE
Differential phase
Black-noise detection level
Black-noise clamp level
*4
*4
∆VBN
RF-AGC operation sensitivity
GRF
Input level difference, when V27 = 1 V
goes to 7 V
0.5
3.0
dB
VCO switch-on drift
∆fPD
Frequency drift from 5 sec. to 5 min. after
SW-on
200
kHz
Inter modulation *5
IM
VfC − VfP = −2 dB, VfS − VfP = −12 dB
46
dB
RF-AGC adjustment sensitivity
SRF
Output voltage in data 1-step,
average change amount of V27
1
4
V/step
AFT offset adjustment sensitivity
SAFT
Output voltage in data 1-step,
average change amount of V30
0.1
0.3
V/step
VCC = ±10%
±15
%
Video detection output fluctuation ∆VP/V
with VCC
Video detection outputtemperature characteristics
∆VP/T
Ta = −20°C to +70°C
±10
%
Input resistance (pin 24, pin 25)
RI24,25
f = 38.9 MHz
1.2
kΩ
Input capacitance (pin 24, pin 25)
CI24,25
f = 38.9 MHz
4.0
pF
fS = 38.9 MHz − 6.0 MHz, P/S = 20 dB
90
110
dBµ
∆V42 = ±0.1 V
2.0
3.5
kHz/mV
3
5
MHz
∆VDP/T Ta = −20°C to +70°C
5
dB
Ta = −20°C to +70°C
300
kHz
AFT center frequency-temperature ∆fAFT/T Input frequency at which AFT output
characteristics
voltage becomes 4.5 V, Ta = −20°C to
+70°C
300
kHz
External mode output DC voltage V41EXT Output DC voltage at AV-SW
outside mode
0.5
1.0
1.8
V
Sound-IF output level
VSIF
VCO control sensitivity
βP
VCO adjustment range
fVCO
RF-AGC delay point-temperature
characteristics
VCO free-running frequencytemperature characteristics
∆fP/T
Free-running frequency change width
at data 0C = 00 to 7F
Note) *1 to *9: Refer to "Explanation of test methods".
11
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
SIF circuit
Symbol
Conditions
Min
Typ
Max
Unit
Typical input; fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dBµ
Input limiting level
VLIM
Input level, when VSOP becomes −3 dB
50
dBµ
AM rejection ratio
AMR
AM = 30%
55
dB
Total harmonic distortion
THD
∆f = ±50 kHz
1.0
%
SN ratio
SNA
∆f = ±50 kHz, fM = 400 Hz, on/off
55
dB
Audio output fluctuation with VCC
∆VS/V
VCC = ±10%
±10
%
Audio output - temperature
characteristics
∆VS/T
Ta = −20°C to +70°C
±10
%
SIF input resistance
RI35
DC measurement
31.5
kΩ
SIF input resistance
RI36
DC measurement
31.5
kΩ
Video-SW crosstalk
(inside → inside)
CTVII
f = 1 MHz, VIN = 1 V[p-p],
inside → inside
− 55
dB
Video-SW crosstalk
(outside → inside)
CTVEI
f = 1 MHz, VIN = 1 V[p-p],
inside → outside, outside → inside
− 55
dB
Audio-SW crosstalk
(inside → inside)
CTAII
fS = 6.5 MHz, fM = 400 Hz, VIN = 1 V[p-p],
fS = 6.5 MHz, fM = 1.0 kHz, VIN = 1 V[p-p]
− 60
dB
AV-SW circuit
Video signal processing circuit
Typical input; 0.6 V[p-p] (VBW = 0.42 V[p-p] stair-step) at G-out
*6
VBL1
Input: All black, difference between
pin 9 = 9 V and open (with RC)
−100
0
100
mV
Black level expansion 2 *
6
VBL2
Input: All black, difference between
pin 9 = 3 V and 9 V
400
700
1000
mV
Black level expansion 3 *6
VBL3
Input: Approx. 20 IRE, voltage
difference between pin 9 = open and
9 V at 03 (contrast) = 3F (max.)
100
300
500
mV
Contrast change by sharpness
∆VCS
Y-out output difference at sharpness
between max. and min.
− 300
0
300
mV
Brightness change by sharpness
∆VBS
Pedestal level DC difference at sharpness − 250
between max. and min.
0
250
mV
Input dynamic change
VImax
03 (contrast) = 20 (typ.)
1.6
V[p-p]
Y-signal SN-ratio
SNY
03 (contrast) = 3F (max.)
53
dB
Black level expansion start point *6
VBLS
Start point at V48 = 4.5 V
37
42
47
IRE
Video output fluctuation with VCC
∆VY/V
VCC1 = 9 V (allowance: ±10%)
±15
%
Video output - temperature
characteristics
∆VY/T
Ta = −20°C to +70°C
±10
%
ACL start point
VACL
V20 at which the output amplitude
becomes 90% when ACL terminal
(V20) is decreased from 5 V
3.4
3.7
4.0
V
Black level expansion 1
Note) *1 to *9: Refer to "Explanation of test methods".
12
ICs for TV
AN5095K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Color signal processing circuit
Symbol
Conditions
Min
Typ
Max
Unit
Burst 150 mV[p-p] (PAL), reference is B-out
Demodulation output residual carrier
VCAR1
2fSC level of pin 60 and pin 61
30
mV
Color-difference output residual
carrier
VCAR2
2fSC level of pin 15, pin 16 and pin 17
50
mV
VCO free-running frequency (PAL)
fCP
Difference from f = 4.433619 MHz
−300
300
Hz
VCO free-running frequency (NTSC)
fCN
Difference from f = 3.579545 MHz
−300
300
Hz
−300
300
Hz
fCO fluctuation with VCC
∆fC /VCC VCC1 = 9 V (allowance: ±10%),
VCC3 = 5 V (allowance: ±10%)
Static phase error (PAL)
∆θP
Tint gap at ∆fC = −300 Hz to +300 Hz
change
5
deg/
100 Hz
Static phase error (NTSC)
∆θN
Tint gap at ∆fC = −300 Hz to +300 Hz
change
5
deg/
100 Hz
PAL/NTSC ratio
RP/N
Output amplitude ratio between PAL
and NTSC
0.7
1.0
1.3
Time
∆VPAL
Pin 61: Output amplitude difference
per 1H at -(R-Y) terminal
50
mV
Band to become −3 dB
1.0
MHz
VCC1 = 9 V (allowance: ±10%),
VCC3 = 5 V (allowance: ±10%)
±15
%
±15
%
Line crawling
Color-difference output bandwidth
fCC
Color-difference output fluctuation
with VCC
∆VC/V
Color-difference output temperature characteristics
∆VC/T
Ta = −20°C to 70°C
PAL/NTSC output impedance
RO60,61PN DC measurement
400
510
620
Ω
SECAM output impedance
RO60,61S DC measurement
100
kΩ
Color, black & white DC
difference voltage
∆VCBW Pedestal voltage difference between
with and without burst signal
− 60
0
60
mV
(C-Y)/Y ratio *7
RC/Y
Color bar input, B-out contrast typ.
color data 00 = 30
0.9
1.2
1.5
V[0-p]/
V[0-p]
fYS
fYS , when YS input is 3 V[0-p] and
output level is −3 dB
7
MHz
RGB processing circuit
YS change-over speed
Outside R, G, B input dynamic
range
VDEXT
Contrast max. data 03 = 3F
1.0
V[p-p]
Inside and outside crosstalk
CTRGB
Leakage at f = 1 MHz, 1 V[p-p],
YS = 5 V
−50
dB
Synchronizing signal processing circuit
Lock detection output voltage
VLD
V18 at horizontal AFC lock
5.7
6.3
6.9
V
Lock detection charge and
discharge current
ILD
DC measurement
±0.6
±0.8
±1.1
mA
Note) *1 to *9: Refer to "Explanation of test methods".
13
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Synchronizing signal processing circuit (continued)
FBR (R, G, B) slice level
VFBP
Pin 50 minimum voltage at which
blanking is applied to R, G, B output
0.4
0.75
1.1
V
FBP (AFC2) slice level
VFBPH
Pin 50 minimum voltage in which
AFC2 operates
1.5
1.9
2.3
V
µH
DC measurement
30
37
44
µA/µs
βH
β curve slant near f = 15.75 kHz
1.4
1.9
2.4
Hz/mV
Delay from H sync. rise for both PAL/
NTSC
0.2
0.4
0.6
µs
WBGPP
3.4
4.0
4.6
µs
WBGPN
2.5
3.0
3.5
µs
Pin 62 DC voltage during BGP period
4.5
4.7
4.9
V
H blanking pulse output voltage VHBLK
Pin62 DC voltage during H blanking
pulse period
2.1
2.4
2.7
V
V blanking pulse output voltage VVBLK
Pin62 DC voltage during V blanking
pulse period
2.1
2.4
2.7
V
PAL V blanking pulse width
WVP
Pulse width at f = 15.625 kHz
1.31
1.41
1.51
ms
NTSC V blanking pulse width
WVN
Pulse width at f = 15.73 kHz
1.01
1.11
1.21
ms
TFBP
Time from H-out rise to FBP center
12
19
µs
VAFBP
2.5
5.0
V
tBUF
4.0
µs
Start condition set-up time
tSU, STA
4.0
µs
Start condition hold time
tHD, STA
4.0
µs
Low period SCL, SDA
tLOW
4.0
µs
High period SCL
tHIGH
4.0
µs
Rise time SCL, SDA
tr
1.0
µs
Fall time SCL, SDA
tf
0.35
µs
Data set-up time (write)
tSU, DAT
0.25
µs
Data hold time (write)
tHD, DAT
0
µs
Acknowledge set-up time
tSU, ACK
3.5
µs
Acknowledge hold time
tHD, ACK
0
µs
Stop condition set-up time
tSU, STO
4.0
µs
Horizontal AFC µ
Horizontal VCO β
Burst gate pulse position
*8
PBGP
PAL burst gate pulse width *8
NTSC burst gate pulse width
*8
Burst gate pulse output voltage
FBP allowable range
*9
FBP maximum allowable input
voltage
VBGP
I2C interface
Bus free before start
Note) *1 to *9: Refer to "Explanation of test methods".
14
ICs for TV
AN5095K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
3-bit, 6-bit, 7-bit DAC DNLE
L3,6,7
Conditions
Min
Typ
Max
Unit
1LSB = {data (max.) − data (00)}
/7, 63, 127
0.1
1.0
1.9
LSB/
Step
L8
1LSB = {data (FF) − data (00)} /255
(7F → 80 excluded)
0.1
1.0
1.9
LSB/
Step
8-bit DAC DNLE (80)
L8-80
LSB = {data (FF) − data (00)} /255
(7F → 80)
0.1
1.0
2.9
LSB/
Step
AFT DAC overlap
∆Step
8-bit of AFT double-stage changeover overlap
27
32
37
Step
DAC
8-bit DAC DNLE
• Explanation of test methods
*1: RF AGC delay point adjusting range: ∆VRFdp
VIF input level
[dBµ]
In the case of VIF gain reduction curve (figure 1), if the RF
AGC delay point adjustment DAC (0 A) goes 00 to 3F, the
internal comparison voltage changes by ∆V, and the delay point
adjustment range is determined.
00
110
100
3F
80
49
∆V
[V]
IF AGC terminal level
Figure 1. Gain reduction curve
*2: AFT discrimination sensitivity: µAFT
Adjust DAC (0C-D7) and DAC (09) so that the AFT output voltage (V30) becomes approx. 4.5 V when fP =
38.9 MHz.
Measure ∆V30 when fP = 38.9 MHz ±25 kHz.
*3: Refer to "■ Technical Information 4. 7) PAL/NTSC, SECAM interface".
*4: Black noise detection level: ∆VBN
Black noise clamp level: ∆VBNC
∆VBNC
VP
∆VBN
Figure 2. Black noise rejection characteristic
*5: Inter modulation: IM
Apply the signal of fP = 38.9 MHz, 90 dBµ and fix the voltage of pin 37 (IF AGC) under that condition.
fP = 38.9 MHz, 82 dBµ
Input those 3 signals and measure 1.57 MHz component of the
fP = 38.9 MHz − 4.43 MHz, 80 dBµ detection output.
fP = 38.9 MHz − 6.0 MHz, 70 dBµ
vieo component [rms]
IM = 20Log
V1.57 MHz [rms]
15
AN5095K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Explanation of test methods (continued)
*6: Black level extension: VBL
Y output
VBLS
VBL1
VBL3
Pedestal level
Y output when
operation is off
(∝Y input)
VBL2
Figure 3. Black level expansion characteristics
In the black level extension characteristics (figure 3), when
the voltage of pin 9 (black level detection filter) is VCC1 = 9 V,
the operation of the black level extension circuit is turned off and
the characteristic becomes as shown by the line
. Also, if
the voltage of pin 9 is set at 3 V, the black level extension forcibly
comes to start and the characteristic becomes as shown by the
line
. When pin 9 is set by only R, C filter, the black level
extension characteristic as shown by the line
can be
obtained.
VBL3 shows an output level difference between the black
extension is off and the normal operation when the video input
level is constant in 20 IRE.
VBLS is a point where the black extension comes to start and can
be adjusted by the DC voltage of pin 48 (CIN).
V48
2.5 V
4.5 V
6.5 V
Start point
52 IRE
42 IRE
32 IRE
*7: (C-Y)/Y ratio: RC/Y
C-Y is the voltage from 0 level to the peak of B-out when color is typ. (00 = 20) and contrast is typ. (03
= 20). Y is the voltage from the pedestal of contrast at typ. to 100 IRE white level.
*8: Burst gate pulse
WBGP
H-sync.
PBGP
Pin 46
Sync. input
As shown in figure 4, the position of the burst gate pulse is
the period from the rise time of the H-sync. signal of pin 46 to
the rise time of BGP.
BGP (4 µs)
Pin 62
SCP output
Figure 4. Burst gate pulse
*9: FBP allowable range : tFBP
tFBP
Pin 56
Hor. pulse
output
Pin 50
FBP
input
Figure 5. FBP allowable range
16
Figure 5 shows the relationship between Hor. pulse and FBP.
The phase delay from Hor. pulse to FBP differs from set to set.
This IC has an adjusting function for the screen center position.
The phase range in which this function normally operate is tFBP.
ICs for TV
AN5095K
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
1
2
3
Description
9V
(VCC1)
Pin
1,
2, 3
300 Ω
C
0.01 µF
300
Ω
BGP
Brightness
control
150 µA
4
5V
(VCC3)
3.3 V
0.47 µF
4
137
270 Ω
kΩ
2.5 V
1V
1.0 MΩ
Killer
det.
circuit
voltage
Pin 1; Primary color signal clamp pin (R)
DC
Pin 2; Primary color signal clamp pin (G) approx. 7 V
Pin 3; Primary color signal clamp pin (B):
For the clamp pulse, the internal clamp
pulse (BGP) is used.
Killer filter pin:
DC
Filter pin of killer detection circuit (operates approx. 3.3 V
for BGP period).
Killer turns on (without color output) at a
voltage of 2.8 V or lower.
BGP
9V
2.8 V
100 µA
5
Microcomputer VCC
(5 V)
Floating
resistance
33 kΩ
To
microcomputer
5
175 Ω
40 µA
On
10 kΩ
0.47 µF
Off
6
APC filter pin:
DC
Filter pin of APC detection circuit (operates approx. 2.5 V
for BGP period).
The detection sensitivity becomes high
when the external resistance is high, (tend
to be pulled-in easily. tend to be influenced by noise).
5V
(VCC3)
1V
SW
2.5 V
BGP
β curve
fC
max. 1 mA
VCO
circuit
R
7.5
kΩ
0.047 µF
6
40
kΩ
2.2 µF
3.3 V
APC
det.
circuit
Killer, 50 Hz/60 Hz, SECAM det. output pin:
DC
Selective output by SW (I2C bus).
Low level
The load resistance 33 kΩ should be connected
0.2 V
to microcomputer VCC .
High livel
5V
270 Ω
V6
Stop APC circuit by short-circuiting 40 kΩ
at SECAM.
17
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
7
8
DC 2.7 V 4.43 MHz
7
C7
12 pF
IP1
IP2
100 µA
500 µA
IN2
DC 2.7 V 3.58 MHz
8
C8
15 pF
IN1
100 100
µA µA
500
µA
9
Description
voltage
Pin 7; Chroma. oscillation pin (4.43 MHz)
Pin 8; Chroma. oscillation pin (3.58 MHz):
AC
f = fC
Either one of the oscillations of 4.43 MHz
approx.
or 3.58 MHz is performed by chroma.
0.7 V[p-p]
oscillation pin.
Frequency changeover is carried out by
08-D7 bit of I2C bus.
When 08-D7 = 0;
IP1 , IP2 turn on, and 4.43 MHz oscillates
When 08-D7 = 0;
IN1, IN2 turn on and 3.58 MHz oscillates
The pattern from pin to oscillator should
be as short as possible.
Black level detection pin
DC
approx. 5.1 V
Blanking off SW pin:
Black level detection filter pin for black
5V
extension circuit.
(VCC3)
Excluding the blanking period, holds the
80
most black Y level.
kΩ
The sensitivity that the black extension
(area judged as black) comes work is
To
blanking variable by means of external R. When R
circuit
is large, it responds to a small area.
Apply VCC (9 V) to pin 9 when stopping
the black extension circuit.
Blanking is turned off when pin 9 is GND
(black extension is also off).
9V
(VCC1)
-Y
80 µA
10 kΩ
75
kΩ
10 kΩ
5.1 V
9
100 µA
Black
expansion
circuit
R
180 kΩ
10
50 µA
4.7 µF
9V
(VCC1)
To R, G, B
output
circuit
From
microcomputer 2.7 kΩ
10
30 kΩ
0.7 V
100 µA
18
YS input pin:
Fast-blanking pulse input pin for external
analog R, G, B.
On at a voltage over 1 V.
Off at a voltage under 0.4 V.
AC
(pulse)
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
11
12
13
Description
9V
(VCC1)
100 µA
Pin 11
12
13
voltage
Pin11; External R input pin
Pin12; External G input pin
Pin13; External B input pin:
The output will change linearly depending on the input level.
AC
VCC1 (9 V typ.):
Output block of VIF, SIF circuit.
AV SW circuit.
Video circuit.
RGB circuit.
DC
9V
Pin15; R-out pin
Pin16; G-out pin
Pin17; B-out pin:
BLK level approx. 0.9 V.
Black (pedestal) level approx. 2.2 V.
Blanking can be released by setting pin 9
(black level detection pin) at 0 V.
AC
Horizontal synch. detection pin:
The phase of horizontal sync. signal and
horizontal output pulse is detected and outputted.
Pin 18 becomes low if out of synchronization.
Color control becomes minimum and chroma
signal disappears in asynchronous state.
Pay attention to impedance when the voltage
of pin 18 is utilized for microcomputer.
(500 kΩ or higher ZO is required)
DC
When
synchronous
approx. 6 V
When
asynchronous
approx. 0.3 V
To
color
circuit
BGP
200 µA
14
15
16
17
100 Ω
100 µA
50 Ω
C-out
9V
(VCC1)
Pin 15
16
17
500 µA
18
To
chroma
circuit
6.3 V
(VCC2)
5V
(VCC3)
10 kΩ
2.8 V
800 µA
I1
12 kΩ
12 kΩ
800 µA
I2
50 µA
Pin56
H-out
Pin46
H/V sync. in
18 ZO
1 MΩ
0.022
µF
10 kΩ
H Sync. period
When pin 56 is high: I1 on
When pin 56 is low: I2 on
19
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
19
Description
GND:
R, G, B circuit.
DAC, I2C circuit.
20
9V
(VCC1)
5.9 V
60 kΩ
To contrast
circuit
60 kΩ
2.1 V
6.9 kΩ
2.3 V
7.1
kΩ
7.1
kΩ
Contrast
control
6.9
kΩ
100 µA
50
µA
1 kΩ
I2C bus data input pin
AC
(pulse)
I2C clock input pin
AC
(pulse)
100 kΩ
1.7 V
21
From
microcomputer
ACK
30 kΩ
To logic
circuit
30 kΩ
5V
(VCC3)
22
100 kΩ
Clock
1 kΩ
22
From
microcomputer
50
µA
100 kΩ
1.7 V
30 kΩ
20
Service SW.
Note) Since pin 20 also serves as the service
SW when used as ALC, design the set
so as not to allow V20 < 0.9 V.
5V
(VCC3)
100 kΩ
23
DC
approx. 3 V
100 µA
21
Data
20
4.7
µF
6.9 kΩ
2.3 V
±1 V 100 µA
3.5 V
ACL pin:
If DC voltage of pin 20 is decreased from
the outside, the contrast is turned down.
voltage
To logic
circuit
30 kΩ
VCC3-1 (5 V typ.):
For VIF and SIF circuitr.
DC
5V
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
24
25
5V
(VCC3)
3.5 V
Pin24; VIF input pin-1
Pin25; VIF input pin-2:
Balanced input by VIF amp. input.
voltage
AC
f = fP
DC level
approx. 2.7 V
27 kΩ
1.2 1.2
kΩ kΩ
25
SAW
24
150 µA 150 µA
26
27
5V
(VCC3)
To tuner
27
GND:
For VIF and SIF circuit.
DC
RF AGC output pin:
Open collector output and usable at any
bias value (12 V max.).
DC
1F AGC
bias
RF AGC
control bias
40
kΩ
28
9V
(VCC1)
Audio output pin
AC
0 kHz to
20 kHz
De-emphasis pin:
De-emphasis filter pin for sound detection
signal.
External C for PAL/NTSC is the same
(internal impedance changes).
PAL: 12 kΩ//60 kΩ × 1 200 pF = 48 µs
AC
0 kHz to
20 kHz
270 Ω
28
100 µA 400 µA
29
9V
(VCC1)
1.7 kΩ
Detection output
120
kΩ
100 µA
PAL
60 kΩ
NTSC
29
1200 pF
NTSC: 60 kΩ × 1 200 pF = 72 µs
21
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
30
1.1 kΩ
9V
(VCC1)
1.1 kΩ
9V
30
1.1 kΩ
To tuner
AFT output pin:
Offset of center voltage is adjusted by
using bus.
When AFT defeat SW is turned on (09 =
00), V30 becomes a value determined by
external resistor-divider.
µ of AFT is variable by impedance of
external resistor.
voltage
DC
40 kΩ 1.1 kΩ
350 µΑ
max.
31
9V
(VCC1)
3.4 V
50 µA
Ext. video
30 kΩ
To
video SW
50 kΩ
31
External video input signal pin:
AC
External video signal input pin and DC cut 1 V[p-p]
input.
(compost)
Typical 1 V[p-p].
10 µF
DC
approx. 2.0 V
100 µA
9V
(VCC1)
32
10 kΩ
1.7 kΩ
32
4.5 V typ.
1.7 kΩ
3 kΩ
10 µF
3 kΩ
Decoupling pin:
S-curve inside the IC is broad-band.
However, DC feedback should be applied
so that DC voltage of output signal becomes
constant.
DC level (4.5 V typ.).
fS → high: V32 → low
DC
20 kΩ
100 µA
13 µA
33
9V
(VCC1)
33
4.4 V
10 pF 30 kΩ
SIF in
1.8
kΩ
30 kΩ
200 µA
9V
5 V to 7 V
100 µA
Sharpness
contorol
22
100 µA
To SIF
limitter amp.
SIF signal input pin:
Used in common as DC input pin for
sharpness control.
DC bias is applied from outside (for
sharpness control DC: 5 V to 7 V).
AC+DC
AC
f = fS
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
34
5V
(VCC3)
53 kΩ
Description
voltage
SIF internal power supply stabilization filter
pin
DC
1.24 V
SIF signal input pin:
Input pin for SIF2 and internally biased.
AC+DC
AC
f = fS
DC
3.0 V
To SIF PLL
1.24 V
34
1 µF
56 µA
35
9V
(VCC1)
100 µA
SIF in
Pin 35, 36
36
40 kΩ
3.7 V
30 kΩ
30 kΩ
9V
1.8 kΩ
200 µA
100 µA
To SIF
limitter amp.
37
5V
(VCC3)
To
IF amp.
37
30 µA
SIF signal input pin:
Input pin for SIF1 and internally biased.
IF AGC filter pin:
DC
IF AGC filter pin. The current obtained from approx. 2 V
peak AGC circuit is smoothed by an
external capacitor.
When C goes smaller, the respons
charaeteristic becomes faster but the sag
tends to appear easily.
0.47 µF
38
50 µA
To
video SW
9V
(VCC1)
3.0 V
Int. video
30 kΩ
Pin 38, 40
10 µF
680 kΩ
Internal video input pin 1:
Input pin for the signal detected by VIF
circuit (internal video signal).
DC cut input.
Typical 1 V[p-p]
AC
1 V[p-p]
(compost)
DC level
approx. 1.6 V
23
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
39
Description
SIF APC filter pin:
Filter pin for SIF APC circuit.
9V
(VCC1)
voltage
DC
VCO
(4 MHz to 7 MHz)
P.C.
7.5 kΩ
8.4 kΩ
To
audio SW
800 µA
13 kΩ
2 pF
72 µA
39
5.6 kΩ
1 000 pF
200 µA
40
9V
(VCC1)
3.0 V
50 µA
Int. video
To
video SW
30 kΩ
Pin 38, 40
Internal video input pin 2:
Input pin for the signal detected by VIF
circuit (internal video signal).
DC cut input.
Typical 1 V[p-p].
10 µF
680 kΩ
41
75 µA
DC level
approx. 1.6 V
VIF detection output pin:
Adjust at 2 V[p-p] by I2C bus (upper 4-bit of
0 A is used).
9V
(VCC1)
41
AC
1 V[p-p]
(compost)
AC
2 V[p-p]
Note) At AV mode,
VIF detection signal output is not given.
42
5V
(VCC3)
50 µA
1
SW
0
500 Ω
20 kΩ
42
150 Ω
3.25 V
75 µA
0.47 µF
24
To
VCO
25 µA
APC1 filter pin:
Filter pin for APC1 circuit of VIF.
Lock detection circuit of VCO is built in
the IC inside and the time constant of
APC filter is changed over.
When locked
SW: 0
When not locked
SW: 1
DC
approx. 2.5 V
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
43
5V
(VCC3)
VIF oscillation pin:
Depending on VIF frequency, change
oscillation coil.
The oscillation frequency is 1/2 of fP .
100 Ω 300 Ω
43
800 µA 400 µA
voltage
AC
f = fP /2
approx.
0.7 V[p-p]
DC level
approx. 3.9 V
100 µA
44
50 µA
9V
(VCC1)
Video output pin:
This pin outputs int.video 1, int. video 2 or
ext. video signal selected by AV SW.
44
AC
2 V[p-p]
DC level
approx. 4.5 V
400 µA
45
9V
(VCC1)
47 kΩ
50 µA
4.3 V
45
1.8 kΩ
10 µA
43 kΩ
46
2 V[p-p]
RH 0.1 µF
270 Ω
16 kΩ
5V
(VCC3)
16 kΩ
Video input pin:
Input pin for video signal (composite video
also available).
Typical input 0.6 V[p-p].
Sync. top is clamped at 3.5 V.
The video signal should be inputted with
low impedance.
Vertical and horizontal sync. separation
input pin:
Sync. top is clamped at 1.3 V.
AC
0.6 V[p-p]
AC
2 V[p-p]
To H-sync. sep.
V-sync. sep.
1.3 V
46
CH
1 200 pF
20 µA
47
VCC3-2 (5 V typ.)
For chroma jungle circuit.
DC
5V
25
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
5V
(VCC3)
48
Chroma
signal 1 000 pF
12.5 pF
voltage
AC+DC
burst
Pin 48 is chroma signal input pin, and the 150 mV[p-p] typ.
15 kΩ
9V
10 kΩ
To
chroma amp.
2.5 V
50 µA
48
10 kΩ
Chroma signal input pin
Black extension start point adjusting pin:
black extension start point is adjusted by
DC voltage applied from the outside.
DC
4.5 V typ.
9V
(VCC1)
To
black level
expansion
100 µA
25 µA
49
50
100
µA
1.9 V
24 kΩ
50
µA
5V
(VCC3)
50
µA
100
µA
To
AFC
To
H-BLK
40
kΩ
0.7 V
60
kΩ
50
GND:
For video chroma jungle circuit.
DC
0V
FBP input pin:
FBP input pin for horizontal blanking and
AFC circuit.
Threshold level
H-BLK: 0.7 V
AFC: 1.9 V
It becomes all blanking when DC 1.3 V is
applied from the outside.
AC
FBP
Horizontal stabilized power supply pin:
Stabilized power supply for starting up the
horizontal circuit that has a zener circuit inside.
DC
6.3 V
40
kΩ
50 µA
51
I51
15 mA typ.
VCC2
51
To hor. OSC
V51
6.3V
47 µF
I51
52
6.3 V
(VCC2)
2 kΩ
2 kΩ
1.9 V
To hor. out
V52
AFC2
detecter
I
From DAC 52
(hor. position)
1 kΩ
1 kΩ
0.022 µF
500 µA max.
26
3.3 V
50 µA
Horizontal AFC2 filter pin:
Comparing the phase of FBP and that of
inside pulse of the IC, charge to and discharge from the capacitor connected to
pin 52 are done.
Performed by charging and discharging
in DC current by the screen center
position adjusting DAC.
V52 changes depending on the time from
H-out to FBP, and the slice level of
internal sawtooth waveform changes.
DC
1.5 V to
3.5 V
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
53
6.3 V
(VCC2)
4.3 V
R1
27 kΩ
AFC1
detecter
27 kΩ
1.5 V
53
22 µF
C2
Hor. sync.
Hor.
OSC
0.033
µF
C1
820 Ω
R2
1 000 µA
200 µA
voltage
Horizontal AFC1 filter pin:
Comparing the phase of horizontal sync.
signal and that of inside pulse of the IC,
charge to and discharge from the capacitor
connected to pin 53 are done.
R1, R2, C1, and C2 are lag-lead filter for
AFC1.
Horizontal
βcurve
fH
DC
4.3 V typ.
V53
6.3 V
(VCC2)
54
Description
22 kΩ
Horizontal oscillation pin:
Oscillate at 32 × fH ≈ 503 kHz by means of
ceramic oscillator.
Horizontal and vertical pulse are generated
by means of count down circuit in the IC.
(
AC
f = 32 fH
approx.
503 kHz
)
300 Ω
10
kΩ
54
100 µA
220 pF
80 µA
10
kΩ
200 µA
55
6.3 V
(VCC2)
4.3 V
20 kΩ
40 kΩ
20 kΩ
3V
To
count down
20 kΩ
55
56
6.3 V
(VCC2)
4.3 V
Overvoltage protection input pin:
Input pin for the protect circuit against X-ray
due to overvoltage.
Shut-down is started by internal logic
circuit when H-out pulse is low.
(Prevent the horizontal drive Tr destruction.)
Horizontal pulse output pin:
Duty cycle is approx. 36%.
DC
normally
0V
AC
pulse
19 kΩ
50 Ω
10 kΩ
40 kΩ
56
2.8 V
0V
Hor. Out
27
AN5095K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
57
4.3 V
50 kΩ
5V
(VCC3)
3 kΩ
16 kΩ
To ver.
count
down
4 kΩ
270 Ω
57
R2 220 Ω
200 Ω
R1
330 kΩ
58
C1
0.33 µF
5V
50 kΩ (VCC3)
Description
voltage
Vertical sync. signal clamp pin:
Peak clamp pin for separating vertical sync.
signal.
Although the integral amount of vertical
sync. signal itself has been determined by
the internal time constant, the trigger
application timing is determined by
selecting external constant R1, C1.
R1 must be used at higher than 200 kΩ.
R2 is resistor for emitter current restriction.
AC
f = fV
Vertical pulse output pin:
Negative polarity, pulse width of 10H.
AC
pulse
58
4.3 V 43 kΩ
0V
59
fC
12
kΩ
56.2 kΩ
50
µA
13.7 kΩ
50
kΩ
61.5 kΩ
9V
(VCC1)
12
kΩ
59
To
SECAM IC
200 µA
100 µA
SECAM SECAM
detecter
SECAM interface pin:
AC+DC
Input and output pin for interfacing with
AC
SECAM IC.
250 mV[p-p]
It becomes the SECAM mode when the
or 0 mV[p-p]
current sink from pin 59 is 100 µA or more. DC 4.4 V
At SECAM
or 1.1 V
DC 4.4 V + AC 250 mV[p-p]
At non-SECAM
DC 1.1 V + AC 250 mV[p-p]: 4.43 MHz
or
0 mV[p-p]: 3.58 MHz
SECAM
60
61
100 µA
100 µA
100 µA
5V
(VCC3)
-(B-Y)
60
61
-(R-Y)
To 1HDL
SECAM
0V
SECAM
28
1.5 kΩ
2.5 kΩ
Pin60; -(B-Y) output pin
Pin61; -(R-Y) output pin:
The output circuit turns off at SECAM
and becomes a high impedance state.
Outputs to 1HDL.
AC
-(B-Y)
-(R-Y)
1.5 kΩ
DC level
approx. 2.1 V
ICs for TV
AN5095K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
62
37 kΩ
15 kΩ
5V
(VCC3)
V-BLK
42 kΩ
Description
voltage
Sand-castle pulse output pin:
The sand-castle pulse is outputted to 1HDL
and SECAM IC.
AC
pulse
4.7 V
2.4 V
62
63 kΩ
44 kΩ
H-BLK
BGP
63
64
9V
(VCC1)
100 µA
Pin 63, 64
Pin63; -(B-Y) input pin
Pin64; -(R-Y) input pin:
The color difference signal outputted from
1HDL is inputted.
The pedestal level is clamped at 4 V by
means of clamp circuit.
AC
-(B-Y)
-(R-Y)
To
color
circuit
From
1HDL
CCP
200 µA
DC level
4V
■ Usage Notes
1. The following terminals are not strongly resistant to surge latch-up. The precautions should be observed when
using the IC.
1) Serge
The + side breakdown voltage of pin 22 and pin 23 is approx. 190 V if the surge source capacitance is 200 pF.
The + side breakdown voltage of pin 45 is approx. 160 V if the surge source capacitance is 200 pF.
Therefore, do not apply a surge stronger than that.
2) Latch-up
For pin 18, pin 21, pin 22, pin 51, pin 54, pin 55 and pin 56, the latch-up occurs by the + side surge of approx.
150 V (surge source capacitance 200 pF). Therefore, do not apply a surge stronger than each voltage indicated for
each pin.
Note) The stronger surge common to the above 1) and 2) means that the establishment of either one of the following two
cases; the surge source capacitance is larger than the indicated value or the surge voltage is higher than the indicated
value.
29
AN5095K
ICs for TV
■ Usage Notes (continued)
2. The protection diode of each Pin is as shown in the following table;
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
With ( ● ) or Without
VCC
●
●
●
●
●
●
●
●
●
●
●
●
●
×
●
●
●
●
×
●
× × ×
●
●
×
( × ) Surge diode
GND
●
●
●
●
●
●
●
●
●
●
●
●
●
×
●
●
●
●
×
●
× × ×
●
●
×
VCC node being connected
1 1 1 3 3 3 3 3 1 1 1 1 1
1 1 1 2
1
3 3
Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
With ( ● ) or Without
VCC
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
×
●
×
●
×
●
( × ) Surge diode
GND
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
×
●
×
●
×
●
VCC node being connected
1 1 1 1 1 1 1 3 1 1 3 1 1 1 1 3 3 3 1 1
Pin 53 54 55 56 57 58 59 60 61 62 63 64
With ( ● ) or Without
VCC
●
●
●
●
●
●
●
●
●
●
●
●
( × ) Surge diode
GND
●
●
●
●
●
●
●
●
●
●
●
●
VCC node being connected
VCC node
1 → VCC1 (9 V system)
2 → VCC2 (6.5 V system)
3 → VCC3 (5 V system)
3
3
2
VCC
VCC
side diode
2 2 2 2 3 3 1 3 3 3 1 1
GND
side diode
GND
■ Technical Information
• Explanation of each block
1. VIF
1) Adapting the inter carrier PLL coherent detection method.
2) The VCO of VIF is controlled by I2C bus (7-bit): Oscillation at 1/2 of the fP frequency. (2 times multiplier
circuit is inside.) Built-in double APC circuit of frequency and phase.
3) AFT without coil: It is applicable to both VS and FS tuners by amplifying the error voltage of APC and
making S-curve to obtain AFT output. The DC offset is controlled by I2C bus (9-bit). The AFT defeat is also
possible.
4) Since the VCO oscillates at 1/2 frequency, a high-frequency disturbance such as tweet is reduced.
5) The video detection output is 2.0 V[p-p] typical: The level adjustment is carried out by I2C bus .
6) The built-in lock detection circuit realizes a stable pulling by the changeover of time constant for APC.
7) The delay point of RF AGC is adjusted by I2C bus (6-bit).
2. SIF
1) The SIF detection uses PLL coherent detection method.
2) 4 frequencies are changed over for use as the VCO oscillation frequency.
At NTSC; 4.5 MHz
At PAL; 5.0 MHz, 5.5 MHz, 6.5 MHz
3) It is possible for the SIF detection output to deal with the difference in deviation of PAL/NTSC by changing
over an amplifier of +6 dB.
4) Built-in video/SIF SW.
Video SW; 2 systems (with 6 dB amp.)
SIFSW; 3 systems
30
ICs for TV
AN5095K
■ Technical Information (continued)
• Explanation of each block (continued)
3. Video
1) The delay line aperture control (contours emphasis type) is used for sharpness control.
The circuit as well as the black extension circuit realizes a high picture quality.
2) Built-in pedestal clamp filter.
3) Service SW: (Y contrast min., vertical output stop).
4. Chroma
1) The circuit realizes an adjustment free condition by using base band 1HDL (externally attached).
2) Incorporation of ACC filter reduces the number of external components.
3) It is possible to support the other systems by the mode changeover I2C bus (1) PAL/NTSC, (2) 4.43 MHz/3.58
MHz, (3) Forced PN/ForcedSECAM.
4) Equipped with the killer output terminal for system discrimination by microcomputer. (When killer is on →
0 V, killer is off → 5 V)
5) The color difference output terminal becomes a high impedance state at SECAM.
6) Since the circuit is provided with the color difference input terminal, the features of ICs such as the AN5244
(IC for color signal compensation) can be connected.
7) PAL/NTSC, SECAM interface (pin 59)
Mode
PAL/NTSC
SECAM
DAC(3.58 MHz/4.43 MHz) Pin59 output
fC
AC level
3.58 MHz
Approx. 1.3 V
3.58 MHz
×
4.43 MHz
Approx. 1.3 V
4.43 MHz
250 mV[p-p]
3.58 MHz
Approx. 4.6 V
4.43 MHz
250 mV[p-p]
Output for V-blank
4.43 MHz
Approx. 4.6 V
4.43 MHz
250mV[p-p]
period only *
CW output
Note) *: AC component of 4.43 MHz is outputted in the vertical sweep period only.
V-sync.
Approx.
DC 4.6 V
Input
250 mV[p-p]
Pin 59
V-blank
(R, G, B out)
5. RGB
1) It supports not only the OSD but also the teletext signal in an analog input system.
(The output level is interlocked with the contrast of TV signal side.)
2) The white balance (drive, cut-off) adjustment is performed by I2C bus.
6. Jungle
1) The horizontal circuit uses the count down method by 32 fH ceramic oscillator. The AFC circuit uses double
method.
2) By the adaption of trigger method count down circuit, the vertical circuit can obtain a stable vertical synchronization without adjustment at all times. The output is pulse signal, so that there is no degradation of interface
due to the influence of pattern layout.
31
AN5095K
ICs for TV
■ Technical Information (continued)
• Explanation of each block (continued)
6. Jungle (continued)
3) Built-in frequency discrimination circuit: The circuit outputs the judgment results of 50 Hz/60 Hz in accordance with the frequency of the vertical synchronizing signal.
(60 Hz → high)
45
Input frequency
Judgement
55
Hold
50 Hz
(Low)
Output voltage
65
60 Hz
(High)
Hold
4) The output holds the previous state when the input frequency is 45 Hz or less and 65 Hz or more, and the
output changes for the first time when judged as 50 Hz or 60 Hz for 3 consecutive vertical periods.
5) The horizontal detection circuit and X-ray protection circuit (shut-down method) are built in.
6) The screen center position is adjustable by the I2C bus. (±1.6 µs)
7) For the blue-back in a weak electric field, the stable screen image is held by the vertical trigger off mode ( I2C
bus).
7. I2C bus
1) Incorporating 14 DAC controls and 12 SWs for eliminating the need for the adjustment of set mechanism.
2) Provided with automatic increment function.
• Sub address 0 *: Automatic increment mode.
(When data are sent in regular succession, sub address changes successively and data are inputted.)
• Sub address 8 *:
(When data are sent in regular succession, data are inputted with the same sub address.)
3) I2C Bus Protocol
• Slave address: 10 001 010 (8AH)
• Slave address format
S
Slave address
Start
condition
0
A
Write
Sub address
A
Data byte
A
Acknowledge bit
P
Stop
condition
4) Sub address byte and data byte format
The description in ( ) shows the initial state.
Sub address
00
(21H)
01
(21H)
02
(41H)
03
(21H)
32
D7
P/N
(0 → P)
Ver. auto
(0 → auto)
Ver. OSC
(0 → 50)
SIF
SW
D6
PN/S
(0 → PN)
Ver. TRG
(0 → normal)
D5
Data byte
D4
D3
Color
Tint
Brightness
Video
SW
Contrast
04
(81H)
Cut off R
05
(81H)
Cut off G
06
(81H)
Cut off B
D2
D1
D0
ICs for TV
AN5095K
■ Technical Information (continued)
• Explanation of each block (continued)
7. I2C bus (continued)
4) Sub address byte and data byte format (continued)
The description in ( ) shows the initial state.
Sub address
07
(41H)
08
(41H)
D7
SIF VCO
SW1
Chroma
VCO
(0 → 4.43)
D6
Data byte
D4
D3
D5
D2
D1
D0
Drive R
Drive B
09
(01H)
AFT
offset
0A
(21H)
50 Hz/60 Hz
killer out
SW
0B
(45H)
0C
(C1H)
SIF/ext.
SW
AFT offset
SW
SECAM det.
SW
RF AGC
delay
Video
adjust
SIF VCO
SW2
H center
VIF VCO
5) Contents of I2C bus control
(1) The control information is in the direction that the output increases when the datum increases.
(Example: Contrast 00 → contrast min. , 3F → max. , brightness 00 → pedestal level low, 7F → high)
(2) Supplement of other control
a. 00: Color
When data are 00, the color becomes off since the chroma output is decreased completely .
b. 01: Tint
Data 00 → Skin color tends to become reddish, 3F → skin color tends to become greenish.
c. 04, 05, 06: Cut off R, G, B
8-bit DAC
d. 07, 08: Driver R, B
7-bit DAC
e. 09: AFT offset adjustment
The DC offset of S-curve of AFT output is corrected.
Data 01 → S-curve falls (DC voltage of center frequency drops).
Data FF → S-curve rises.
It becomes AFT defeat mode when data 00, the voltage of AFT out (pin 30) becomes the value in
accordance with the external resistor.
AFT changes over 8-bit DAC into 2 stages for variable range and improvement of precision for per 1-bit.
Output
Example: In the case of AFT
0A: 00
0C-D7: 0
Overlap approx. 1/8
FF
00
0, 1
Data
FF
1
33
AN5095K
ICs for TV
■ Technical Information (continued)
• Explanation of each block (continued)
7. I2C bus (continued)
5) Contents of I2C bus control (continued)
(2) Supplement of other control (continued)
f. 0A: RF AGC delay point adjustment
The same operation as when bias is applied from outside conventionally.
Data 00 → DC-applied bias drops → delay point rises
Data 3F → DC-applied bias drops → delay point down
g. 0B: Video adjustment
Data 0* → detection output min. 7* → max. to be used for correcting the dispersion of detection
output inside the IC.
h. 0B: Hor. screen image position
Data *0 → screen image goes to the left 7 * → screen image shifts to the right.
i. 0C: VCO control
Fine control for the oscillation frequency of VCO (1/2 frequency of fP) of VIF.
8. Supplementary explanation of SW operation
Data-bit
Concrete contents
00-D7
PAL/NTSC mode SW
(0 → PAL)
(1 → NTSC)
00-D6
PAL, NTSC/SECAM mode SW 1) Demodulation output mode changeover.
(1 → forced SECAM)
The color difference output terminal becomes high
(0 → normal discrimination mode)
impedance at forced SECAM.
01-D7
Ver. auto SW
(0 → auto changeover)
(1 → manual changeover)
1) Vertical frequency discrimination circuit changeover.
Auto changeover: Automatic discrimination mode by
internal counter.
Manual changeover: Forcibly changeover 50 Hz/60
Hz by 02-D7 data.
01-D6
Ver. TRG stop SW
(0 → normal)
(1→ trigger off)
1) Vertical trigger input inhibit SW.
1 → trigger input-off is the mode to protect from the
vertical dancing caused by noise at blue-back .
02-D7
Ver. OSC SW
(0 → 50 Hz)
(1→ 60 Hz)
1) Vertical frequency changeover SW.
Valid only when 01-D7 is 1.
03-D7
SIF, external AV input changeover switch
0B-D7
34
SW contents
1)
2)
3)
4)
BGP width changeover (PAL: Wide)
CW changeover to killer (PAL: 90 deg./270 deg.)
Tint operation changeover (PAL: Tint off)
Ident operation changeover (PAL: With operation)
03-D7
0B-D7
0
0
SIF1 (int.)
Output signal
0
1
SIF2 (int.)
1
0
SIF3 (int.)
1
1
Ext. (video)
Power on time
Int. is set at SIF1
ICs for TV
AN5095K
■ Technical Information (continued)
• Explanation of each block (continued)
8. Supplementary explanation of SW operation (continued)
Data-bit
03-D6
SW contents
Concrete contents
Video input changeover switch
03-D6
Input signal
0
Video1
1
Video2
Power on time
08-D7
Chroma VCO SW
(0 → 4.43 MHz)
(1 → 3.58 MHz)
0A-D7
50 Hz/60 Hz, killer, SECAM det. out switch
0A-D6
0A-D6
0A-D7
0
0
50 Hz/60 Hz out
0
1
Killer out
1
0
SECAM det. out
Mode
Output signal
Power on time
50 Hz/60 Hz out
Killer out
SECAM det. out
H (5 V)
60 Hz
Off (color)
SECAM
L (0 V)
50 Hz
On (B/W)
No SECAM
Output
07-D7
0B-D3
1) Chroma oscillation circuit changeover.
SIF VCO free-running frequency, de-emphasis
Detection output gain changeover switch
07-D7 0B-D3 De-emphasis/gain Oscillation frequency of VCO SIF input terminal
0C-D7
4.5 MHz (power on time)
PAL
5.5 MHz
0
PAL
6.0 MHz
1
PAL
6.5 MHz
1
0
NTSC
1
1
0
0
AFT offset SW
(0 → without offset)
(1 → with offset)
1) For AFT 2-stage changeover.
(Power on preset: AFT offset SW → 1)
2) AFT defeat.
Defeat comes ettective only when 0C-D7 = 0,
DAC(09) = 00.
35
AN5095K
ICs for TV
■ Application Circuit Example
100 µF
AN78M09
VCC3=5 V
2 1
1.8 kΩ
5
60
U-COM
7
58
10
55
11
54
220 pF
12
53
10 µF 820 Ω
52
14
51
47
19
46
R
G
C in
B
29
37
30
36
AGC
0.01 µF
0.01 µF
SIF2 in
34
Ext.audio in
33
SIF3 in
sharpness
10 µF
470 Ω
32
0.01 µF
BPF
4.5 MHz
35
470 Ω
5.1 kΩ
10 kBΩ
Sharpness
Ext.video
10 µF
0.47 µF
680 kΩ
470 Ω
75 Ω
Int.
V1
SIF1 in
31
10 µF
Decoupling
1000 pF
470 Ω
38
BPF
470 Ω 6.5 MHz
28
BPF
5.5
MHz
/6.0
MHz
39
470 Ω
27
6.0 µH
Int. V2130 kΩ
Trap
5.5 µH
Audio out
10 µF
1200 pF
De-emphasis
910 Ω 910 Ω
680 kΩ
12 H
RF AGC
39 kΩ
6.8 kΩ
910 Ω
1200 pF Det. out
910 Ω
40
6.5 µH
26
APC1
9V
41
VOSC
0.47 µF 150 Ω
10 µF
25
9V
42
1 kΩ 2.2 kΩ
2 V[p-p]
24
10 µF
Video out
150 kΩ 150 kΩ AFT
10 kBΩ
TU1
36
23
43
10 kΩ
2 kΩ
Y in
SIF
APC
0.01 µF
+B (12 V)
10µF
0.39
µH
0.01 µF
GND
(VIF/SIF)
2 1
10µF
VCC3
(VIF/SIF)
SAW
910 Ω
3 Band SW
2
4 SW1
1
10µF
44
SCL
0.01 µF
8.2 µH
10µF
1F BM AFT BL AGC BH BT BU
10µF
22
270 Ω
2.7 µH 150 pF
1 V[p-p]
4.7 kΩ
1.2 µH
0.01 µF
10µF
45
Sync. in
4 3 2 1
0.01 µF
47µF
21
SDA
7.5 kΩ
1 kΩ
ACL
4.7 kΩ
47 µF
56 Ω
0.1 µF
1200 pF
20
4.7 µF
1000 pF
47 µF
VCC3
5V
1 MΩ
GND (RGB/DAC)
(VCJ)
Hor. lock det.
10 kΩ 3.6 kΩ
0.022 µF
10 kΩ
3.58/4.43
On
48
18
56 µH 30 pF
2 1
17
FBP in
(VCJ)
GND
10 kΩ 10 kΩ
3.58 MHz
Trap
1.5 kΩ
1.8 kΩ
120 pF
49
180 Ω
100 pF
4.7 µH
16
47 µF
3.3 kΩ
1.2 kΩ
50
1 kΩ
AFC1
0.033 µF
AFC2
0.022 µF
15
33 pF
47 pF
13
8.2 µH
680 kΩ
10 kΩ
10 kBΩ
56
1.8 kΩ
1 2 3 4 5
1.5 kΩ
1
Trap&DL
(340 nsec ±35 nsec)
9V
1.5 kΩ
(8 V)
10 kΩ
9
G
47 µF B
1
2.2 kΩ
57
VCC2
VCC1 (9 V)
0.47 µF
16
0.022 µF
V-out
220 Ω 2.2 µF
8
R
0.47 µF
3
2
X-ray protect.
HOSC
0.47 µF
2
47 µF
SECAM interface
YS
1 MΩ
15
1 2 3
180
kΩ
59
4
H-out
1 2 3 4 5 6 7
15 pF B L
4.7 µF
det.
6
3
0.1 µF
Ver.
clamp
2.2 µF
APC
0.047 µF
4.43
MHz
12 pF 3.58
MHz
15 kΩ 15 kΩ
16
4
14
5V
33 kΩ
14
0.01
µF 15
13
0.1 µF
5
5 4 3 2 1
61
13
0.047 µF
0.22 µF
51 Ω
4
5
Video Video
out
in
0.47 µF
0.01 µF
12
6
12
820 Ω
6
7
11
0.1 µF
62
7 0.047 µF
MN3868(1H DL)
3
0.1 µF
−(R−Y) −(B−Y)
out
out
0.022 µF
10
11
0.1 µF
SCP
G
B
Clamp filter
63
8
−(R−Y) −(B−Y)
R
Killer out
50 Hz/60 Hz out
SECAM det. out
2
0.47 µF
0.1 µF
64
0.022 µF
1 MΩ
Killer
1
In
VCC1 = 9 V
AN78M05
47 µF
0.022 µF
0.01 µF
9
8
SECAM
0.1 µF
82 µH 82 µH
33
pF
33
pF
47 µF
9
10