Application Note 1641 ISL28134SOICEVAL1Z Evaluation Board User’s Guide Introduction Power Supplies (Figure 1) The ISL28134SOICEVAL1Z Evaluation Board is designed to evaluate the performance of the ISL28134 Low Noise Chopper Stabilized op amp. The evaluation board contains the circuitry needed to evaluate the high performance of the ISL28134 amplifier. The ISL28134 chopper stabilized rail-to-rail input/output amplifier features a low 2.5µV maximum VOS and 15nV/°C drift over-temperature. The amplifier has no 1/f noise corner down to 0.1Hz with a 1kHz voltage noise density of 10nV/√Hz. The high open loop gain of 174dB allows a high gain single-stage DC amplifier that can operate from a 3V single cell battery while consuming 700µA of current. The ISL28134SOICEVAL1Z evaluation board can be configured as a precision high-gain (G = 1,000V/V) differential amplifier to demonstrate the level of performance possible with this amplifier. External power connections are made through the V+, V-, and GND connections on the evaluation board. The circuit can operate from a single supply or from dual supplies. For single supply operation, the V- and GND pins are tied together to the negative or ground reference of the power supply. For split supplies, V+ and V- terminals connect to their respective supply terminals. The evaluation board power supply range is from +2.25V to +5.5V or ±1.125V to ±2.75V. De-coupling capacitors C2 and C4 provide low-frequency power-supply filtering, while additional capacitors, C1 and C5, which are connected close to the part, filter out high frequency noise. Anti-reverse diodes D1 and D2 protect the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. J8 J7 3 2 C4 4.7µF D1 4.7µF D2 1 S1AB 2 1 1 1 1 DNP • Singled-Ended or Differential Input Operation with High Gain (G = 1,000V/V) C2 R16 R4 • Dual Supply Operation: ±1.125V to ±3.0V DNP • Single Supply Operation: +2.25V to +6.0V 1 1 Evaluation Board Key Features 2 1 2 VREF J11 3 J9 • ISL28134 Data Sheet V+ J10 V- J13 Reference Documents S1AB • Banana Jack Connectors for Power Supply Inputs FIGURE 1. POWER SUPPLY CIRCUIT • BNC Connectors for Op Amp Input and Output Terminals • Convenient PCB pads for changing gain configurations, filtering and impedance loading. • External VREF Input R11 100kΩ R9 IN- V+ IN- 2 100Ω R12 IN+ 7 6 ISL28134 IN+ 100Ω 3 OUT R18 + V- R13 100kΩ 0Ω 4 R17 OPEN C6 OPEN FIGURE 2. BASIC DIFFERENTIAL AMPLIFIER CONFIGURATION June 1, 2011 AN1641.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1641 Amplifier Configuration (Figure 3) The schematic of the op amp input stage with the components supplied is shown in Figure 3, with a closed loop gain of 1,000V/V. The differential amplifier implements a high impedance differential input. The amplifier gain equation is expressed in Equation 1 as: V OUT = ( V IN+ – V IN- ) • ( R11 ⁄ R9 ) (EQ. 1) For single-ended inputs the amplifier can be configured as an inverting gain G = -1,000V/V by grounding the IN+ input, or as a non-inverting amplifier with G = +1,001V/V by grounding the INinput. The non-inverting gain is strongly dependent on any resistance from IN- to GND. For good gain accuracy, a 0Ω resistor should be installed on the empty R1 pad. User-Selectable Options (Figures 3 and 4) Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, outputs and the amplifier feedback loops. The inverting and non-inverting inputs have additional resistor placements for adding input attenuation or to establish input DC offset through the VREF pin. To add a reference input without R9 0 1 VOUT 2 100k OP AMP OUTPUT OUTPUT R18 1 R7 DNP 1 100 R12 2 100 2 IN+ 1 DNP J12 5 100k R2 R13 4 3 1 2 C6 IN + J2 5 0 IN- 1 2 3 4 2 The high performance of the ISL28134 allow it to be configured as a very high gain amplifier with excellent DC and noise performance. The low offset voltage and low noise combined with a high gain is ideal for amplifying very small precision signals accurately for sensor applications. The eval board has been specifically configured for a gain of 1,000V/V to highlight these features of the ISL28134. DNP R5 High Gain Low Noise Amplifier 1 4 3 1 R1 2 1 2 NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. OPEN 1 R17 2 - OPEN R11 DNP IN The op-amp output (Figure 4) also has additional resistor and capacitor placements for filtering and loading. 1 2 J1 5 scaling it by the gain of the amplifier to the output, the circuit needs to be modified slightly. R13 and R15 form a voltage divider to the amplifier IN+ terminal and is chosen to give the inverse of the feedback gain. In this configuration, R13 = R9 and R15 = R11 to scale the reference input by 1,000 while the feedback gain of the amplifier drives the input DC offset to the output in a 1:1 ratio. The non-inverting input signal will need to be AC-coupled into the amplifier. FIGURE 3. INPUT STAGE FIGURE 4. OUTPUT STAGE TABLE 1. ISL28233SOICEVAL1Z COMPONENTS PARTS LIST DEVICE # DESCRIPTION U1 R11 C3 R9, R12 COMMENTS ISL28134IBZ SOIC 8 Ld Package 100kΩ, 603, 0.125W, SMD Resistor Feedback Gain DNP 603 SMD Capacitor Feedback Filtering 100Ω, 603, 0.125W SMD Capacitor Gain Set Resistors R17 DNP, 603, SMD Resistor Output Loading C6 DNP 603 SMD Capacitor Output Filtering R1, R2, R3, R4, R6, R7, R8, R10, R14, R15, R16, R19, R20 DNP 603 SMD Resistor C1, C2, C4, C5 Power Supply Decoupling D1, D2 C1 = C5 = 0.01µF; C2 = C4 = 4.7µF Reverse Polarity Protection Diode 2 AN1641.0 June 1, 2011 Application Note 1641 ISL28134SOICEVAL1Z Top View Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1641.0 June 1, 2011 ISL28134SOICEVAL1Z Schematic Diagram J8 J7 4.7µF D1 1 2 S1AB 1 1 1 J6 OPEN R11 DNP 1 2 R19 0.01µF C1 R13 100k 21 R15 DNP 5 VREF 2 R18 6 0 5 1 2 J12 5 3 4 4 7 DNP SOIC8 7 GENERIC PACK. 6 8 1 3 4 DNP 1 2 3 8 OPEN R17 2 1 100 2 U1 C6 R2 1 2 1 R12 1 0.01µF DNP C5 DNP R20 1 R7 DNP R3 2 DNP 4 3 IN + 1 2 C3 100k 100 DNP J2 5 2 R14 DNP R9 2 2 1 2 4 3 0 R10 DNP 2 1 R5 2 1 DNP 2 1 R1 J5 J4 J3 R6 1 2 J1 5 2 2 2 2 R8 OUT 1 1 1 1 1 1 S1AB Application Note 1641 NODE IN+ 4.7µF D2 DNP C4 R16 R4 DNP 4 2 1 1 1 1 2 C2 IN - VREF J11 3 2 IN- J10 J9 3 V+ J13 V- OUTPUT AN1641.0 June 1, 2011