Single Micropower, Chopper Stabilized, RRIO Operational Amplifier ISL28133 Features The ISL28133 is a single micropower, chopper stabilized operational amplifier that is optimized for single supply operation from 1.8V to 5.5V. Its low supply current of 18µA and wide input range enable the ISL28133 to be an excellent general purpose op amp for a range of applications. The ISL28133 is ideal for handheld devices that operates off 2 AA or single Li-ion batteries. • Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . 8µV, Max. The ISL28133 is available in the 5 Ld SOT-23, the 5 Ld SC70 and the 6 Ld 1.6mmx1.6mm µTDFN packages. All devices operates over the extended temperature range of -40°C to +125°C. • Low Offset TC . . . . . . . . . . . . . . . . . . . . . . . . 0.075µV/°C, Max • Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . 300pA, Max. • Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . . . . .18µA, Typ. • Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V • Low Noise (0.01Hz to 10Hz) . . . . . . . . . . . . . . . . . 1.1µVP-P, Typ. • Rail-to-Rail Inputs and Output • Operating Temperature Range. . . . . . . . . . .-40°C to +125°C Related Literature Applications • AN1480 “ISL28133ISENS-EV1Z Evaluation Board Users Guide” • Bidirectional Current Sense • AN1499 “ISL28133EVAL1Z High Gain Evaluation Board User’s Guide” • Medical Equipment • Temperature Measurement • Electronic Weigh Scales VS 1.8V TO +5.5V I-SENSE+ 10 0.1 4.99k 499k 5 + V+ 1 ISL28133 V4 2 499k MAX 6 3 VSENSE OUT VOS (µV) 4.99k N = 67 8 VREF 4 2 MEDIAN 0 -2 -4 GND I-SENSEBIDIRECTIONAL CURRENT SENSE AMPLIFIER FIGURE 1. TYPICAL APPLICATION CIRCUIT July 22, 2011 FN6560.5 1 -6 MIN -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 2. VOS vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28133 Block Diagram V+ MAIN AMPLIFIER + - IN+ 5kHz CROSSOVER FILTER VOUT + IN- CLOCK GEN + DRIVERS V- Ordering Information PART NUMBER PACKAGE Tape & Reel (Pb-Free) PART MARKING PKG. DWG. # ISL28133FHZ-T7 (Notes 1, 2) BCFA 5 Ld SOT-23 P5.064A ISL28133FHZ-T7A (Notes 1, 2) BCFA 5 Ld SOT-23 P5.064A ISL28133FEZ-T7 (Notes 1, 2) BHA 5 Ld SC70 P5.049 ISL28133FRUZ-T7 (Notes 1, 3) T8 6 Ld µTDFN L6.1.6x1.6 ISL28133ISENS-EV1Z Evaluation Board ISL28133EVAL1Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL28133. For more information on MSL please see techbrief TB363. 2 FN6560.5 July 22, 2011 ISL28133 Pin Configuration ISL28133 (5 LD SC-70) TOP VIEW 1 V- 2 IN+ 3 5 V+ + 4 IN- IN+ 1 V- 2 IN- 3 5 V+ + OUT - ISL28133 (5 LD SOT-23) TOP VIEW 4 OUT ISL28133 (6 LD µTDFN) TOP VIEW OUT 1 V- 2 6 V+ - + 5 NC IN - 3 4 IN + FUNCTION Pin Descriptions ISL28133 (5 Ld SOT23) ISL28133 (5 Ld SC70) ISL28133 (6 Ld µTDFN) PIN NAME 3 1 4 IN+ EQUIVALENT CIRCUIT Non-inverting input V+ + - IN+ + IN- CLOCK GEN + DRIVERS VCircuit 1 2 2 2 V- Negative supply 4 3 3 IN- Inverting input 1 4 1 OUT Output (See Circuit 1) V+ OUT VCircuit 2 5 5 3 6 V+ Positive supply 5 NC Not Connected – This pin is not electrically connected internally. FN6560.5 July 22, 2011 ISL28133 Absolute Maximum Ratings Thermal Information Max Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V Max Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 (Note 5, 6) . . . . . . . . . . . . . . . . 225 110 5 Ld SC70 (Note 5). . . . . . . . . . . . . . . . . . . . 206 N/A 6 Ld µTDFN (Note 5). . . . . . . . . . . . . . . . . . . 240 N/A Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = Open, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN PARAMETER DESCRIPTION CONDITIONS (Note 7) TYP MAX (Note 7) UNIT -8 ±2 8 µV 15.5 µV 0.075 µV/°C DC SPECIFICATIONS VOS Input Offset Voltage -15.5 TCVOS Input Offset Voltage Temperature Coefficient 0.02 IOS Input Offset Current -60 IB Input Bias Current Common Mode Input Voltage Range CMRR Common Mode Rejection Ratio -300 ±30 pA 300 pA -600 600 pA V+ = 5.0V, V- = GND -0.1 5.1 V VCM = -0.1V to 5.0V 118 125 dB 115 PSRR Power Supply Rejection Ratio Vs = 2V to 5.5V 110 dB 138 dB 110 dB VOH Output Voltage Swing, High RL = 10kΩ VOL Output Voltage Swing, Low RL = 10kΩ 18 AOL Open Loop Gain RL = 1MΩ 174 V+ Supply Voltage (Note 8) IS Supply Current RL = OPEN ISC+ Output Source Short Circuit Current ISC- Output Sink Short Circuit Current RL = Short to ground or V+ 4.965 4.981 1.8 18 V 35 mV dB 5.5 V 25 µA 35 µA 13 17 26 mA -26 -19 -13 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product f = 50kHz 4 AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM 400 kHz FN6560.5 July 22, 2011 ISL28133 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = Open, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN PARAMETER DESCRIPTION (Note 7) CONDITIONS MAX (Note 7) TYP UNIT eN VP-P Peak-to-Peak Input Noise Voltage f = 0.01Hz to 10Hz 1.1 µVP-P eN Input Noise Voltage Density f = 1kHz 65 nV/√(Hz) iN Input Noise Current Density f = 1kHz 72 fA/√(Hz) f = 10Hz 79 fA/√(Hz) f = 1MHz 1.6 pF 1.12 pF 0.2 V/µs 0.1 V/µs 1.1 µs 1.1 µs Cin Differential Input Capacitance Common Mode Input Capacitance TRANSIENT RESPONSE SR Positive Slew Rate VOUT = 1V to 4V, RL = 10kΩ Negative Slew Rate tr, tf, Small Signal AV = +1, VOUT = 0.1VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% tr, tf Large Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% ts Settling Time to 0.1%, 2VP-P Step AV = +1, VOUT = 2VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF 8 µs 10 µs AV = +1, RF = 0Ω, RL = 10kΩ, 35 µs CL = 1.2pF NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. Parts are 100% tested with a minimum operating voltage of 1.8V to a VOS limit of ±15µV. Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. 8 3.5 N = 67 +25°C -40°C 4 N = 67 MEDIAN 2 2.5 VOS (µV) AVERAGE VOS (µV) 3.0 2.0 1.5 0 MIN -2 -4 -6 1.0 0.5 MAX 6 -8 125°C 2.0 2.5 3.0 3.5 4.0 4.5 -10 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 3. AVERAGE INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE 5 -12 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 4. VOS vs TEMPERATURE, VS = ±1.0V, VIN = 0V, RL = INF FN6560.5 July 22, 2011 ISL28133 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 10 IBIAS IN+(pA) VOS (µV) 4 2 N = 12 150 MAX 6 MEDIAN 0 -2 +125°C 100 50 +100°C +75°C 0 -4 -6 200 N = 67 8 -40°C -40°C MIN -40 -20 0 20 40 60 80 100 -50 1.5 120 2.0 +25°C 2.5 TEMPERATURE (°C) FIGURE 5. VOS vs TEMPERATURE, VS = ±2.5V, VIN = 0V, RL = INF 4.5 5.0 5.5 +125°C 150 100 +100°C +75°C 50 +25°C -40°C 0 -50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -10 -20 N = 67 +25°C 0 AVERAGE IOS (pA) IBIAS IN- (pA) 4.0 10 N = 12 200 -40°C -30 -40 +125°C -50 -60 -70 5.0 -80 1.5 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 7. IB- vs SUPPLY VOLTAGE vs TEMPERATURE FIGURE 8. IOS vs SUPPLY VOLTAGE vs TEMPERATURE 28 25 N = 67 24 +125°C 23 22 21 20 +25°C 19 18 -40°C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 9. AVERAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 6 N = 67 26 MAX 24 22 MEDIAN 20 MIN 18 16 17 2.0 SUPPLY CURRENT (µA) AVERAGE SUPPLY CURRENT (µA) 3.5 FIGURE 6. IB+ vs SUPPLY VOLTAGE vs TEMPERATURE 250 16 3.0 SUPPLY VOLTAGE (V) 14 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 10. MIN/MAX SUPPLY CURRENT vs TEMPERATURE, VS = ±0.8V, VIN = 0V, RL = INF FN6560.5 July 22, 2011 ISL28133 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 800 28 INPUT NOISE VOLTAGE (nV) SUPPLY CURRENT (µA) 30 N = 67 MAX 26 24 MEDIAN 22 20 MIN 18 16 14 -40 -20 0 20 40 60 80 100 600 400 200 0 -200 -400 -600 120 0 V+ = 5V RL = 100k CL = 3.7pF Rg = 10, Rf = 100k AV = 10,000 10 20 30 40 50 TEMPERATURE (°C) INPUT NOISE CURRENT (pA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 1000 V+ = 5V AV = 1 100 0.1 1 10 100 1k 10k 100k 100 V+ = 5V AV = 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1k 10k 100k 150 PHASE 100 50 GAIN RL = 10k CL = 100pF SIMULATION -100 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 15. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10k FIGURE 14. INPUT NOISE CURRENT DENSITY vs FREQUENCY OPEN LOOP GAIN (dB)/PHASE (°) OPEN LOOP GAIN (dB)/PHASE (°) 200 7 90 FREQUENCY (Hz) FIGURE 13. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY -50 80 1.0 FREQUENCY (Hz) 0 70 FIGURE 12. INPUT NOISE VOLTAGE 0.01Hz TO 10Hz FIGURE 11. MIN/MAX SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V, VIN = 0V, RL = INF 10 0.001 0.01 60 TIME (s) 200 150 PHASE 100 50 GAIN 0 -50 RL = 10M CL = 100pF SIMULATION -100 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 16. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10M FN6560.5 July 22, 2011 ISL28133 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 2 RL = 100k RL = OPEN 1 0 RL = 1k -1 RL = 10k -2 RL = 49.9k -3 -4 V+ = 1.6V -5 CL = 3.7pF AV = +1 VOUT = 10mVP-P -6 -7 -8 100 1k 10k 100k 1M NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 1 RL = OPEN 0 RL = 1k -1 RL = 49.9k -3 -4 -5 -6 -7 V+ = 5V CL = 3.7pF AV = +1 VOUT = 10mVP-P -8 100 10M RL = 100k RL = 10k -2 1k 10k FIGURE 17. GAIN vs FREQUENCY vs R L, VS = 1.6V 6 Rf = Rg = 10k 5 1 V+ = 5V RL = 100k CL = 3.7pF AV = +2 VOUT = 10mVP-P 0 100 1k 10k 100k FREQUENCY (Hz) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 7 Rf = Rg = 1k Rf = Rg = 100k 8 2 1M GAIN (dB) Rg = 1k, Rf = 100k AV = 100 V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P AV = 10 Rg = 10k, Rf = 100k 10 AV = 1 -10 10 VOUT = 1V -3 VOUT = 500mV -4 VOUT = 250mV -5 -6 V+ = 5V RL = OPEN -7 CL = 3.7pF -8 AV = +1 -9 1k 100 VOUT = 100mV 10k 100k 1M 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 21. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 8 0 -1 -2 V+ = 1.2V -3 V+ = 1.6V -4 V+ = 3.0V V+ = 5.5V -5 -6 -7 -8 Rg = OPEN, Rf = 0 100 NORMALIZED GAIN (dB) Rg = 100, Rf = 100k 30 0 -2 1 AV = 1000 50 20 VOUT = 10mV FIGURE 20. GAIN vs FREQUENCY vs VOUT, RL = OPEN 70 40 0 -1 FREQUENCY (Hz) FIGURE 19. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg 60 10M 1 9 3 1M FIGURE 18. GAIN vs FREQUENCY vs RL, VS = 5V 10 4 100k FREQUENCY (Hz) FREQUENCY (Hz) RL = 100k CL = 3.7pF AV = +1 VOUT = 10mVP-P -9 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 22. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FN6560.5 July 22, 2011 ISL28133 Typical Performance Curves 10 CL = 824pF CL = 474pF CL = 224pF 6 4 0 -10 -20 2 CMRR (dB) NORMALIZED GAIN (dB) 8 V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 0 -2 -4 V+ = 5V CL = 104pF -6 RL = 100k CL = 51pF AV = +1 -8 V OUT = 10mVP-P CL = 3.7pF -10 100 1k -30 -40 -50 -70 -80 -90 10k 100k FREQUENCY (Hz) 1M -100 10 10M 100 1k 100k 10M 1M FIGURE 24. CMRR vs FREQUENCY, VS = 5V 10 0 0 -20 -10 -30 -20 -40 -50 PSRR+ -60 V+ = 5V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P -80 -90 PSRR- -100 10 100 1k 10k 100k 1M CMRR (dB) -10 -70 -30 -40 -50 V+ =1.6V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P -60 -70 -80 -90 -100 10 10M 100 1k 10k 100k 10M 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 25. PSRR vs FREQUENCY, VS = 5V FIGURE 26. CMRR vs FREQUENCY, VS = 1.6V 200 0 N = 67 -10 180 -20 MAX -30 -40 -50 PSRR+ -60 V+ = 1.6V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P -70 -80 PSRR- -90 -100 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 27. PSRR vs FREQUENCY, VS = 1.6V 9 10M CMRR (dB) PSRR (dB) 10k FREQUENCY (Hz) FIGURE 23. GAIN vs FREQUENCY vs C L PSRR (dB) V+ = 5V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P -60 160 MEDIAN 140 120 MIN 100 80 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 28. CMRR vs TEMPERATURE, VCM = -2.5V TO +2.5V, V+ = ±2.5V FN6560.5 July 22, 2011 ISL28133 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 155 4.5 MAX 125 LARGE SIGNAL (V) 135 PSRR (dB) 5.0 N = 67 145 MEDIAN 115 105 MIN 95 85 4.0 3.5 3.0 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P 2.5 2.0 1.5 1.0 0.5 75 -40 -20 0 20 40 60 80 100 0 120 0 50 100 TEMPERATURE (°C) 1.0 0.12 SMALL SIGNAL (V) LARGE SIGNAL (V) 0.14 0.8 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 1VP-P 0.2 0 10 20 30 40 50 60 70 80 0.06 0 5 10 15 20 25 30 35 40 TIME (µs) FIGURE 32. SMALL SIGNAL STEP RESPONSE (100mV) 0.024 4.986 N = 67 0.022 4.980 MEDIAN 4.978 MIN VOUT (V) MAX 0.020 4.974 0.017 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 33. VOUT HIGH vs TEMPERATURE, RL = 10k, VS +-2.5V MEDIAN 0.019 0.018 0 MAX 0.021 4.976 -20 N = 67 0.023 4.982 VOUT (V) 400 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 100mVP-P 0.04 0 90 100 FIGURE 31. LARGE SIGNAL STEP RESPONSE (1V) 4.972 -40 350 0.08 TIME (µs) 4.984 300 0.10 0.02 0 250 FIGURE 30. LARGE SIGNAL STEP RESPONSE (4V) 1.2 0.4 200 TIME (µs) FIGURE 29. PSRR vs TEMPERATURE, V+ = 2V TO 5.5V 0.6 150 0.016 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 34. VOUT LOW vs TEMPERATURE, RL = 10k, VS +-2.5V n 10 FN6560.5 July 22, 2011 ISL28133 Applications Information Layout Guidelines for High Impedance Inputs Functional Description The ISL28133 uses a proprietary chopper-stabilized architecture shown in the “Block Diagram” on page 2. The ISL28133 combines a 400kHz main amplifier with a very high open loop gain (174dB) chopper stabilized amplifier to achieve very low offset voltage and drift (2µV, 0.02µV/°C typical) while consuming only 18µA of supply current per channel. This multi-path amplifier architecture contains a time continuous main amplifier whose input DC offset is corrected by a parallel-connected, high gain chopper stabilized DC correction amplifier operating at 100kHz. From DC to ~5kHz, both amplifiers are active with DC offset correction and most of the low frequency gain is provided by the chopper amplifier. A 5kHz crossover filter cuts off the low frequency amplifier path leaving the main amplifier active out to the 400kHz gain-bandwidth product of the device. To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28133 amplifiers, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. High Gain, Precision DC-Coupled Amplifier Rail-to-rail Input and Output (RRIO) The circuit in Figure 36 implements a single-stage, 10kV/V DC-coupled amplifier with an input DC sensitivity of under 100nV that is only possible using a low VOS amplifier with high open loop gain. This circuit is practical down to 1.8V due to it's rail-to-rail input and output capability. Standard high gain DC amplifiers operating from low voltage supplies are not practical at these high gains using typical low offset precision op amps because the input offset voltage and temperature coefficient consume most of the available output voltage swing. For example, a typical precision amplifier in a gain of 10kV/V with a ±100µV VOS and a temperature coefficient of 0.5µV/°C would produce a DC error at the output of >1V with an additional 5mV°C of temperature dependent error. At 3V, this DC error consumes > 30% of the total supply voltage, making it impractical to measure sub-microvolt low frequency signals. The RRIO CMOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing 100mV beyond either supply rail. The inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew-rate input signals. The ±8µV max VOS and 0.075µV/°C of the ISL28133 produces a temperature stable maximum DC output error of only ±80mV with a maximum temperature drift of 0.75mV/°C. The additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables DC voltages and voltage fluctuations well below 100nV to be easily detected with a simple single stage amplifier. The key benefits of this architecture for precision applications are very high open loop gain, very low DC offset, and low 1/f noise. The noise is virtually flat across the frequency range from a few mHz out to 100kHz, except for the narrow noise peak at the amplifier crossover frequency (5kHz). The output stage uses common source connected PMOS and NMOS devices to achieve rail-to-rail output drive capability with 17mA current limit and the capability to swing to within 20mV of either rail while driving a 10kΩ load. CF 0.018µF 1MΩ, IN+ and IN- Protection +2.5V All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications where either input is expected to exceed the rails by 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (see Figure 35). VIN 100Ω 1MΩ VOUT RL + 100Ω -2.5V ACL = 10kV/V FIGURE 36. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER VIN RIN VOUT RL + FIGURE 35. INPUT CURRENT LIMITING 11 FN6560.5 July 22, 2011 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 VOS (µV) VOS (µV) ISL28133 0.0 -0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 30 60 90 120 180 240 300 360 420 480 540 600 TIME (DAYS) -1.0 0 30 60 90 120 180 240 300 360 420 480 540 600 TIME (DAYS) FIGURE 37. LONG TERM DRIFT (VOS vs TIME) FOR 30 UNITS FIGURE 38. LONG TERM DRIFT (VOS vs TIME) FOR A SINGLE UNIT Long Term VOS Drift ISL28133 SPICE Model Figure 37 shows a plot of daily VOS drift measurements of 30 individual ISL28133 amplifiers over a continuous 572 day period at +25°C. The 30 units were connected in a gain of 10k, mounted on a single PC board and kept at room temp. The 30 amplifier outputs were measured daily by a DVM and scanner under computer control. The daily VOS measurements were subtracted from the initial VOS value to calculate the VOS shift. The test board was powered from a UPS to maintain uninterrupted power to the test units. Three instances of lost measurement data ranging from 2 days to 2 weeks due to power loss to the measurement scanner were detected, and data were interpolated. Figure 40 shows the SPICE model schematic and Figure 41 shows the net list for the ISL28133 SPICE model. The model is a simplified version of the actual device and simulates important parameters such as noise, Slew Rate, Gain and Phase. The model uses typical parameters from the ISL28133. The poles and zeros in the model were determined from the actual open and closed-loop gain and phase response. This enables the model to present an accurate AC representation of the actual device. The model is configured for ambient temperature of +25°C. The change in amplifier VOS over the 572 day period for all 30 amplifiers (see Figure 38) was less than ±100nV, and no clear VOS long term drift trend was evident in the data. The excellent long term drift performance is a result of the chopper amplifier’s ability to measure and correct VOS errors, leaving only the VOS error contribution due to changes in the long term stability of the external components (see Figure 39). Figures 42 through 49 show the characterization vs simulation results for the Noise Density, Frequency Response vs Close Loop Gain, Gain vs Frequency vs CL and Large Signal Step Response (4V). 100kΩ +2.5V 10Ω 10Ω 100kΩ VOUT + 1kΩ -2.5V ACL = 10kV/V FIGURE 39. LONG TERM DRIFT TEST CIRCUIT 12 FN6560.5 July 22, 2011 ISL28133 V16 V15 Dn2 7 Dn1 I2 R22 I1 R21 R1 R2 + - + - Vin+ M1 En M2 Cin1 Cin2 13 Vin- 12 R3 R4 4 Input Stage Voltage Noise 7 7 + + D2 R6 - R8 - G2 D4 C1 G4 V4 V6 13 VV3 12 16 - V3 G1 - R5 D1 + V5 G3 R7 C2 + D3 4 4 SR Limit & First Pole Gain Stage 7 + - R12 L1 + G8 G5 D7 R14 + D8 G10 C3 V+ R16 R11 VV3 Vout 16 R10 E1 + + - G7 - G5 + 4 R9 L2 R13 + C4 G9 + - D6 D5 G10 + - G11 + R15 VZero/Pole Pole Output Stage FIGURE 40. SPICE CIRCUIT SCHEMATIC 13 FN6560.5 July 22, 2011 ISL28133 * ISL28133 Macromodel * Revision B, April 2009 * AC characteristics, Voltage Noise * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28133 3 2 7 4 6 * *Voltage Noise D_DN1 102 101 DN D_DN2 104 103 DN R_R21 0 101 120k R_R22 0 103 120k E_EN 8 3 101 103 1 V_V15 102 0 0.1Vdc V_V16 104 0 0.1Vdc * *Input Stage C_Cin1 8 0 0.4p C_Cin2 2 0 2.0p R_R1 9 10 10 R_R2 10 11 10 R_R3 4 12 100 R_R4 4 13 100 M_M1 12 8 9 9 pmosisil + L=50u + W=50u M_M2 13 2 11 11 pmosisil + L=50u + W=50u I_I1 4 7 DC 92uA I_I2 7 10 DC 100uA * *Gain stage G_G1 4 VV2 13 12 0.0002 G_G2 7 VV2 13 12 0.0002 R_R5 4 VV2 1.3Meg R_R6 VV2 7 1.3Meg D_D1 4 14 DX D_D2 15 7 DX V_V3 VV2 14 0.7Vdc V_V4 15 VV2 0.7Vdc * *SR limit first pole G_G3 4 VV3 VV2 16 1 G_G4 7 VV3 VV2 16 1 R_R7 4 VV3 1meg R_R8 VV3 7 1meg C_C1 VV3 7 12u C_C2 4 VV3 12u D_D3 4 17 DX D_D4 18 7 DX V_V5 VV3 17 0.7Vdc V_V6 18 VV3 0.7Vdc * *Zero/Pole E_E1 16 4 7 4 0.5 G_G5 4 VV4 VV3 16 0.000001 G_G6 7 VV4 VV3 16 0.000001 L_L1 20 7 0.3H R_R12 20 7 2.5meg R_R11 VV4 20 1meg L_L2 4 19 0.3H R_R9 4 19 2.5meg R_R10 19 VV4 1meg *Pole G_G7 4 VV5 VV4 16 0.000001 G_G8 7 VV5 VV4 16 0.000001 C_C3 VV5 7 0.12p C_C4 4 VV5 0.12p R_R13 4 VV5 1meg R_R14 VV5 7 1meg * *Output Stage G_G9 21 4 6 VV5 0.0000125 G_G10 22 4 VV5 6 0.0000125 D_D5 4 21 DY D_D6 4 22 DY D_D7 7 21 DX D_D8 7 22 DX R_R15 4 6 8k R_R16 6 7 8k G_G11 6 4 VV5 4 -0.000125 G_G12 7 6 7 VV5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model DN D(KF=6.4E-16 AF=1) .MODEL DX D(IS=1E-18 Rs=1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28133 FIGURE 41. SPICE NET LIST 14 FN6560.5 July 22, 2011 ISL28133 1000 V+ = 5V AV = 1 100 10 0.001 0.01 0.1 1 10 100 1k 10k 100k INPUT NOISE VOLTAGE (nV/√Hz INPUT NOISE VOLTAGE (nV/√Hz Characterization vs Simulation Results 1000 V+ = 5V AV = 1 100 10 0.1 1 FREQUENCY (Hz) FIGURE 42. CHARACTERIZED INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 70 Rg = 100, Rf = 100k GAIN (dB) 50 40 V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P 30 20 AV = 10 Rg = 10k, Rf = 100k 10 0 50 Rg = 1k, Rf = 100k AV = 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 4 2 0 -2 -4 V+ = 5V CL = 104pF -6 RL = 100k CL = 51pF AV = +1 -8 VOUT = 10mVP-P CL = 3.7pF -10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 46. CHARACTERIZED GAIN vs FREQUENCY vs C L 15 Rg = 100, Rf = 100k Rg = 10k, Rf = 100k AV = 10 20 AV = 1 -10 10 Rg = 10M Rf = 1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 45. SIMULATED FREQUENCY RESPONSE vs CLOSED LOOP GAIN NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 30 8 CL = 824pF CL = 474pF CL = 224pF 6 100k Rg = 1k, Rf = 100k 0 FIGURE 44. CHARACTERIZED FREQUENCY RESPONSE vs CLOSED LOOP GAIN 8 10k AV = 100 10 Rg = OPEN, Rf = 0 100 1k 40 AV = 1 -10 10 AV = 1000 60 GAIN (dB) 60 100 FIGURE 43. SIMULATED INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 70 AV = 1000 10 FREQUENCY (Hz) CL = 824pF 6 CL = 474pF 4 CL = 224pF 2 0 -2 -4 -6 CL = 3.7pF -8 -10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 47. SIMULATED GAIN vs FREQUENCY vs CL FN6560.5 July 22, 2011 ISL28133 5.0 5.0 4.5 4.5 4.0 4.0 LARGE SIGNAL (V) LARGE SIGNAL (V) Characterization vs Simulation Results (Continued) 3.5 3.0 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P 2.5 2.0 1.5 1.0 0.5 0 VIN 3.5 VOUT 3.0 2.5 2.0 1.5 1.0 0.5 0 50 100 150 200 250 300 350 400 TIME (µs) FIGURE 48. CHARACTERIZED LARGE SIGNAL STEP RESPONSE (4V) 16 0 0 50 100 150 200 250 300 350 400 TIME (µs) FIGURE 49. SIMULATED LARGE SIGNAL STEP RESPONSE (4V) FN6560.5 July 22, 2011 ISL28133 Revision History v The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 5/31/11 FN6560.5 Changed minimum operating supply voltage from +1.65V to +1.8V throughout entire datasheet. Added Tjc information for 5 Ld SOT-23 package in Thermal information on page 5. 2/1/11 FN6560.4 -Converted to Updated Intersil Template. -Page 1 Graphics numbered as Figures 1 and 2. -Updated Ordering Information on page 2 by adding part ISL28133FHZ-T7A. -Changed Note on page 5, which read “Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.” to “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.” -Added two Long Term Drift Curves (Figures 37 and 38) and section “Long Term VOS Drift” on page 12 -Replaced POD MDP0038 (no dimension changes), now obsolete with P5.064A. 5/3/10 FN6560.3 Title Page 1: Replaced “Zero-Drift” with “Chopper Stabilized” for title and part description On page 3: Pin Configuration: MTDFN -> uTDFN On page 7: Figure 12: Changed 0.1Hz to 0.01Hz in Figure caption On page 11: In “Functional Description”; Paragraph 1, 2nd sentence: Changed text from "…open loop gain (200dB)…" -to- "…open loop gain (174dB)…" Changed TYP for “Open Loop Gain” on page 4 from 200dB to 174dB. On page 11: In “High Gain, Precision DC-Coupled Amplifier”; Paragraph 2, 1st sentence: Changed text from "...DC output error of only ±80mV with a maximum temperature drift of 0.75µV/°C." to "… DC output error of only ±80mV with a maximum temperature drift of 0.75mV/C." 2/24/10 CHANGE Removed “Coming Soon” from ISL28133EVAL1Z in the ordering information table on pg 2. 09/24/09 FN6560.2 Converted to new Intersil template. Removed ISL28233 and ISL28433 from data sheet, added Applications, Related Literature, Typical Application Circuit, Performance Curve, updated ordering information by removing “coming soon” on SC70 and uTDFN packages and adding Eval board listed as “coming soon”. Added Block Diagram, Changed in Abs Max Rating Voltage from “5.75V” to “6.5V”. Removed Tjc from Thermal Information until provided by packaging scheduled for 9-11-09. Changed Low Offset “drift” to Low Offset “TC”, added Max Junction Temp 140C, added SPICE model and simulation results, removed supply current graph at +-3V, re-ordered typical performance curves, removed guard ring information from application section. Added Revision History and Products Information 05/29/09 FN6560.1 Page 4: Removed the RL = 100 Curve from Figures 3, 4 and 5. Page 1: Under Features, removed the word "Output" from "Low Output Noise" 03/25/09 FN6560.0 Initial Release to WEB Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28133 To report errors or suggestions for this data sheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6560.5 July 22, 2011 ISL28133 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 α WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 18 FN6560.5 July 22, 2011 ISL28133 Package Outline Drawing L6.1.6x1.6 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL) Rev 1, 11/07 2X 1.00 1.60 A 6 PIN 1 INDEX AREA PIN #1 INDEX AREA 6 B 4X 0.50 1 3 5X 0 . 40 ± 0 . 1 1X 0.5 ±0.1 1.60 (4X) 0.15 4 6 0.10 M C A B TOP VIEW 4 0.25 +0.05 / -0.07 BOTTOM VIEW ( 6X 0 . 25 ) SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX 0.10 C C BASE PLANE (1.4 ) SIDE VIEW ( 5X 0 . 60 ) C SEATING PLANE 0.08 C 0 . 2 REF 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" ( 4X 0 . 5 ) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 19 FN6560.5 July 22, 2011 ISL28133 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 5 (0.60) 0.20 C 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 H 0.15 C A-B 2x C 1.45 MAX 1.14 ±0.15 0.10 C SIDE VIEW SEATING PLANE (0.25) GAUGE PLANE 0.45±0.1 0.05-0.15 4 DETAIL "X" (0.60) (1.20) NOTES: (2.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN 20 FN6560.5 July 22, 2011