ISL28134 Datasheet

DATASHEET
5V Ultra Low Noise, Zero Drift Rail-to-Rail Precision
Op Amp
ISL28134
Features
The ISL28134 is a single, chopper-stabilized zero drift
operational amplifier optimized for single and dual supply
operation from 2.25V to 6.0V and ±1.125V and ±3.0V. The
ISL28134 uses auto-correction circuitry to provide very low input
offset voltage, drift and a reduction of the 1/f noise corner below
0.1Hz. The ISL28134 achieves ultra low offset voltage, offset
temperature drift, wide gain bandwidth and rail-to-rail
input/output swing while minimizing power consumption.
• Rail-to-rail inputs and outputs
- CMRR at VCM = 0.1V beyond VS . . . . . . . . . . . . . 135dB, typ
- VOH and VOL . . . . . . . . . . . . . . . . . . . . . . .10mV from VS, typ
The ISL28134 is ideal for amplifying the sensor signals of analog
front-ends that include pressure, temperature, medical, strain
gauge and inertial sensors down to the µV levels.
The ISL28134 can be used over standard amplifiers with high
stability across the industrial temperature range of -40°C to
+85°C and the full industrial temperature range of -40°C to
+125°C. The ISL28134 is available in an industry standard
pinout SOIC and SOT-23 packages.
Applications
• Medical instrumentation
• No 1/f noise corner down to 0.1Hz
- Input noise voltage . . . . . . . . . . . . . . . . . 10nV/Hz at 1kHz
- 0.1Hz to 10Hz noise voltage . . . . . . . . . . . . . . . . . 250nVP-P
• Low offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5µV, Max
• Superb offset drift . . . . . . . . . . . . . . . . . . . . . . . 15nV/°C, Max
• Single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 6.0V
• Dual supply . . . . . . . . . . . . . . . . . . . . . . . . . ±1.125V to ±3.0V
• Low ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675µA, typ
• Wide bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5MHz
• Operating temperature range
- Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- Full industrial . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
• Packaging
- Single: SOIC, SOT-23
• Sensor gain amps
• Precision low drift, low frequency ADC drivers
• Precision voltage reference buffers
Related Literature
• Thermopile, thermocouple, and other temperature sensors
front-end amplifiers
• AN1641, “ISL28134SOICEVAL1Z Evaluation Board User’s
Guide”
• Inertial sensors
• AN1560, “Making Accurate Voltage Noise and Current Noise
Measurements on Operational Amplifiers Down to 0.1Hz”
• Process control systems
• Weight scales and strain gauge sensors
+5
ISL28134
0Ω
ISL22316
+
ISL26102
50Ω
35
-
24-BIT ADC
50kΩ
0
35
35
0Ω
ISL21010
Ω
DCP
-
50kΩ
50Ω
5V VREF
+
1200
Vs = ±2.5V
VCM = 0V
T = -40°C to +125°C
N = 2796
1000
800
600
400
0
-2.5 -2.0 -1.5 -1.0 -0.5
FIGURE 1. PRECISION WEIGH SCALE / STRAIN GAUGE
1
1400
200
ISL28134
October 14, 2014
FN6957.6
NUMBER OF AMPLIFIERS
1600
0
0.5
1.0
1.5
2.0
2.5
FIGURE 2. VOS HISTOGRAM VS = 5V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL28134
Pin Configurations
ISL28134
(8 LD SOIC)
TOP VIEW
ISL28134
(5 LD SOT-23)
TOP VIEW
OUT
1
V-
2
IN+
3
5
V+
4
IN-
+ -
NC
1
IN-
2
IN+
V-
8
NC
7
V+
3
6
OUT
4
5
NC
- +
Pin Descriptions
ISL28134
(8 Ld SOIC)
ISL28134
(5 Ld SOT-23)
PIN
NAME
FUNCTION
2
4
IN-
Inverting input
3
3
IN+
Non-inverting input
EQUIVALENT CIRCUIT
(See Circuit 1)
V+
+
-
IN+
+
IN-
CLOCK GEN + DRIVERS
VCircuit 1
4
2
V-
6
1
OUT
Negative supply
Output
V+
OUT
VCircuit 2
7
5
V+
Positive supply
1, 5, 8
-
NC
No Connect
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2
Pin is floating. No connection made to IC.
FN6957.6
October 14, 2014
ISL28134
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
ISL28134IBZ (Notes 1, 3)
28134 IBZ
ISL28134FHZ-T7 (Notes 2, 3)
BEEA (Note 5)
ISL28134FHZ-T7A (Notes 2, 3)
BEEA (Note 5)
ISL28134ISENSEV1Z
Evaluation Board
ISL28134SOICEVAL1Z
Evaluation Board
TEMP RANGE
(°C)
-40°C to +85°C
PACKAGE
(Pb-Free)
PKG.
DWG. #
8 Ld SOIC
M8.15E
-40°C to +125°C
5 Ld SOT-23
P5.064A
-40°C to +125°C
5 Ld SOT-23
P5.064A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL28134. For more information on MSL please see techbrief TB363.
5. The part marking is located on the bottom of the part.
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3
FN6957.6
October 14, 2014
ISL28134
Absolute Maximum Ratings
Thermal Information
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Voltage VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . (V- - 0.3V) to (V+ + 0.3V) V
Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V+) or (V-)
dv/dt Supply Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V/µs
ESD Rating
Human Body Model (Tested per JED22-A114F) . . . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JED22-A115B). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JED22-C110D) . . . . . . . . . . . . . . 2kV
Latch-up (Passed Per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
5 Ld SOT-23 (Notes 6, 7) . . . . . . . . . . . . . . .
225
116
8 Ld SOIC (Notes 6, 7) . . . . . . . . . . . . . . . . .
125
77.2
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Ambient Operating Temperature Range
Industrial Grade Package . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Full Industrial Grade Package. . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Voltage Range. . . . . . . . . . . . . . . . . 2.25V (±1.125V) to 6V (±3V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
operating temperature range.
PARAMETER
VS = 5V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply across the specified
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
-2.5
-0.2
2.5
µV
DC SPECIFICATIONS
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Temperature
Coefficient
IB
Input Bias Current
TCIB
IOS
TCIOS
Input Bias Current Temperature
Coefficient
PSRR
VS
-3.4
-
3.4
µV
-4
-
-4
µV
TA = -40°C to +125°C
-15
-0.5
15
nV/°C
-300
±120
300
pA
TA = -40°C to +85°C
-300
-
300
pA
TA = -40°C to +125°C
-550
-
550
pA
TA = -40°C to +85°C
-
±1.4
-
pA/°C
TA = -40°C to +125°C
-
±2
-
pA/°C
-600
±240
600
pA
TA = -40°C to +85°C
-600
-
600
pA
TA = -40°C to +125°C
-750
-
750
pA
-
±2.8
-
pA/°C
TA = -40°C to +125°C
-
±4
-
pA/°C
V+ = 5.0V, V- = 0V
Guaranteed by CMRR
-0.1
-
5.1
V
VCM = -0.1V to 5.1V
120
135
-
dB
VCM = -0.1V to 5.1V
115
-
-
dB
Input Offset Current
Input Offset Current Temperature Coefficient TA = -40°C to +85°C
Common Mode Input
Voltage Range
CMRR
TA = -40°C to +85°C
TA = -40°C to +125°C
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Supply Voltage (V+ to V-)
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4
VS = 2.25V to 6.0V
120
135
-
dB
VS = 2.25V to 6.0V
120
-
-
dB
Guaranteed by PSRR
2.25
-
6.0
V
FN6957.6
October 14, 2014
ISL28134
Electrical Specifications
operating temperature range. (Continued)
PARAMETER
IS
ISC
VOH
VS = 5V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply across the specified
DESCRIPTION
Supply Current Per Amplifier
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
RL = OPEN
-
675
900
µA
RL = OPEN
TA = -40°C to +85°C
-
-
1075
µA
RL = OPEN
TA = -40°C to +125°C
-
-
1150
µA
Short Circuit Output Source Current
RL = Short to V-
-
65
-
mA
Short Circuit Output Sink Current
RL = Short to V+
-
-65
-
mA
Output Voltage Swing, HIGH
From VOUT to V+
RL = 10kΩto VCM
15
10
-
mV
RL = 10kΩto VCM
15
-
-
mV
-
10
15
mV
VOL
Output Voltage Swing, LOW
From V- to VOUT
RL = 10kΩto VCM
RL = 10kΩto VCM
-
-
15
mV
AOL
Open Loop Gain
RL = 1MΩ
-
174
-
dB
Input Capacitance
Differential
-
5.2
-
pF
Common Mode
-
5.6
-
pF
f = 0.1Hz to 10Hz
-
250
400
nVP-P
AC SPECIFICATIONS
CIN
eN
IN
Input Noise Voltage
Input Noise Current
f = 10Hz
-
8
-
nV/Hz
f = 1kHz
-
10
-
nV/Hz
f = 1kHz
-
200
-
fA/Hz
GBWP
Gain Bandwidth Product
-
3.5
-
MHz
EMIRR
EMI Rejection Ratio
AV = +1, VIN = 200mVp-p, VCM = 0V,
V+ = 2.5V, V- = -2.5V
-
75
-
dB
Positive Slew Rate
V+ = 5V, V- = 0V, VOUT = 1V to 3V, RL = 100kΩ,
CL = 3.7pF
-
1.5
-
V/µs
-
1.0
-
V/µs
-
0.07
-
µs
-
0.17
-
µs
-
1.3
-
µs
-
2.0
-
µs
-
100
-
µs
-
3.1
-
µs
-2.5
-0.2
2.5
µV
-3.4
-
3.4
µV
TRANSIENT RESPONSE
SR
Negative Slew Rate
tr, tf, Small Signal
Rise Time, tr 10% to 90%
Fall Time, tf 10% to 90%
tr, tf Large Signal
Rise Time, tr 10% to 90%
Fall Time, tf 10% to 90%
V+ = 5V, V- = 0V, VOUT = 0.1VP-P, RF = 0Ω,
RL = 100kΩ, CL = 3.7pF
V+ = 5V, V- = 0V, VOUT = 2VP-P, RF = 0Ω,
RL = 100kΩ, CL = 3.7pF
ts
Settling Time to 0.1%, 2VP-P Step
AV = -1, RF = 1kΩ, CL = 3.7pF
trecover
Output Overload Recovery Time, Recovery AV = +2, RF = 10kΩ, RL = 100k, CL = 3.7pF
to 90% of Output Saturation
VOS
Input Offset Voltage
TA = -40°C to +85°C
TCVOS
Input Offset Voltage Temperature
Coefficient
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5
TA = -40°C to +125°C
-4
-
-4
µV
TA = -40°C to +125°C
-15
-0.5
15
nV/°C
FN6957.6
October 14, 2014
ISL28134
Electrical Specifications
operating temperature range.
PARAMETER
VS = 2.5V, VCM = 1.25V, TA = +25°C, unless otherwise specified. Boldface limits apply over the specified
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
-300
±120
300
pA
TA = -40°C to +85°C
-300
-
300
pA
TA = -40°C to +125°C
-550
-
550
pA
TA = -40°C to +85°C
-
±1.4
-
pA/°C
TA = -40°C to +125°C
-
±2
-
pA/°C
-600
±240
600
pA
TA = -40°C to +85°C
-600
-
600
pA
TA = -40°C to +125°C
-750
-
750
pA
TA = -40°C to +85°C
-
±2.8
-
pA/°C
TA = -40°C to +125°C
-
±4
-
pA/°C
V+ = 2.5V, V- = 0V
Guaranteed by CMRR
-0.1
-
2.6
V
VCM = -0.1V to 2.6V
120
135
-
dB
VCM = -0.1V to 2.6V
DESCRIPTION
TEST CONDITIONS
DC SPECIFICATIONS
IB
TCIB
IOS
TCIOS
Input Bias Current
Input Bias Current Temperature
Coefficient
Input Offset Current
Input Offset Current Temperature
Coefficient
Common Mode Input
Voltage Range
CMRR
Common Mode Rejection Ratio
IS
Supply Current per Amplifier
115
-
-
dB
RL = OPEN
-
715
940
µA
RL = OPEN
TA = -40°C to +85°C
-
-
1115
µA
RL = OPEN
TA = -40°C to +125°C
-
-
1190
µA
Short Circuit Output Source Current
RL = Short to Ground
-
65
-
mA
Short Circuit Output Sink Current
RL = Short to V+
-
-65
-
mA
VOH
Output Voltage Swing, HIGH
From VOUT to V+
RL = 10kΩ to VCM
15
10
-
mV
RL = 10kΩ to VCM
15
-
-
mV
VOL
Output Voltage Swing, LOW
From V- to VOUT
RL = 10kΩ to VCM
-
10
15
mV
RL = 10kΩ to VCM
-
-
15
mV
Differential
-
5.2
-
pF
Common Mode
-
5.6
-
pF
f = 0.1Hz to 10Hz
-
250
400
nVP-P
f = 10Hz
-
8
-
nV/Hz
f = 1kHz
-
10
-
nV/Hz
f = 1kHz
-
200
-
fA/Hz
-
3.5
-
MHz
ISC
AC SPECIFICATIONS
CIN
eN
Input Capacitance
Input Noise Voltage
IN
Input Noise Current
GBWP
Gain Bandwidth Product
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6
FN6957.6
October 14, 2014
ISL28134
Electrical Specifications
operating temperature range. (Continued)
PARAMETER
VS = 2.5V, VCM = 1.25V, TA = +25°C, unless otherwise specified. Boldface limits apply over the specified
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
-
1.5
-
V/µs
-
1.0
-
V/µs
-
0.07
-
µs
-
0.17
-
µs
-
1.3
-
µs
-
2.0
-
µs
-
100
-
µs
-
1.5
-
µs
TRANSIENT RESPONSE
SR
Positive Slew Rate
V+ = 2.5V, V- = 0V, VOUT = 0.25V to 2.25V,
RL = 100kΩ, CL = 3.7pF
Negative Slew Rate
tr, tf, Small Signal
Rise Time, tr 10% to 90%
V+ = 2.5V, V- = 0V, VOUT = 0.1VP-P,
RF = 0Ω, RL = 100kΩ, CL = 3.7pF
Fall Time, tf 10% to 90%
tr, tf Large Signal
Rise Time, tr 10% to 90%
V+ = 2.5V, V- = 0V, VOUT = 2VP-P, RF = 0Ω,
RL = 100kΩ, CL = 3.7pF
Fall Time, tf 10% to 90%
ts
Settling Time to 0.1%, 2VP-P Step
trecover
Output Overload Recovery Time, Recovery AV = +2, RF = 10kΩ, RL = 100k,
to 90% of Output Saturation
CL = 3.7pF
AV = -1, RF = 1kΩ, CL = 3.7pF
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
TA = +25°C, VCM = 0V Unless otherwise specified.
2.0
2.0
1.5
1.5
1.0
1.0
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE (µV)
Typical Performance Curves
0.5
0
-0.5
-1.0
VS = ±2.5V
-1.5
-20
0
-0.5
-1.0
10
70
40
TEMPERATURE (°C)
100
130
40
70
100
130
160
Vs = ±2.5V
VCM = 0V
T = -40°C to +125°C
N = 2796
140
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
10
FIGURE 4. VOS vs TEMPERATURE, VS = ±1.125V
1000
800
600
400
120
Vs = ±2.5V
VCM = 0V
T = -40°C to +125°C
N = 480
100
80
60
40
20
200
0
-20
TEMPERATURE (°C)
1600
1200
VCM = 0V
-2.0
-50
FIGURE 3. VOS vs TEMPERATURE, VS = ±2.5V
1400
VS = ±1.125V
-1.5
VCM = 0V
-2.0
-50
0.5
-2.5
-2.0 -1.5 -1.0 -0.5
0
0.5
1.0
1.5
VOS (µV)
FIGURE 5. VOS HISTOGRAM VS = 5V
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7
2.0
2.5
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
TCVOS (nV/°C)
FIGURE 6. TCVOS HISTOGRAM VS = 5V
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
120
1400
Vs = ±1.25V
VCM = 0V
T = -40°C to +125°C
N = 2325
1000
800
600
400
80
60
40
20
200
0
Vs = ±1.25V
VCM = 0V
T = -40°C to +125°C
N = 310
100
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
1200
-2.5
-2.0 -1.5
-1.0 -0.5
0
0.5
1.0
1.5
2.0
0
2.5
-10
-8
-6
-4
4
4
3
3
2
2
Vs = ±2.5V
0
-1
-2
Vs = ±1.125V
-3
6
8
10
0
-1
-2
-2.4
-1.6
-0.8
0
0.8
1.6
2.4
-4
1.0
3.2
1.5
2.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
COMMON MODE VOLTAGE (V)
FIGURE 10. VOS vs SUPPLY VOLTAGE
600
500
400
IB+ Vs = ±2.5V
500
IB+ Vs = ±1.125V
INPUT OFFSET CURRENT (pA)
INPUT BIAS CURRENT (pA)
4
1
FIGURE 9. VOS vs VCM
200
100
0.00 IB- Vs = ±2.5V
IB- Vs = ±1.125V
-100
-200
-300
-400
-500
-3
2
-3
-4
-3.2
300
0
FIGURE 8. TCVOS HISTOGRAM VS = 2.5V
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE (µV)
FIGURE 7. VOS HISTOGRAM VS = 2.5V
1
-2
TCVOS (nV/°C)
VOS (µV)
-2
-1
0
1
COMMON MODE VOLTAGE (V)
FIGURE 11. IB vs VCM
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8
2
3
400
300
Vs = ±2.5V
200
100
-100
Vs = ±1.125V
-200
-3
-2
-1
0
1
2
3
COMMON MODE VOLTAGE (V)
FIGURE 12. IOS vs VCM
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
350
350
IB+
VS = ±2.5V
300
INPUT OFFSET CURRENT (pA)
INPUT BIAS CURRENT (pA)
300
250
IB+
VS = ±1.125V
200
150
IBVS = ±1.125V
100
IBVS = ±2.5V
50
0
-50
250
VS = ±2.5V
200
150
100
50
VS = ±1.125V
0
-50
-100
-100
-40
-20
0
20
40
60
80
100
120
-150
-40
140
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. IB vs TEMPERATURE
FIGURE 14. IOS vs TEMPERATURE
160
1000
T = +125°C
CMRR/PSRR (dB)
SUPPLY CURRENT (µA)
PSRR
150
140
130
CMRR
120
PSRR
VS = ±1.125V TO ±3V
VCM = 0V
110
100
-40
-20
0
20
CMRR
VS =±2.5V
VCM = -2.6V TO +2.6V
40
60
80
100
120
900
800
T = +25°C
700
600
500
2.0
140
T = +85°C
T = -40°C
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
1000
1000
VS = ±2.5V
T = -40°C to +125°C
VS = ±2.5V
T = -40°C to +125°C
VOLTAGE FROM V- RAIL (mV)
VOLTAGE FROM V+ RAIL (mV)
6.0
5.0
SUPPLY VOLTAGE (V)
FIGURE 15. CMRR and PSRR vs TEMPERATURE
100
10
1
0.01
4.0
3.0
TEMPERATURE (°C)
1.0
0.1
10
100
LOAD CURRENT (mA)
FIGURE 17. OUTPUT HIGH OVERHEAD VOLTAGE vs LOAD CURRENT
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9
100
10
1
0.01
0.1
1.0
10
100
LOAD CURRENT (mA)
FIGURE 18. OUTPUT LOW OVERHEAD VOLTAGE vs LOAD CURRENT
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
1.0
1.0
RL = 1kΩ
VOLTAGE FROM V- RAIL (mV)
VOLTAGE FROM V+ RAIL (mV)
VS = ±2.5V
RL = OUT to GND
0.1
0.01
RL = 12.5kΩ
VS = ±2.5V
RL = OUT to GND
RL = 1kΩ
0.1
0.01
RL = 12.5kΩ
0.001
-40
-20
0
20
40
60
80
100
120
0.001
-40
140
-20
0
20
40
60
80
100
120
140
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 19. VOH vs TEMPERATURE
FIGURE 20. VOL vs TEMPERATURE
300
100
VOLTAGE (nV)
NOISE (nV√Hz)
200
10
100
0.00
-100
VS = ±2.5V
AV = 10,000
Rg = 10, Rf = 100k
-200
1
0.001
0.01
0.1
1
-300
10
0
1
2
3
4
7
8
140
1000
VS = ±2.5V
AV = 1
RS = 5MΩ
100
CIN+ =100pF
100
80
60
40
20
VS = ±2.5V
RL = 10MΩ
0
1
10
100
1000
10k
100k
FREQUENCY (Hz)
FIGURE 23. INPUT NOISE CURRENT DENSITY vs FREQUENCY
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10
PHASE
GAIN
120
GAIN (dB) / PHASE (°)
CIN+ = 0pF
CURRENT NOISE (fA/√Hz)
6
FIGURE 22. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
FIGURE 21. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY
10
0.1
5
TIME (s)
FREQUENCY (Hz)
-20
SIMULATION
0.1
1
10
100
1k
10k
100k
1M
10M 100M
FREQUENCY (Hz)
FIGURE 24. OPEN LOOP GAIN AND PHASE, RL = 10M
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
90
140
PHASE
GAIN
80
70
60
100
50
80
GAIN (dB)
GAIN (dB) / PHASE (°)
120
60
40
40
30
20
10
0
20
0
VS = ±2.5V
-10
RL = 10kΩ
-20
SIMULATION
-20
0.1
1
10
AV = 10,000
Rg = 10, Rf = 100k
AV = 1000
Rg = 100, Rf = 100k
AV = 100
AV = 10
VS = ± 2.5V
CL = 3.7pF
RL = 100k
VOUT = 10mVP-P
Rg = 1k, Rf = 100k
Rg = 10k, Rf = 100k
AV = 1
Rg = OPEN, Rf = 0
-30
100
1k
10k
100k
1M
10M
-40
100M
10
100
1k
10k
100k
10M
1M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. OPEN LOOP GAIN AND PHASE, RL = 10k
FIGURE 26. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
2
4
1
2
0
-2
GAIN (dB)
GAIN (dB)
RL > 10kΩ
0
1
RL > 10kΩ
-3
-4
-2
RL = 1kΩ
-4
RL = 1kΩ
-5
-6
VS = ± 1.25V
AV = 1V
CL = 3.7pF
VOUT = 10mVP-P
-6
-7
-8
10k
-8
100k
1M
-10
100k
10M
VS = ± 2.5V
AV = 1V
CL = 3.7pF
VOUT = 10mVP-P
1M
FREQUENCY (Hz)
FIGURE 27. GAIN vs FREQUENCY vs RL, VS = 2.5V
2
Rg = 100k, Rf = 100k
VS = ± 2.5V
AV = 2V
RL = 100k
VOUT = 10mVP-P
10
0
-2
Rg = 1k, Rf = 1k
0
GAIN (dB)
Rg = 10k, Rf = 10k
5
-4
1VP-P
500mVP-P
-6
-5
-10
100M
FIGURE 28. GAIN vs FREQUENCY vs RL, VS = 5.0V
15
NORMALIZED GAIN (dB)
10M
FREQUENCY (Hz)
-8
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 29. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES
Rf/Rg
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11
-10
10
250mVP-P
VS = ± 2.5V
AV = 1V
RL = OPEN
CL = 3.7pF
100
100mVP-P
10mVP-P
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 30. GAIN vs FREQUENCY vs VOUT
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
12
2
824pF
VS = ± 2.5V
AV = 1V
RL = 100k
VOUT = 10mVP-P
10
8
±1.5V
1nF
-2
GAIN (dB)
104pF
4
2
51pF
0
±0.8V
-4
-6
VOUT = 10mVP-P
AV = 1V
RL = 100k
CL = 3.7pF
-2
-8
3.7pF
-4
-6
10k
100k
1M
10M
±3.0V
0
474pF
6
GAIN (dB)
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
-10
1M
100M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 32. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 31. GAIN vs FREQUENCY vs CL
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1k
10k
FREQUENCY (MHz)
160
160
140
140
120
120
CMRR (dB)
CMRR (dB)
FIGURE 33. EMIRR AT IN+ PIN vs FREQUENCY
100
80
60
20
40
SIMULATION
1m
0.1
10
1k
100k
FREQUENCY (Hz)
FIGURE 34. CMRR vs FREQUENCY, VS = 5V
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80
60
VS = ±2.5V
VCM = 0V
40
100
12
10M
20
1m
VS = ±1.25V
VCM = 0V
SIMULATION
0.1
10
1k
100k
10M
FREQUENCY (Hz)
FIGURE 35. CMRR vs FREQUENCY, VS = 2.5V
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
120
140
-PSRR
120
100
+PSRR
80
+PSRR
GAIN (dB)
GAIN (dB)
100
80
60
-PSRR
60
40
VS = ± 2.5VDC
AV = 1V
RL = 100k
VIN = 1VP-P
40
20
0
10
VS = ± 1.25VDC
AV = 1V
RL = 100k
VIN = 1VP-P
20
100
1k
10k
100k
1M
0
10
10M
100
1k
FREQUENCY (Hz)
4
4.5
3
4.0
2
3.5
1
3.0
0
VS = ±2.5V
AV = 1V
RL = 1MΩ
VIN = -3V TO 3V
-2
5
10
10M
2.5
2.0
OUTPUT
1.5
VS = 5VDC
AV = 1V
RL = 100k
VIN = 1V TO 4V
0.5
0
1M
INPUT
1.0
-3
-4
100k
FIGURE 37. PSRR vs FREQUENCY, VS = 2.5V
VOLTAGE (V)
VOLTAGE (V)
FIGURE 36. PSRR vs FREQUENCY, VS = 5V
-1
10k
FREQUENCY (Hz)
15
0.0
20
0
5
10
TIME (ms)
15
20
TIME (µs)
FIGURE 38. NO PHASE INVERSION
FIGURE 39. LARGE SIGNAL STEP RESPONSE (3V)
1.2
0.10
1.0
INPUT
VOLTAGE (V)
VOLTAGE (V)
0.08
0.8
0.6
OUTPUT
0.4
0
0
2
4
6
8
FIGURE 40. LARGE SIGNAL STEP RESPONSE (1V)
13
INPUT
0.02
VS = ±2.5VDC
AV = 1V
RL = 100k
VIN = 0V TO 0.1V
-0.02
TIME (µs)
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0.04
0
VS = 5VDC
AV = 1V
RL = 100k
VIN = 0.1V TO 1.1V
0.2
OUTPUT
0.06
10
-0.04
0
2
4
6
8
10
TIME (µs)
FIGURE 41. SMALL SIGNAL STEP RESPONSE (100mV)
FN6957.6
October 14, 2014
ISL28134
Typical Performance Curves
60
55
55
50
- OS
50
45
40
+OS
35
30
25
VS = ±2.5V
AV = 1V
RL = 100k
VOUT = 100mVp-p
20
15
10
10
- OS
45
OVERSHOOT (%)
OVERSHOOT (%)
TA = +25°C, VCM = 0V Unless otherwise specified. (Continued)
100
1000
LOAD CAPACITANCE (pF)
FIGURE 42. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE,
VS = ±2.5V
Applications Information
Functional Description
40
35
30
+OS
25
VS = ±1.25V
AV = 1V
RL = 100k
VOUT = 100mVp-p
20
15
10
10
100
1000
LOAD CAPACITANCE (pF)
FIGURE 43. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE,
VS = ±1.25V
0.01µF or larger high frequency decoupling capacitor is placed
across the power supply pins of the IC to maintain high performance
of the amplifier.
The ISL28134 is a single 5V rail-to-rail input/output amplifier
that operates on a single or dual supply. The ISL28134 uses a
proprietary chopper-stabilized technique that combines a 3.5MHz
main amplifier with a very high open loop gain (174dB) chopper
amplifier to achieve very low offset voltage and drift (0.2µV,
0.5nV/°C) while having a low supply current (675µA). The very low
1/f noise corner <0.1Hz and low input noise voltage (8nV/√Hz at
100Hz) of the amplifier makes it ideal for low frequency precision
applications requiring very high gain and low noise.
Rail-to-rail Input and Output (RRIO)
This multi-path amplifier architecture contains a time continuous
main amplifier whose input DC offset is corrected by a
parallel-connected, high gain chopper stabilized DC correction
amplifier operating at 100kHz. From DC to ~10kHz, both
amplifiers are active with the DC offset correction active with
most of the low frequency gain provided by the chopper
amplifier. A 10kHz crossover filter cuts off the low frequency
chopper amplifier path leaving the main amplifier active out to
the -3dB frequency (3.5MHz GBWP).
Low Input Voltage Noise Performance
The key benefits of this architecture for precision applications are
rail-to-rail inputs/outputs, high open loop gain, low DC offset and
temperature drift, low 1/f noise corner and low input noise
voltage. The noise is virtually flat across the frequency range
from a few MHz out to 100kHz, except for the narrow noise peak
at the amplifier crossover frequency (10kHz).
Power Supply Considerations
The ISL28134 features a wide supply voltage operating range. The
ISL28134 operates on single (+2.25V to +6.0V) or dual (±1.125 to
±3.0V) supplies. Power supply voltages greater than the +6.5V
absolute maximum (specified in the “Absolute Maximum Ratings”
on page 4) can permanently damage the device. Performance of
the device is optimized for supply voltages greater than 2.5V. This
makes the ISL28134 ideal for portable 3V battery applications that
require the precision performance. It is highly recommended that a
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14
Unlike some amplifiers whose inputs may not be taken to the power
supply rails or whose outputs may not drive to the supply rails, the
ISL28134 features rail-to-rail inputs and outputs. This allows the
amplifier inputs to have a wide common mode range (100mV
beyond supply rails) while maintaining high CMRR (135dB) and
maximizes the signal to noise ratio of the amplifier by having the
VOH and VOL levels be at the V+ and V- rails, respectively.
In precision applications, the input noise of the front end
amplifier is a critical parameter. Combined with a high DC gain to
amplify the small input signal, the input noise voltage will result
in an output error in the amplifier. A 1µVP-P input noise voltage
with an amplifier gain of 10,000V/V will result in an output offset
in the range of 10mV, which can be an unacceptable error
source. With only 250nVP-P at the input, along with a flat noise
response down to 0.1Hz, the ISL28134 can amplify small input
signals with minimal output error.
The ISL28134 has the lowest input noise voltage compared to
other competitor Zero Drift amplifiers with similar supply
currents (see Table 1). The overall input referred voltage noise of
an amplifier can be expressed as a sum of the input noise
voltage, input noise current of the amplifier and the Johnson
noise of the gain-setting resistors used. The product of the input
noise current and external feedback resistors along with the
Johnson noise, increases the total output voltage noise as the
value of the resistance goes up. For optimizing noise
performance, choose lower value feedback resistors to minimize
the effect of input noise current. Although the ISL28134 features
a very low 200fA/Hz input noise current, at source impedances
>100kΩ, the input referred noise voltage will be dominated by
the input current noise. Keep source input impedances under
10kΩ for optimum performance.
FN6957.6
October 14, 2014
ISL28134
IN+ and IN- Protection
TABLE 1.
PART
VOLTAGE NOISE AT
100Hz
0.1Hz TO 10Hz PEAK-TO-PEAK
VOLTAGE NOISE
Competitor A
22nV/√Hz
600nVP-P
Competitor B
16nV/√Hz
260nVP-P
Competitor C
90nV/√Hz
1500nVP-P
ISL28134
8nV/√Hz
250nVP-P
The ISL28134 is capable of driving the input terminals up to and
beyond the supply rails by about 0.5V. Back biased ESD diodes
from the input pins to the V+ and V- rails will conduct current
when the input signals go more than 0.5V beyond the rail (see
Figure 45). The ESD protection diodes must be current limited to
20mA or less to prevent damage of the IC. This current can be
reduced by placing a resistor in series with the IN+ and IN- inputs
in the event the input signals go beyond the rail.
High Source Impedance Applications
The input stage of Chopper Stabilized amplifiers do not behave
like conventional amplifier input stages. The ISL28134 uses
switches at the chopper amplifier input that continually ‘chops’
the input signal at 100kHz to reduce input offset voltage down to
1µV. The dynamic behavior of these switches induces a charge
injection current to the input terminals of the amplifier. The
charge injection current has a DC path to ground through the
resistances seen at the input terminals of the amplifier. Higher
input impedance cause an apparent shift in the input bias
current of the amplifier. Input impedances larger than 10kΩ
begin to have significant increases in the bias currents. To
minimize the effect of impedance on input bias currents, an
input resistance of <10kΩ is recommended.
Because the chopper amplifier has charge injection currents at
each terminal, the input impedance should be balanced across
each input (see Figure 44). The input impedance of the amplifier
should be matched between the IN+ and IN- terminals to
minimize total input offset current. Input offset currents show up
as an additional output offset voltage, as shown in Equation 1:
VOSTOT = VOS - RF*IOS
(EQ. 1)
If the offset voltage of the amplifier is negative, the input offset
currents will add to the total output offset. For a 10,000V/V gain
amplifier using 1MΩ feedback resistor, a 500pA total input offset
current will have an additional output offset voltage of 0.5mV. By
keeping the input impedance low and balanced across the
amplifier inputs, the input offset current is kept below 100pA,
resulting in an offset voltage 0.1mV or less.
RI
RF
+2.5V
VIN
RS
VIN
IN+
-
VOUT
+
ESD
DIODES
RL
V+
V-
FIGURE 45. INPUT CURRENT LIMITING
EMI Rejection
Electromagnetic Interference (EMI) can be a problem in high
frequency applications for precision amplifiers. The op amp pins
are susceptible to EMI signals which can rectify high frequency
inputs beyond the amplifier bandwidth and present itself as a
shift in DC offset voltage. Long trace leads to op amp pins may
act as an antenna for radiated RF signals, which result in a total
conductive EMI noise into the op amp inputs.
The most susceptible pin is the non-inverting IN+ input therefore,
EMI rejection (EMIR) on this pin is important for RF type
applications. The ability of the amplifier output to reject EMI is
called EMI Rejection Ratio (EMIRR) and is computed as:
EMIRR (dB) = 20 log (VIN_PEAK/ΔVOS
The test circuit for measuring the DC offset of the amplifier with
an RF signal input to the IN+ pin is shown in Figure 46. The
EMIRR performance of the ISL28134 at the IN+ pin across a
frequency of 10MHz to 2.4GHz is plotted on Figure 33. The
ISL28134 shows a typical EMIRR of 75dB at 1GHz. For better EMI
immunity, a small RFI filter can be placed at the input to
attenuate out of band signals and reduce DC offset shift from
high frequency RF signals into the IN+ pin. For example, a 15Ω
and 100pF RC filter will roll off signals above 100MHz for better
EMIRR performance.
VOUT
+
RL
Rg
-2.5V
RF//RI = RS//Rg
FIGURE 44. CIRCUIT IMPLEMENTATION FOR REDUCING INPUT
BIAS CURRENTS
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INRIN
15
INVIN = 200mVP-P
IN+
+2.5V
-
VOUT
+
RL= 10kΩ
-2.5V
FIGURE 46. CIRCUIT TESTING EMIRR
FN6957.6
October 14, 2014
ISL28134
Output Phase Reversal
ISL28134 SPICE Model
The Output phase reversal is the unexpected inversion of the
amplifier output signal when the inputs exceed the common
mode input range. Since the ISL28134 is a rail-to-rail input
amplifier, the ISL28134 is specifically designed to prevent output
phase reversal within its common mode input range. In fact, the
ISL28134 will not phase invert even when the input signals go
0.5V beyond the supply rails (see Figure 38). If input signals are
expected to go beyond the rails, it is highly recommended to
minimize the forward biased ESD diode current to prevent phase
inversion by placing a resistor in series with the input.
Figure 48 shows the SPICE model schematic and Figure 49 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. The AC parameters incorporated into the model are:
1/f and flat band noise voltage, slew rate, CMRR, and gain and
phase. The DC parameters are IOS, VOS, total supply current,
output voltage swing and output current limit (65mA). The model
uses typical parameters given in the “Electrical Specifications”
table beginning on page 4. The AVOL is adjusted for 174dB with
the dominant pole at 6.5mHz. The CMRR is set at 135dB,
f = 200Hz. The input stage models the actual device to present an
accurate AC representation. The model is configured for an
ambient temperature of +25°C.
High Gain, Precision DC-Coupled Amplifier
Precision applications that need to amplify signals in the range
of a few µV require gain in the order of thousands of V/V to get a
good signal to the Analog to Digital Converter (ADC). This can be
achieved by using a very high gain amplifier with the appropriate
open loop gain and bandwidth.
In addition to the high gain and bandwidth, it is important that
the amplifier have low VOS and temperature drift along with a
low input noise voltage. For example, an amplifier with 100µV
offset voltage and 0.5µV/°C offset drift configured in a closed loop
gain of 10,000V/V would produce an output error of 1V and a
5mV/°C temperature dependent error. Unless offset trimming and
temperature compensation techniques are used, this error makes it
difficult to resolve the input voltages needed in the precision
application.
The ISL28134 features a low VOS of ±4µV max and a very stable
10nV/°C max temperature drift, which produces an output error of
only ±40mV and a temperature error of 0.1mV/°C. With an ultra
low input noise of 210nVP-P (0.1Hz to 10Hz) and no 1/f corner
frequency, the ISL28134 is capable of amplifying signals in the µV
range with high accuracy. For even further DC precision, some
feedback filtering CF (see Figure 47) to reduce the noise can be
implemented as a total signal stage amplifier. As a method of best
practice, the ISL28134 should be impedance matched at the two
input terminals. A balancing capacitor of the same value at the
on-inverting terminal will result in the amplifier input impedances
tracking across frequency
CF
100Ω
1MΩ
+2.5V
ACL = 10kV/V
VIN
LICENSE STATEMENT
The information in the SPICE model is protected under United
States copyright laws. Intersil Corporation hereby grants users of
this macro-model, hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model, as long
as the Licensee abides by the terms of this agreement. Before
using this Macro-Model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
Macro-Model to suit his/her specific applications, and the
Licensee may make copies of this Macro-Model for use within
their company only.
This Macro-Model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental, or
consequential damages in connection with or arising out of the
use of this Macro-Model. Intersil reserves the right to make
changes to the product and the Macro-Model without prior notice.
VOUT
100Ω
+
1MΩ
Figures 50 through 63 show the characterization vs simulation
results for the noise voltage, open loop gain phase, closed loop
gain vs frequency, CMRR, large signal 3V step response, large
signal 1V step response, and output voltage swing VOH/VOL
±2.5V supplies (no phase inversion).
CF
RL
-2.5V
FIGURE 47. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER
Submit Document Feedback
16
FN6957.6
October 14, 2014
DX
Submit Document Feedback
V1
1e-6
D3
I2
5e-3
R1
7.5004
G1A
+
-
R2
7.5004
En
D1
+
-
+
-
28
VOS
IN-
M15
0.2E-6
9
5
EOS
DN
+
-
6
+
-
17
0
V3
0.607
100
16
D2
10
12
IOS
CinDif
4.71e-12
R23
5e11
29
10
11
D13
V9
0
10
14
R6
17
GAIN = 113.96e-3
15
PMOSISIL
M10
M11
PMOSISIL
NCHANNELMOSFET
R22
5e11
8
0.607
V4
240e-12
Vcm
R3
0.14
0.
R4
7
10
Vin-
R7
7.5
10
R8
7.5
13
RA2
G2A
G2
1
+
-
80
NCHANNELMOSFET
R11
1
R9
DX
En
R21
R5
1
1
4
M14
+
-
1
GAIN = 233.426
GAIN = 113.96e-3
DX
V2
1e-6
I1
5e-3
18
R12
+
-
Vin+
3
G1
RA1
GAIN = 233.426
IN+
R10
1e9
DX
2
D4
Cin1
10.1e-12
Cin2
10.1e-12
Differential to Single Ended
1st Gain Stage
Input Stage
Voltage Noise Stage
Conversion Stage
V+
E2
+
-
V++
DX
0
D5
L1
G11
+
-
GAIN = 68.225E-3
V5
0.607
G7
7346.06E6
GAIN = 177.83E-6
10e-12
+
-
21
D10
DX
3.33E-09
R13
D9
DX
+
-
7.957E-07
G5
+
-
C4
C2
19
G3
R17
GAIN = 879.62E-6
GAIN = 20e-3
1136.85
R15
1.00E-03
D7
DX
24
VOUT
1.04
Vc
23
Vg
R19
50
V7
26
27
Vmid
ISY
675E-6
D8
1.04
R16
1.00E-03
G8
+
GAIN = 68.225E-3
3.33E-09
G6
L2
R18
G10
1136.85
C5
GAIN = 879.62E-6
7.957E-07
10e-12
G9
D11
+
-
+
-
GAIN = 20e-3
DX
GAIN = 20e-3
GAIN = 177.83E-6
V-E3
2nd Gain Stage
Mid Supply ref V
D12
G12
GAIN = 20e-3
D6
Common Mode
Gain Stage
with Zero
DY
C3
DY
22
R14
7346.06E6
+
-
20
G4
+
-
V8
+
-
V6
+
-
0.607
+
-
25
DX
E4
V-
+
-
+
-
2nd Pole Stage
GAIN = 1
FN6957.6
October 14, 2014
0
Supply Isolation
Stage
FIGURE 48. SPICE SCHEMATIC
Output Stage
R20
50
ISL28134
+
-
GAIN = 1
ISL28134
*ISL28134 Macromodel
*
*Revision History:
* Revision A, LaFontaine June 17th 2011
* Model for Noise, quiescent supply currents,
*CMRR135dB f = 200Hz, AVOL 174dB f =
*6.5mHz, SR = 1.5V/us, GBWP 3.5MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms – such as
*iSim PE.
*
*Device performance features supported by
*this model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate, Input and Output Headroom limits
*to I/O voltage swing, Supply current at
*nominal specified supply voltages,
*Output current limiting (65mA)
*
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects,
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Performance variation vs. supply voltage,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28134
*
* Connections: +input
*
| -input
*
| | +Vsupply
*
| |
| -Vsupply
*
| |
| | output
*
| |
| |
|
.subckt ISL28134 Vin+ Vin- V+ V- VOUT
*
*Voltage Noise
E_En
VIN+ EN 28 0 1
D_D13
29 28 DN
V_V9
29 0 0.14
R_R21
28 0 80
*
*Input Stage
M_M10
11 VIN- 9 9 PMOSISIL
M_M11
12 1 10 10 PMOSISIL
M_M14
3 1 5 5 NCHANNELMOSFET
M_M15
4 VIN- 6 6 NCHANNELMOSFET
I_I1
7 V-- DC 5e-3
I_I2
V++ 8 DC 5e-3
I_IOS
VIN- 1 DC 240e-12
G_G1A
V++ 14 4 3 233.4267
G_G2A
V-- 14 11 12 233.4267
V_V1
V++ 2 1e-6
V_V2
13 V-- 1e-6
V_VOS
EN 30 0.2E-6
R_R1
3 2 7.5004
R_R2
4 2 7.5004
R_R3
5 7 10
R_R4
7 6 10
R_R5
9 8 10
R_R6
8 10 10
R_R7
13 11 7.5
R_R8
13 12 7.5
R_RA1
14 V++ 1
R_RA2
V-- 14 1
C_CinDif
VIN- EN 4.71e-12
C_Cin1
V-- 30 10.1e-12
C_Cin2
V-- VIN- 10.1e-12
*
*1st Gain Stage
G_G1
V++ 16 15 VMID 113.96e-3
G_G2
V-- 16 15 VMID 113.96e-3
V_V3
17 16 0.607
V_V4
16 18 0.607
D_D1
15 VMID DX
D_D2
VMID 15 DX
D_D3
17 V++ DX
D_D4
V-- 18 DX
R_R9
15 14 100
R_R10
15 VMID 1e9
R_R11
16 V++ 1
R_R12
V-- 16 1
*
*2nd Gain Stage
G_G3
V++ VG 16 VMID 68.225E-3
G_G4
V-- VG 16 VMID 68.225E-3
V_V5
19 VG 0.607
V_V6
VG 20 0.607
D_D5
19 V++ DX
D_D6
V-- 20 DX
R_R13
VG V++ 7346.06E6
R_R14
V-- VG 7346.06E6
C_C2
VG V++ 3.33E-09
C_C3
V-- VG 3.33E-09
*
*Mid supply Ref
E_E4
VMID V-- V++ V-- 0.5
*
*Supply Isolation Stage
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
I_ISY
V+ V- DC 675E-6
*
*Common Mode Gain Stage
G_G5
V++ VC VCM VMID 177.83E-6
G_G6
V-- VC VCM VMID 177.83E-6
E_EOS
1 30 VC VMID 1
R_R15
VC 21 1.00E-03
R_R16
22 VC 1.00E-03
R_R22
EN VCM 5e11
R_R23
VCM VIN- 5e11
L_L1
21 V++ 7.957E-07
L_L2
22 V-- 7.957E-07
*
*2nd Pole Stage
G_G7
V++ 23 VG VMID 879.62E-6
G_G8
V-- 23 VG VMID 879.62E-6
R_R17
23 V++ 1136.85
R_R18
V-- 23 1136.85
C_C4
23 V++ 10e-12
C_C5
V-- 23 10e-12
*
*Output Stage
G_G9
26 V-- VOUT 23 20e-3
G_G10
27 V-- 23 VOUT 20e-3
G_G11
VOUT V++ V++ 23 20e-3
G_G12
V-- VOUT 23 V-- 20e-3
V_V7
24 VOUT 1.04
V_V8
VOUT 25 1.04
D_D7
23 24 DX
D_D8
25 23 DX
D_D9
V++ 26 DX
D_D10
V++ 27 DX
D_D11
V-- 26 DY
D_D12
V-- 27 DY
R_R19
VOUT V++ 50
R_R20
V-- VOUT 50
*
.model pmosisil pmos (kp=16e-3 vto=-0.6
+kf=0 af=1)
.model NCHANNELMOSFET nmos (kp=3e-3
+vto=0.6 kf=0 af=1)
.model DN D(KF=6.69e-9 af=1)
.MODEL DX D(IS=1E-12 Rs=0.1 kf=0 af=1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1 kf=0
+af=1)
.ends ISL28134
FIGURE 49. SPICE NET LIST
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FN6957.6
October 14, 2014
ISL28134
Characterization vs Simulation Results
400
VOLTAGE NOISE (nV/√Hz)
VOLTAGE NOISE (nV/√Hz)
100
10
100
10
VS = ±2.5V
AV = 1
VS = ±2.5V
AV = 1
1
0.001
0.01
0.1
1
10
100
FREQUENCY (Hz)
1000
10k
1.0
1.0m
100k
100m
GAIN (dB) / PHASE (°)
80
60
40
20
VS = ±2.5V
RL = 10MΩ
0
100
60
40
20
1
10
VOS = 0
0
100
1k
10k
100k
1M
10M
-20
0.1
100M
1
10
100
20
10
0
70
Rg = 100, Rf = 100k
50
AV = 100
AV = 10
VS = ± 2.5V
CL = 3.7pF
RL = 100k
VOUT = 10mVP-P
Rg = 1k, Rf = 100k
Rg = 10k, Rf = 100k
AV = 1
-10
60
GAIN (dB)
GAIN (dB)
30
80
Rg = 10, Rf = 100k
AV = 1000
10k
100k
1M
10M
100M
FIGURE 53. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
90
AV = 10,000
1k
FREQUENCY (Hz)
FIGURE 52. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
40
100k
PHASE
FREQUENCY (Hz)
50
10k
80
SIMULATION
-20
0.1
60
1.0k
GAIN
120
100
70
100
140
PHASE
GAIN
120
80
10
FIGURE 51. SIMULATED INPUT NOISE VOLTAGE
140
90
1.0
FREQUENCY (Hz)
FIGURE 50. CHARACTERIZED INPUT NOISE VOLTAGE
GAIN (dB) / PHASE (°)
10m
40
30
AV = 10,000
Rg = 10, Rf = 100k
AV = 1000
Rg = 100, Rf = 100k
AV = 100
AV = 10
Rg = 1k, Rf = 100k
20
10
0
Rg = 10k, Rf = 100k
AV = 1
-10
Rg = OPEN, Rf = 0
-20
VS = ± 2.5V
CL = 3.7pF
RL = 100k
VOUT = 10mVP-P
Rg = OPEN, Rf = 0
-20
-30
-30
-40
10
-40
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 54. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY
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19
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 55. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY
FN6957.6
October 14, 2014
ISL28134
(Continued)
160
160
140
140
120
120
CMRR (dB)
CMRR (dB)
Characterization vs Simulation Results
100
80
60
100
80
60
VS = ±2.5V
VCM = 0V
40
40
SIMULATION
20
1m
0.1
VS = ±2.5V
VCM = 0V
10
1k
100k
SIMULATION
20
1m
10M
0.1
FREQUENCY (Hz)
4.5
4.0
4.0
3.5
10M
3.5
3.0
VOLTAGE (V)
INPUT
2.5
2.0
OUTPUT
1.5
VS = 5VDC
AV = 1V
RL = 100k
VIN = 1V TO 4V
1.0
0.5
0
0
2
INPUT
2.5
2.0
OUTPUT
1.5
VS = 5VDC
AV = 1V
RL = 100k
VIN = 1V TO 4V
1.0
0.5
6
4
3.0
8
0
10
0
2
1.2
1.0
1.0
VOLTAGE (V)
INPUT
0.6
OUTPUT
VS = 5VDC
AV = 1V
RL = 100k
VIN = 0.1V TO 1.1V
0.2
0
2
6
4
8
10
FIGURE 60. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE
20
0.8
INPUT
0.6
OUTPUT
0.4
VS = 5VDC
AV = 1V
RL = 100k
VIN = 0.1V TO 1.1V
0.2
TIME (µs)
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10
FIGURE 59. SIMULATED LARGE SIGNAL STEP RESPONSE (3V)
1.2
0.4
8
TIME (µs)
FIGURE 58. CHARACTERIZED LARGE SIGNAL STEP RESPONSE (3V)
0.8
6
4
TIME (µs)
VOLTAGE (V)
100k
FIGURE 57. SIMULATED CMRR vs FREQUENCY
4.5
0
1k
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED CMRR vs FREQUENCY
VOLTAGE (V)
10
0
0
2
6
4
8
10
TIME (µs)
FIGURE 61. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE
FN6957.6
October 14, 2014
ISL28134
Characterization vs Simulation Results
(Continued)
4.0
4
VOH = 2.489V
3
2.0
1
VOLTAGE (V)
VOLTAGE (V)
2
0
-1
VS = ±2.5V
AV = 1V
RL = 1MΩ
VIN = -3V TO 3V
-2
0
-3
-4.0
-4
0
5
10
15
TIME (ms)
FIGURE 62. CHARACTERIZED NO PHASE INVERSION
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21
20
VOL = -2.489V
VS = ±2.5V
AV = 1V
RL = 1MΩ
VIN = -4V TO 4V
-2.0
0
0.2
0.4
0.6
0.8
1.0
TIME (ms)
FIGURE 63. SIMULATED NO PHASE INVERSION, VOH AND VOL
FN6957.6
October 14, 2014
ISL28134
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
October 14, 2014
FN6957.6
Figure 44 updated from: Rs//Rg= RS//Rg to: RF//RI= RS//Rg.
Removed part numbers ISL28134FRUZ-T7 and ISL28134FBZ from ordering information table.
Removed 6 LD UTDFN throughout the document.
Removed pod L6.1.6x1.6.
July 3, 2013
FN6957.5
Updated the figure 1 on page 1, and changed title from “PRECISION 10-BIT WEIGH SCALE/STRAIN GAUGE” to
“PRECISION WEIGH SCALE / STRAIN GAUGE”.
Updated Figure 21: “Input noise voltage density vs frequency” on page 10.
Added typical EMIRR spec to Electrical Spec table under section “AC SPECIFICATIONS” on page 5.
Added applications paragraph to “EMI Rejection” on page 15.
Added 2 Figures, 33 and 46, describing the test circuit and typical performance graph for “EMI Rejection” on
page 15.
August 3, 2012
FN6957.4
Made correction to Figure 1 on page 1 by changing resistor label from “1M” to “20k”.
December 12, 2011
FN6957.3
Updated front page introduction to reflect +125°C grade and SOT-23 package release.
Updated Figure 1 with newer relevant Apps Circuit
Updated Figure 2 with extended temp range -40°C to 125°C
Updated “Ordering Information” on page 3 by removing “Coming Soon” from ISL28134FHZ SOT-23 packages.
Updated “Operating Conditions” on page 4 to include Full Industrial Grade Package.
Updated “Electrical Specifications” Tables for both Vs = 5V and Vs = 2.5V (page 4 to page 7) as follows:
Modified common conditions at top of tables from "Boldface limits apply over the operating
temperature range, -40°C to +85°C." to "Boldface limits apply over the specified operating temperature range."
Added MIN/MAX Vos spec from -40°C to 125°C: ±4µV
Updated Conditions cell for TCVos from +85°C to +125°C. No limit change.
Added MIN/MAX Ibias spec from -40°C to 125°C: ±550pA
Added Typ TCIbias spec from -40°C to 125°C: ±2pA/C
Added MIN/MAX Ios spec from -40°C to 125°C: ±750pA
Added Typ TCIos spec from TA = -40°C to +125°C: ±4pA/C
Updated Conditions cell for Common Mode Input Voltage Range Spec (removed TA = -40°C to +85°C). No limit
change.
Updated Conditions cell for CMRR for over temp (bolded) specs (removed TA = -40°C to +85°C). No limit change.
Updated Conditions cell for PSRR for over temp (bolded) specs (removed TA = -40°C to +85°C). No limit change.
Updated Conditions cell for Vs (removed TA = -40°C to +85°C). No limit change.
Added MAX Is spec from -40°C to 125°C: 1150µA
Updated Conditions cell for VOH for over temp (bolded) specs (removed TA = -40°C to +85°C). No limit change.
Updated Conditions cell for VOL for over temp (bolded) specs (removed TA = -40°C to +85°C). No limit change.
Updated the following Figures to reflect the temp range from the range of (-40°C to 85°C) to (-40°C to 125°C)
Figures 3-8, page 7 to page 8
Figures 11-20, page 8 to page 10
Minor edit to SPICE netlist Figure 49, page 18. Added “+” signs on 3 rows as follows:
“model pmosisil pmos (kp=16e-3 vto=-0.6
+kf=0 af=1)
.model NCHANNELMOSFET nmos (kp=3e-3
+vto=0.6 kf=0 af=1)
.model DN D(KF=6.69e-9 af=1)
.MODEL DX D(IS=1E-12 Rs=0.1 kf=0 af=1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1 kf=0
+af=1)
.ends ISL28134”
July 6, 2011
FN6957.2
Added Evaluation board to “Ordering Information” on page 3.
Updated “INPUT NOISE VOLTAGE DENSITY vs FREQUENCY” on page 10 (Changed MIN frequency from 100mHz
to 1mHz)
Updated “LARGE SIGNAL STEP RESPONSE (3V)” on page 13 by changing the Time from 0 to 10 to 0 to 20
Added “ISL28134 SPICE Model” section, which includes Schematic, Macromodel and Characterization vs
Simulation Results.
June 8, 2011
FN6957.1
Initial release to web.
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22
FN6957.6
October 14, 2014
ISL28134
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6957.6
October 14, 2014
ISL28134
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
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FN6957.6
October 14, 2014
ISL28134
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
D
A
0.08-0.20
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
2
5
(0.60)
0.20 C
2x
0.95
SEE DETAIL X
B
0.40 ±0.05
3
END VIEW
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
2.90
5
H
0.15 C A-B
2x
C
1.45 MAX
1.14 ±0.15
0.10 C
SIDE VIEW
SEATING PLANE
(0.25) GAUGE
PLANE
0.45±0.1
0.05-0.15
4
DETAIL "X"
(0.60)
(1.20)
NOTES:
(2.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
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FN6957.6
October 14, 2014