MN L SIs66fo2r7C8o5m TB pU acCt Disc/CD-RO M Player MN662785TBUC 1. TYPE Signal processing integrated circuit for CDs (Compact Discs) 2. OVERVIEW MN662785TBUC is a signal processing IC for CDs. It incorporates optical servo (focus, tracking, and traverse servos) processing function, digital signal processing function (EFM demodulation and error correction), digital servo processing function for spindle motor, anti-shock memory control function for 16M, 4M, or 1M DRAM in compression or decompression mode available to disc rotation synchronous playback (jitter-free), a digital filter, and D/A converter. All the processing functions after the head amplifier (RF amplifier) are incorporated into a single chip. 3. FUNCTIONS AND FEATURES (Optical servo) ・Focus (Fo), tracking (Tr), and traverse (TRV) servos ・ Automatic adjustment functions (Fo/Tr gain, Fo/Tr offset, Fo/Tr balance) ・ On-chip PWM for drive output ・Provided with a countermeasure for dropout ・ Provided with anti-shock function ・Provided with track cross detection function (Digital signal processing) ・ Containing DSL and PLL ・ Provided with a frame synchronous detection/protection/interpolation ・ Subcode data processing Q-data CRC check On-chip Q-data register On-chip CD-TEXT-data register ・CIRC error correction C1 decoder：double error correction C2 decoder：triple error correction On-chip de-interleaving 16K RAM ・Audio data interpolation processing 4-sampling linear interpolation and previous value hold ・Soft muting ・Digital attenuation (256 levels) (-∞, -48 dB to 0 dB, 256 levels) ・Soft attenuation (256 levels) (-∞, -48 dB to 0 dB, 256 levels) ・Digital audio interface (EIAJ format), IEC format ・Compatible with digital audio interface when anti-shock memory control is turned on. ・Compatible with bilingual operation when anti-shock memory control is turned on. (Spindle motor servo) ・CLV digital servo ・Provided with servo gain selection function ・Provided with shaft loss compensation setting function ・Provided with forced acceleration/deceleration output level setting function Public ation date: J une 2002 SDD00026AEM 1 MN662785TBUC (Audio circuit) ・ 8x-oversampling digital filter ・ On-chip low-voltage op amp ・ Bass boost filter, high-band notch filter, and surround function (Anti-shock memory controller) ・ ADPCM 4-bit compression or expansion mode/decompression full 16-bit mode ・ External DRAM selectable 16M DRAM (4M × 4 bits) ×1 4M DRAM (1M × 4 bits) ×2 4M DRAM (1M × 4 bits) ×1 1M DRAM (256K × 4 bits) × 2 1M DRAM (256K × 4 bits) × 1 (Others) ・ Disc rotation synchronous playback (jitter-free) mode SDD00026AEM 2 MN662785TBUC 4. PIN ASSIGNMENT TX EXT2/IBCLK/EFM EXT1/ILRCK/VDET/PCK EXT0/ISRDATA/SRMON2 IPFLAG/CLVS FLAG/SRMON1 TMOD2 TMOD1 FSEL AVDD1 OUTR AVSS1 OUTL AVSS2 AVDD2 VCOF PLLF DRF DSLF ADPVCC ・80-pin qua d fla t pa c ka ge ( LQF P 080-P -1414A) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ＭＮ６６２７８５ＴＢＵＣ 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 IREF ARF LD O N BDO NRFDET OFT RFENV TE FE CSEL TBAL FBAL FOM FOP TRM TRP TRVM TRVP SPOUT DVDD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DVDD3V D0 D1 NW E NRAS D2 D3 NCAS0 NCAS1 A8 A7 A6 A5 A4 A9 A0 A1 A2 A3 DVSS2 MCLK MDATA MLD BLKCK/DQSY1 SQCK/BCLK1/TXTCLK1 SUBQ/LRCK1/TXTDAT1 DMUTE/SRDATA1 STAT NRST SPPOL PMCK SMCK SUBC/TXTDAT2/SRDATA2 SBCK/TXTCLK2/LRCK2 NCLDCK/DQSY2/BCLK2 NTEST X1 X2 DVDD1 DVSS1 SDD00026AEM 3 MN662785TBUC SQCK/BCLK1/TXTCLK2 SUBQ/LRCK1/TXTDAT1 AVSS2 AVDD2 ARF DRF IREF DSLF PLLF VCOF MDATA MCLK/TXTCLK2 MLD STAT CSEL X1 X2 FSEL PMCK IPFLAG/CLVS SMCK 5. BLOCK DIAGRAM DVDD2 DVSS2 DVDD1 TIMING GENERATOR DVSS1 SUBCODE/CD-TEXT BUFFER DSL ･ PLL VCO TMOD1 TMOD2 EXT0/ISRDATA/SRMON2 EXT1/ILRCK/VDET/PCK EXT2/IBCLK/EFM SERVO TIMING GENERATOR NRST NTEST SYNC INTERFACE SUBC/SSYNC/ TXTDAT2/SRDATA2 SBCK/64FS/ TXTCLK2/LRCK2 NCLDCK/DQSY2/ BCLK2 DEMODULATION EFM MICROCOMPUTER INTERPOLATION SUBCODE DEMODULATION BLKCK/DQSY1 CLV NRFDET OFT SERVO INPUT PORT BDO DIGITAL SERVO CIRC ERROR CORRECTION DEINTERLEAVE FLAG/SRMON1 16K SRAM INTERPOLATION DIGITAL AUDIO INTERFACE SOFT ATTENUATION ANTI-SHOCK DIGITAL DEEMPHASIS MEMORY PWM CONTROLLER TX 1-bit DAC SDD00026AEM PWM (L) PWM (R) L.P.F L.P.F AVDD1 AVSS1 PWM+ CHARGE PUMP OUTR ADPVCC DIGITAL ATTENUATION OUTPUT PORT OUTL RFENV SOFT MUTING DMUTE/SRDATA1 TE FBAL TBAL LDON FOM FOP TRM TRP TRVM TRVP SPOUT SPPOL DVDD3V A9 to A0 D3 to D0 NCAS0 NCAS1 NRAS NWE FE A/D CONVERTER 8x-OVERSAMPLING DIGITAL FILTER 4 MN662785TBUC 6. PIN DESCRIPTIONS No. Symbol I/O Function 1 DVDD3V 2 D0 I/O DR AM da ta I/O 0 3 D1 I/O DR AM da ta I/O 1 4 NW E O DR AM write e na ble signa l output 5 NR AS O DR AM R AS c ontrol signa l output 6 D2 I/O DR AM da ta I/O 2 7 D3 I/O DR AM da ta I/O 3 8 NC AS 0 O DR AM C AS c ontrol signa l output 0 9 NC AS 1 O DR AM C AS c ontrol signa l output 1 ( W he n two 1M or 4M DR AMs a re in use ) DR AM a ddre ss signa l output 10 ( W he n 16M DR AM is in use ) 10 A8 O DR AM a ddre ss signa l output 8 11 A7 O DR AM a ddre ss signa l output 7 12 A6 O DR AM a ddre ss signa l output 6 13 A5 O DR AM a ddre ss signa l output 5 14 A4 O DR AM a ddre ss signa l output 4 15 A9 O DR AM a ddre ss signa l output 9 16 A0 O DR AM a ddre ss signa l output 0 17 A1 O DR AM a ddre ss signa l output 1 18 A2 O DR AM a ddre ss signa l output 2 19 A3 O DR AM a ddre ss signa l output 3 20 DVSS2 I Ground for digita l c irc uits 21 DVDD2 I P owe r supply for digita l c irc uits 22 S P OUT O S pindle motor drive signa l output I P owe r supply for DR AM inte rfa c e ( P ins 2 to 19) SDD00026AEM 5 MN662785TBUC No. Symbol I/O Function 23 TR VP O Tra ve rse drive signa l output ( + side output) 24 TR VM O Tra ve rse drive signa l output ( - side output) 25 TR P O Tra c king drive signa l output ( + side output) 26 TR M O Tra c king drive signa l output ( - side output) 27 F OP O F oc us drive signa l output ( + side output) 28 F OM O 29 F B AL O F oc us drive signa l output ( - side output) F oc us ba la nc e a djustme nt signa l output 30 TB AL O Tra c king ba la nc e a djustme nt signa l output 31 C S EL I Te st pin 32 FE I F oc us e rror signa l input 33 TE I Tra c king e rror signa l input 34 RFENV I R F e nve lope signa l input 35 OFT I Off-tra c k signa l input H：Off tra c k 36 NRFDET I R F de te c tion signa l input L：De te c t 37 BDO I Dropout signa l input H：Dropout 38 LDON O La se r ON signa l output H：ON 39 ARF I R F signa l input 40 IREF I R e fe re nc e c urre nt input 41 ADPVCC I A/D c onve rte r re fe re nc e volta ge input 42 DSLF O DS L loop filte r 43 DRF I DS L bia s 44 PLLF O P LL loop filte r 45 VCOF O Jitte r-fre e VC O loop filte r 46 AVDD2 I P owe r supply for a na log c irc uits ( F or DS L, P LL, VC OF , DR F , a nd A/D c onve rte r) 47 AVSS2 I Ground for a na log c irc uits ( F or DS L, P LL, VC OF , DR F , a nd A/D c onve rte r) Norma l: H SDD00026AEM 6 MN662785TBUC Symbol No. I/O Function 48 OUTL O L-c h a udio output 49 AVSS1 I Ground for a na log c irc uits 50 OUTR O R -c h a udio output 51 AVDD1 I P owe r supply for a na log c irc uits ( F or a udio output sta ge ) 52 F S EL I Te st pin 53 TMOD1 I 54 TMOD2 I P in mode se le c tion input 1 Norma l: L P in mode se le c tion input 2 Norma l: L 55 F LAG/S R MON1 O F la g signa l output / S e ria l monitor signa l output 1 ( Eva lua tion de dic a te d monitor) 56 IP F LAG/C LVS O C omma nd se le c tion ・Inte rpola tion fla g signa l output H: Inte rpola tion ・S pindle se rvo pha se sync signa l output H: C LV L: R ough se rvo 57 EXT0/ IS R DATA/ S R MON2 I/O C omma nd se le c tion ・ Expa nsion port 0 I/O ・ S e ria l a udio da ta input ( Exte rna l I/O mode ) 64fs ・ S e ria l monitor signa l output 2 ( Eva lua tion de dic a te d monitor) 58 EXT1/ ILR C K/ VDET/P C K I/O 59 EXT2/ IB C LK/EF M I/O C omma nd se le c tion ・ Expa nsion port 2 I/O ・ B it c loc k input ( Exte rna l I/O mode ) 64fS ・ EF M monitor signa l 60 TX O Digita l a udio inte rfa c e signa l output 61 MCLK I Mic roc ompute r c omma nd c loc k signa l input 62 MDATA I Mic roc ompute r c omma nd da ta signa l input 63 MLD I Mic roc ompute r c omma nd loa d signa l input 64 B LKC K/ DQS Y1 O ・B loc k c loc k signa l output ・C D-TEXT sync signa l output 65 S QC K/ B C LK1/ TXTC LK1 I/O ・External clock input for subcode Q register ・Bit clock output ・CD-TEXT data read clock input 1 66 S UB Q/ LR C K1/ TXTDAT1 O ・S ubc ode Q-da ta output ・L or R disc rimina tion signa l output H: L-c h a udio da ta L: R -c h a udio da ta ・C D-TEXT da ta output 1 ( R e fe r to Note in pa ge 3) ( F or a udio output sta ge ) ( R e fe r to Note in pa ge 3) Norma l: H ( Noise filte r is se le c te d by using a c omma nd.) C omma nd se le c tion ・ Expa nsion port 1 I/O ・ L or R disc rimina tion signa l input ( Exte rna l I/O mode ) H: L-c h a udio da ta L: R -c h a udio da ta ・ Vibra tion de te c tion fla g signa l output ・ P LL e xtra c tion c loc k output fPCK = 4.321 MHz ( Norma lspe e d pla yba c k) SDD00026AEM L：Loa d fBLKCK= 75 Hz ( Norma l-spe e d pla yba c k) fDQSY= 300 Hz ( Norma l-spe e d pla yba c k) 7 MN662785TBUC No. Symbol I/O 67 DMUTE/ S R DATA1 I/O 68 S TAT 69 NR S T Function ・ Muting input H：Mute ( Muting of OUTL, OUTR , a nd TX outputs) ・ S e ria l a udio da ta output O S ta tus signa l output ( C R C , R ES Y, C LVS , NTTS TOP , S QOK, F LAG6, S ENS E, NF LOC K, NTLOC K, B S S EL, ZDET, S UB Q da ta output, C D-TEXT da ta output, Anti-shoc k me mory c ontrolle r re a ding da ta , Disc rota tion spe e d da ta ) I R e se t input L：R e se t 70 S P P OL O 71 PMCK O 88.2-kHz clock signal output 72 SMCK O ・4.2336-MHz clock signal output ・8.4672-MHz clock signal output 73 SUBC/ SSYNC/ TXTDAT2/ SRDATA2 O ・Subcode output ・CD-TEXT data output ・Serial audio data output SBCK/ TXTCLK2/ LRCK2 I ・Subcode output clock input ・CD-TEXT data read clock input 3 ・L or R discrimination signal output (External output mode) H: L-ch audio data L: R-ch audio data 75 NCLDCK/ DQSY2/ BCLK2 O ・Frame sync signal output fCLDCK=7.35 kHz (Normal-speed playback) ・CD-TEXT output fDQSY =300 Hz (Normal-speed playback) ・Bit clock output 76 NTEST I Te st pin 77 X1 I Crystal oscillator input pin 78 X2 O Crystal oscillator output pin 79 DVDD1 I P owe r supply for digita l c irc uits 80 DVSS1 I Ground for digita l c irc uits 74 S pindle motor powe r c ontrol signa l output ( P C ) Norma l: H SDD00026AEM f＝33.8688 MHz f＝33.8688 MHz 8 MN662785TBUC 7. FUNCTION DESCRIPTION (Table of contents) ──────────── P10 ───────────────────── P 12 （１）List of commands vs. control items （２）List of microcomputer commands （３）Initial setting （４）Data setting for servos （５）Data setting for signal processing section （６）Data setting for anti-shock memory controller （７）Automatic adjustment P 13 P 14 P 18 P 19 P 46 P 55 P 60 7-2 I/O timing ─────────────────────────── P 62 7-0 Contents of functions amended from MN662780 7-1 Microcomputer interface （１）Subcode interface （２）Serial data output （３）Serial data input P 61 P 62 P 63 SDD00026AEM 9 MN662785TBUC 7-0 Contents of functions amended from MN662780 (1) Digital servo section ・ Focus and tracking servos' sampling frequency : 88.2 kHz ・ Timings of initial settings ・ Spindle forced acceleration/deceleration output level setting ・ KICK pulse level setting (KICK2) for servo pull-in operation abolished ・ Zero-cross reference brake mode abolished ・ Fixed noise rejection mode during braking operation of tracking ・ Software reset function added ・ Change of servo parameter exponent part format (FEXP, TEXP) (2) Digital filter (DF) and D/A converter (DAC) sections ・ DF and DAC sections operating clock selectable between normal-speed and 2x-speed modes ・ DF section 8x-oversampling operation ・ Low-voltage op amp ・ Change of low-band boost filter characteristics (Low band: ＋3 dB →＋4.5 dB) (3) Signal processing section ・ 33.8688-MHz system clock ・ Function to select a microcomputer interface input noise filter with a command ・ Clock selection function for microcomputer (4 MHz, 8 MHz) ・ Function to select current rate of PLL frequency comparison and phase comparison ・ Function to select output width when detecting 12T or 5T ・ Subcode Q data adding function in control of digital audio interface output when the anti-shock memory function is in use ・ Compatible with bilingual operation when anti-shock memory function is in use ・ Compatible with 2x-speed digital audio interface output ・ Muting of data output from anti-shock memory controller ・ Audio data 0 detection flag function (ZDET signal) SDD00026AEM 10 MN662785TBUC (4) Anti-shock memory controller (5) The whole system ・ Digital servo's D/A converter output abolished by PWM charge pump current output of FBAL, TBAL, and DSLF2 ・ No VREF pin ・ No DSLF2 pin ・ Serial input/output interfaces added ・ No PWMCK and TRVSTP pins ・ No peak detection circuit ・ No variable pitch function ・ CD-TEXT mode interface added ・ IPFLAG pin (pin 56) added ・ EFM signal output added ・ PCK signal output added ・ VDET signal output added ・ Added function to stop A/D converter operation with reference current shut-off command ・ Oscillation stop mode added ・ A/D converter reference voltage input pin (ADPVCC: pin 41) added ・ No CD-TEXT modes 1 and 3 SDD00026AEM 11 MN662785TBUC 7-1. Microcomputer interface Each mode can be set by inputting the 16-bit data (D15 to D0) and 8-bit command (B7 to B0) starting from the MSB in 3 inputs of MDATA, MCLK, and MLD at the timing as shown in Figure 7-1-1. MDATA D15 D14 D13 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 ∼ ∼ MCLK ∼ ∼ ∼ ∼ MSB LSB MLD Note）・ Data is determined at the "L" level of MLD. ・ MDATA, MCLK, and MLD are invalid while NRST is "L." ・ All commands are initialized by setting NRST to "L." ・ While MLD is set to "L," MCLK will be canceled if it rises. ・ Set 0 to any bit which is input through the MDATA input with no functional specification assigned to the bit. （Timing） MDATA B2 B1 B0 MCLK MLD 300 ns 300 ns 300 ns 300 ns min. min. min. min. Figure 7-1-1 SDD00026AEM 300 ns min. 500 ns 300 ns min. min. 5 µs max. 12 MN662785TBUC 7-1 (1) List of commands vs. control items Table 7-1-1 Command (HEX) (B7 to B0) Control Target Block 1× 4× 7× Spindle servo Various signal processing STAT output Signal processing section 8× 9× Anti-shock memory write command Anti-shock memory read command Anti-shock memory controller E× F× Focus, tracking, and traverse servos Optical servo Initial setting, automatic adjustment, and access section SDD00026AEM 13 MN662785TBUC 7-1 (2) List of microcomputer commands Set 0 to any bit which is indicated by X in the following list of commands with no functional specification assigned to the bit. (1) Commands for signal processing section No data length setting is required wherever ─ appears in the following table. Table 7-1-2 (1) Control target Spindle Control 1 Various signal processing control Data length Command (B7 to B0) ――― ――― ――― ――― ――― ――― ０００１ ０００１ ０００１ ０００１ ０００１ ０００１ Ｘ０ＸＸ Ｘ１ＸＸ ＸＸ００ ＸＸ０１ ＸＸ１０ ＸＸ１１ 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０１００ ０００１ ００１０ ０１００ ０１０１ ０１１０ １００１ １０１０ １０１１ １１００ １１０１ １１１０ Function (＊：Setting at reset) Symbol Reference page TTOFF ＊ Turntable OFF Turntable ON TTO N ＊ Free-running STOP Acceleration ACC Deceleration BRAKE Normal play PLAY Audio control Digital audio interface control Attenuation control Spindle control PWM output control (Optical servo system) Playback speed control Dropout control PLL control I/O control 1 DSL unbalance compensation control I/O control 2 SDD00026AEM 46 47 48 48 49 50 50 51 52 52 53 14 MN662785TBUC Table 7-1-2 (2) Control target Data length ――― STAT pin output ――― ――― ――― ――― 3 bits ――― ――― ――― ――― ――― ――― ――― Command (B7 to B0) Symbol Function (＊：Setting at reset) ＊ STAT output CRC STAT output RESY STAT output CLVS STAT output NTTSTOP STAT output SQOK STAT output switching STAT output BSSEL STAT output FCLV STAT output SSTAT STAT output SUBQ (SQCK sync) STAT output SUBQ (MCLK sync) STAT output ZDET (Zero data detection) STAT output SPEED (Disc rotation speed) ０１１１ ００００ ０１１１ ０００１ ０１１１ ００１０ ０１１１ ００１１ ０１１１ ０１００ ０１１１ ０１０１ ０１１１ ０１１０ ０１１１ ０１１１ ０１１１ １０００ ０１１１ １００１ ０１１１ １０１０ ０１１１ １０１１ ０１１１ １１１０ (2) Commands for anti-shock memory controller No data length setting is required wherever ─ appears in the following table. Reference page 54 54 54 54 54 54 54 54 54 54 54 54 54 Table 7-1-2 (3) Control target Data length Command (B7 to B0) Write command 8 bits 4 bits 4 bits 8 bits 8 bits ――― １０００ ００００ １０００ ０００１ １０００ ００１０ １０００ ０１０１ １０００ ０１１０ １０００ ０１１１ Memory system command Expansion I/O port I/O setting Expansion I/O port output data setting Option setting Option setting TX Q-data input 55 55 56 56 56 57 Read command ――― ――― ――― １００１ ００００ １００１ ０００１ １００１ ００１０ 58 58 59 ――― １００１ ００１１ Status 1 reading (Read data length: 8 bits) Status 2 reading (Read data length: 8 bits) Remaining enabled data check (Read data length: 16 bits) Expansion I/O port input data setting (Read data length: 8 bits) Symbol Function (＊：Setting at reset) SDD00026AEM Reference page 59 15 MN662785TBUC (3) Commands for optical servo section No data length setting is required wherever ─ appears in the following table. Table 7-1-2 (4) Control target Optical servo Data length Command (B7 to B0) Symbol Reference page OFT Unchanged TV F TV R TV P ＊ Traverse stop Reserved Traverse forward feed Traverse reverse feed Traverse play １１１１ ００００ １１１１ ０００１ １１１１ ００１１ ACA KICK TCNT Stopping access operation Kick Track count move NACEND NACEND NACEND 44 44 16 bits 8 bits １１１１ ００１０ １１１１ ０１００ DTMS Data write Data read DTSM N W TEN D DATA 19 20 ――― ――― １１１１ ０１０１ １１１１ ０１１０ SYS １１１１ ０１１１ １１１１ １０００ １１１１ １００１ １１１１ １０１０ １１１１ １０１１ １１１１ １１００ １１１１ １１０１ １１１１ １１１０ １１１１ １１１１ ABC1 ADA AOC STB ――― ――― ――― ――― ――― １１１０ １０００ １１１０ １００１ １１１０ １０１０ １１１０ １０１１ １１１０ １１ＸＸ TV S ――― 16 bits 16 bits Data setting Initial setting Access SENSE signal ＊ Standby Reserved Disc detection Fo ON, Tr OFF Fo ON, Tr ON Reserved Reserved ――― １１１０ ００００ ――― １１１０ ０００１ ――― １１１０ ００１０ ――― １１１０ ００１１ ――― １１１０ ０１０Ｘ ――― １１１０ ０１１０ ――― １１１０ ０１１１ Traverse servo Function (＊：Setting at reset) Automatic ――― adjust ――― ment ――― ――― ――― ――― ――― ――― ――― DDT TO F PLY FESL FESL OFT Unchanged Unchanged Unchanged Await initialization cancel command Reserved Focus balance adjustment Stopping automatic adjustment Offset adjustment (focus, tracking) Reserved ABC2 Tracking balance adjustment Focus rough gain adjustment AGC1 Tracking rough gain adjustment AGC2 Focus fine gain adjustment FAGC Tracking fine gain adjustment TA G C SDD00026AEM 18 NAJEND NAJEND NAJEND 60 60 60 NAJEND NAJEND NAJEND NAJEND NAJEND 60 60 60 60 60 16 MN662785TBUC ・SENSE signal SENSE signal can be monitored through STAT pin. The meaning of SENSE signal varies with the input command. The meanings are described below. OFT Off-track input signal is output as it is. FESL It is set to "H" when the absolute value of the focus error signal amplitude exceeds 30 LSBs by executing the disc detection command. NACEND It is set to "L" when the access terminates and the pull-in operation of the tracking servo starts. NAJEND It is set to "L" when automatic adjustment terminates. NWTEND It is set to "L" when data write terminates normally. DATA The contents of the RAM of the specified address is output beginning with MSB by inputting MCLK a minimum of 25 µs after MLD is set to "L" with the data read command, DTSM, sent out for data reading. Refer to Figure 7-1-4. MDATA Disc detection Fo ON, Tr ON Fo fine AGC KICK MLD FESL OFT NAJEND NACEND SENSE (STAT pin) End of automatic adjustment End of KICK Figure 7-1-2 Switching of SENSE output SDD00026AEM 17 MN662785TBUC 7-1 (3) Initial setting After clearing NRST, the SENSE signal is set to "H" and the system is in the standby status for the SYS command. After 75-ms continuous standby status for the SYS command, the STANDBY mode starts. If the SYS command is sent during the period of 75-ms continuous standby status for the SYS command, however, the SENSE signal is set to "L" and the STANDBY mode starts immediately. In the STANDBY mode, the system is ready for receiving the DTMS and DTSM commands. Table 7-1-3 Data Address (HEX) Command (HEX) Function (D7 to D0) (A7 to A0) (B7 to B0) D7 D6 D5 D4 D3 D2 D1D0 XX Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ F5 SYS command 75 ms max. NRST SENSE (STATpin) SYS MDATA Other than SYS MLD Figure 7-1-3 Timing chart in initial setting SDD00026AEM 18 MN662785TBUC 7-1 (4) Data setting for servos [1] Data write (DTMS) Various features can be achieved by writing various characteristics of the optical servo system from an external microcomputer to this IC. DTMS command is used to write the data such as servo parameters. (Application) (A) Setting of automatic adjustment value (B) Setting of the optical servo loop characteristics including the characteristics for anti-vibration (C) Setting of gain crossover for the optical servo loop (D) Mode selection for anti-vibration (E) Various system settings (F) Various settings for optical servo system (G) Access command setting (MDATA format) D７ D6 D５ D４ D３ D２ D１ D０ : Data : Address (Label specified) A７ A６ A５ A４ A３ A２ A１ A０ １ １ １ １ ０ ０ １ ０ : Command (DTMS) Note) ・Use the DTMS command in the STANDBY or PLAY mode. ・If you write data successively, wait at least 25 µs before each data writing so that the microcomputer finishes DSP processing and becomes ready for writing next data. SDD00026AEM 19 MN662785TBUC [2] Data read (DTSM) ・This IC can read out the parameters such as automatic adjustment results of the optical servo with the DTSM command. (MDATA format) A7 A6 A5 A4 A3 A2 A1 A0 ：Address (Label specified) １ １ １ １ ０ １ ０ ０ ：Command (DTSM) (Data output format) Input an address and command, and after a lapse of at least 25 µs since setting MLD to "H" from "L," input MCLK, thus enabling to read data from STAT pin. (SENSE output) MDATA DTSM MLD MCLK SENSE (STAT pin) Indefinite Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Min. 25 µs Figure 7-1-4 Timing chart for reading data Note) Perform either in the STANDBY or PLAY mode. SDD00026AEM 20 MN662785TBUC (List of DTMS/DTSM addresses) Table 7-1-4 (1) Address (HEX) (A7 to A0) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 16 17 18 19 1A 1B 1C 1D 1E 1F Label FG0 FEXP0 FBAL FOFS TG 0 TEXP0 TBAL TOFS FC FR TC TR FC2 FR2 TC2 TR2 GSET VSET SET0 SET1 SET2 FES TES CRAM2 SD KS TV G CRAM3 CRAM4 SET3 DED0 Application Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus balance automatic adjustment value Focus offset automatic adjustment value Tracking gain automatic adjustment value in normal-speed mode (for setting use) Tracking gain automatic adjustment value in normal-speed mode (for setting use) Tracking balance automatic adjustment value Tracking offset automatic adjustment value Focus phase compensation constant Focus low-band compensation constant Tracking phase compensation constant Tracking low-band compensation constant Focus phase compensation constant at vibration Focus low-band compensation constant at vibration Tracking phase compensation constant at vibration Tracking low-band compensation constant at vibration Gain crossover setting Mode selection for anti-vibration System settings System settings System settings Focus gain disturbance amplitude Tracking gain disturbance amplitude Focus search amplitude Search direction Kick speed / Kick brake timing Traverse gain constant in tracking brake operation Fail-safe value for tracking servo Tracking balance disturbance adjustment value System settings Traverse drive dead-zone SDD00026AEM Reference page 23 23 23 23 23 23 23 23 25 25 25 25 25 25 25 25 27 28 30 31 32 23 23 38 38 39 40 39 39 33 41 21 MN662785TBUC Table 7-1-4 (2) Address (HEX) (A7 to A0) Label 2B 2C 2D 2E 2F 35 36 37 39 3A 3B 3C 3D 3E 3F 40 49 4A 4B ECM SVOFS FG2 FEXP2 SPG0 TG2 TEXP2 TRVG0 GLF1 GLF2 GLF3 GLF4 GLT1 GLT2 GLT3 GLT4 SETKC SETTB KCCNT 6C 6D 78 79 7B 7C 7D 80 81 AA FMAX FMIN KICK TRV VSLT SETV1 SETV2 − − − Application Spindle forced acceleration/deceleration output level setting Spindle shaft loss compensation output level setting Focus gain constant mantissa part at vibration (for setting use) Focus gain constant exponent part at vibration (for setting use) Spindle gain setting Tracking gain constant mantissa part at vibration (for setting use) Tracking gain constant exponent part at vibration (for setting use) Traverse gain setting Focus gain constant upper limit mantissa part Focus gain constant upper limit exponent part Focus gain constant lower limit mantissa part Focus gain constant lower limit exponent part Tracking gain constant upper limit mantissa part Tracking gain constant upper limit exponent part Tracking gain constant lower limit mantissa part Tracking gain constant lower limit exponent part Track count noise elimination width System settings Inverted pulse width with tracking brake and servo control turned on Initial accelerating time with tracking brake turned on FE signal maximum value (8-bit 2's complement) FE signal minimum value (8-bit 2's complement) KICK output level Traverse output level Vibration detecting level mantissa part Soft VDET parameter setting 1 Soft VDET parameter setting 2 Focus and tracking gains setting for normal gain Focus and tracking gains setting for forced gain-up Software reset Reference page 45 45 29 29 45 29 29 43 43 43 43 43 43 43 43 43 41 36 42 42 42 42 35 34 34 37 37 37 ※ Do not write illegal data in any of the above addresses, otherwise the existing data in the address is overwritten and the operation of this IC is not guaranteed. SDD00026AEM 22 MN662785TBUC (A) Setting of automatic adjustment value FG0 (Focus gain mantissa part) FEXP0 (Focus gain exponent part) FBAL (Focus balance adjustment value) (Focus offset adjustment value) FOFS (Disturbance amplitude FES in focus gain adjustment) (Disturbance amplitude TES in tracking gain adjustment) , , , , TG0 TEXP0 TBAL TOFS (Tracking gain mantissa part) (Tracking gain exponent part) (Tracking balance adjustment value) (Tracking offset adjustment value) Table 7-1-4 (3) Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0) Data (D7 to D0) D7 D6 D5 D4 D3 D2 D1 D0 00 D7 D6 D5 D4 D3 D2 D1 D0 01 D7 D6 D5 D4 D3 D2 D1 D0 02 D7 D6 D5 D4 D3 D2 D1 D0 03 D7 D6 D5 D4 D3 D2 D1 D0 04 D7 D6 D5 D4 D3 D2 D1 D0 05 D7 D6 D5 D4 D3 D2 D1 D0 06 D7 D6 D5 D4 D3 D2 D1 D0 07 D7 D6 D5 D4 D3 D2 D1 D0 16 D7 D6 D5 D4 D3 D2 D1 D0 17 F2 Function Focus gain constant (FG0) (8-bit mantissa) (1 to 255) Focus gain constant (FEXP0) (8-bit exponent) (0 to 7) (Note) (Focus gain constant = mantissa / 28-FEXP0) Focus balance constant (FBAL) (8-bit 2' s complement) (−128 to +127) Focus offset constant (FOFS) (8-bit 2' s complement) (−128 to +127) Tracking gain constant (TG0) (8-bit mantissa) (1 to 255) Tracking gain constant (TEXP0) (8-bit exponent) (0 to 7) (Note) (Tracking gain constant = mantissa / 28-TEXP0) Tracking balance constant (TBAL) (8-bit 2' s complement) (−128 to +127) Tracking offset constant (TOFS) (8-bit 2' s complement) (−128 to +127) Disturbance amplitude in focus gain adjustment (FES) (1 to 127) Disturbance amplitude in tracking gain adjustment (TES) (1 to 127) Setting at reset 202 2 0 0 150 1 0 0 85 85 (Note) The operation may fluctuate when FEXP0 or TEXP0 setting is 5 or more. FEXP0/TEXP0 corresponding setting table MN662783 128 64 32 16 MN662785 1 2 3 4 SDD00026AEM 23 MN662785TBUC (B) Setting of the optical servo characteristics including the characteristics for anti-vibration ・Gain constant Focus gain mantissa part FG Tracking gain mantissa part Focus gain exponent part FEXP Tracking gain exponent part TG TEXP ・Phase compensation and low-band compensation constant Focus phase compensation constant FC Tracking phase compensation constant TC Focus low-band compensation constant FR Tracking low-band compensation constant TR The above four constants can be set by writing 8-bit data (0 to 127) directly with the microcomputer command. Configuration K + Z -1 R − ＋ ＋ Ｘ Z -N + +＋ − ＋ C G Ｙ ・fs of the focus system: 88.2 kHz ・fs of the tracking system: 88.2 kHz ・fs of the filter for low-band compensation: 44.1 kHz 1 −N G (Z) ＝G −1 ・R ＋ (1−C・Z ) 1−Z ｛ G= R= TG or 28-FEXP 28-TEXP TR 2 15 FG or C= ｝ TC or 128 FC 128 FR 2 15 K=1 N in Z−N can be replaced with : 2 or 1 (by setting bit 1 of SET0) in case of the focus system. 1 in case of the tracking system. SDD00026AEM 24 MN662785TBUC ・Setting of loop filter constants Table 7-1-4 (4) Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) Data (D7 to D0) D7 D6 D5 D4 D3 D2 D1 D0 08 D7 D6 D5 D4 D3 D2 D1 D0 09 D7 D6 D5 D4 D3 D2 D1 D0 0A D7 D6 D5 D4 D3 D2 D1 D0 0B D7 D6 D5 D4 D3 D2 D1 D0 0C D7 D6 D5 D4 D3 D2 D1 D0 0D D7 D6 D5 D4 D3 D2 D1 D0 0E D7 D6 D5 D4 D3 D2 D1 D0 0F F2 Function Setting at reset Focus phase compensation constant : 117 FC (8 bits) (1 to 127) Focus low-band compensation constant : 64 FR (8 bits) (1 to 127) Tracking phase compensation constant: 122 TC (8 bits) (1 to 127) Tracking low-band compensation constant : 64 TR (8 bits) (1 to 127) Focus phase compensation constant at 117 vibration : FC2 (8 bits) (1 to 127) Focus low-band compensation constant at 64 vibration : FR2 (8 bits) (1 to 127) Tracking phase compensation constant at 122 vibration : TC2 (8 bits) (1 to 127) Tracking low-band compensation constant at 64 vibration : TR2 (8 bits) (1 to 127) SDD00026AEM 25 MN662785TBUC ・Setting of the traverse filter Configuration Ｋ Ｚ-1 + Low-band Component of TE Ｒ + + Dead-Zone Amp + Traverse filter sampling frequency＝ 11.02 kHz -14 K=1 - 2 -10 R= 2 ・There are three types of dead-zone amps; type A, type B, and type C. They can be selected by setting SET2. The dead-zone width can be specified by setting DED0. SDD00026AEM 26 MN662785TBUC (C) Setting of gain crossover for optical servo loop Before performing focus and tracking automatic adjustments, gain crossover after automatic adjustment can be determined by writing data to the label name GSET (address: 10h) according to the table below. In the automatic gain adjustment, disturbance is input to the servo loop, and gain is increased or decreased according to the GSET setting after adjusting the gain so that the feedback gain at the disturbance frequency becomes 0 dB (gain crossover is equal to the disturbance frequency). (Setting for focus system) Data (D7 to D0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D3 D2 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Table 7-1-4 (5) Address (HEX) Command (HEX) (A7 to A0) D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10 F2 (Setting for tracking system) Data (D7 to D0) D7 D6 D5 D4 Ｘ Ｘ Ｘ Ｘ 0 1 1 1 ＸＸＸＸ 0 1 1 0 ＸＸＸＸ 0 1 0 1 ＸＸＸＸ 0 1 0 0 ＸＸＸＸ 0 0 1 1 ＸＸＸＸ 0 0 1 0 ＸＸＸＸ 0 0 0 1 ＸＸＸＸ 0 0 0 0 ＸＸＸＸ 1 1 1 1 ＸＸＸＸ 1 1 1 0 ＸＸＸＸ 1 1 0 1 ＸＸＸＸ 1 1 0 0 ＸＸＸＸ 1 0 1 1 ＸＸＸＸ 1 0 1 0 ＸＸＸＸ 1 0 0 1 ＸＸＸＸ 1 0 0 0 ＸＸＸＸ Function (＊ : Setting at reset) Focus gain at the disturbance frequency of 750 Hz Approx. value： −3.92 dB Approx. value： −3.36 dB Approx. value： −2.80 dB Approx. value： −2.24 dB Approx. value： −1.68 dB Approx. value： −1.12 dB Approx. value： −0.56 dB ＊ Approx. value： 0 dB Approx. value： 1.05 dB Approx. value： 2.11 dB Approx. value： 3.16 dB Approx. value： 4.21 dB Approx. value： 5.27 dB Approx. value： 6.32 dB Approx. value： 7.37 dB Approx. value： 8.43 dB Table 7-1-4 (6) Address (HEX) (A7 to A0) Command (HEX) 10 F2 SDD00026AEM Function (＊ : Setting at reset) Tracking gain at the disturbance frequency of 1 kHz Approx. value： −3.92 dB Approx. value： −3.36 dB Approx. value： −2.80 dB Approx. value： −2.24 dB Approx. value： −1.68 dB Approx. value： −1.12 dB Approx. value： −0.56 dB ＊ Approx. value： 0 dB Approx. value： 1.05 dB Approx. value： 2.11 dB Approx. value： 3.16 dB Approx. value： 4.21 dB Approx. value： 5.27 dB Approx. value： 6.32 dB Approx. value： 7.37 dB Approx. value： 8.43 dB 27 MN662785TBUC (D) Setting for anti-vibration (VSET) The gain-up amount and gain-up time can be set when VDET is set to "H." (VDET can be monitored through the EXT1 pin. Refer to 7-1 (5) (I) for details.) Table 7-1-4 (7) Address (HEX) Command (HEX) (B7 to B0) (A7 to A0) Data (D7 to D0) Function (＊ : Setting at reset) Setting of the focus gain-up amount at vibration Scale factor ：× 1.0 (0 dB) Scale factor ：× 1.125 (＋1.0 dB) Scale factor ：× 1.25 (＋1.9 dB) Scale factor ：× 1.375 (＋2.8 dB) ＊ Scale factor ：× 1.5 (＋3.5 dB) Scale factor ：× 1.625 (＋4.2 dB) Scale factor ：× 1.75 (＋4.9 dB) Scale factor ：× 2.0 (＋6.0 dB) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D5 Ｘ 0 Ｘ 0 Ｘ 0 Ｘ 0 Ｘ 1 Ｘ 1 Ｘ 1 Ｘ 1 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Setting of the tracking gain-up amount at vibration Scale factor ：× 1.0 (0 dB) Scale factor ：× 1.125 (＋1.0 dB) Scale factor ：× 1.25 (＋1.9 dB) Scale factor ：× 1.375 (＋2.8 dB) Scale factor ：× 1.5 (＋3.5 dB) Scale factor ：× 1.625 (＋4.2 dB) Scale factor ：× 1.75 (＋4.9 dB) ＊ Scale factor ：× 2.0 (＋6.0 dB) D7 D6 Ｘ Ｘ Ｘ Ｘ 0 0 Ｘ Ｘ Ｘ Ｘ 0 1 Ｘ Ｘ Ｘ Ｘ 1 0 Ｘ Ｘ Ｘ Ｘ 1 1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Setting of the gain-up time at vibration Time ： 23.2 ms Time ： 46.4 ms Time ： 92.9 ms ＊ Time ：185.8 ms Note) 11 F2 The gain-up amount set by VSET is valid only when FC2 or FR2 for the focus system or TC2 or TR2 for the tracking system is written after VSET setting. (No operation is performed to set servo parameters in the anti-vibration mode only by VSET setting.) SDD00026AEM 28 MN662785TBUC The gain values can be overwritten when VDET is set to "H." Data (D7 to D0) Address ( H EX ) (A7 to A0) D7 D6 D5 D4 D3 D2 D1D0 2D D7 D6 D5 D4 D3 D2 D1D0 2E D7 D6 D5 D4 D3 D2 D1D0 35 D7 D6 D5 D4 D3 D2 D1D0 36 Command ( H EX ) (B7 to B0) F2 Table 7-1-4 (8) Function Focus gain constant at vibration (FG2) (8-bit mantissa) (1 to 255) Focus gain constant at vibration (FEXP2) (8-bit exponent) (1 to 7) (Focus gain constant = mantissa / 28-FEXP2) Tracking gain constant at vibration (TG2) (8-bit mantissa) (1 to 255) Tracking gain constant at vibration (TEXP2) (8-bit exponent) (1 to 7) (Tracking gain constant = mantissa / 28-TEXP2) Setting at reset 202 2 150 1 Note) Be aware that the gain set with VSET applies at the time of fine gain adjustment or writing data to the FC2, FR2, TC2, or TR2. SDD00026AEM 29 MN662785TBUC (E) System settings (E)-1 SET0 setting Address (HEX) Command (HEX) (A7 to A0) (B7 to B0) Data (D7 to D0) Ｘ Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D5 D4 0 0 0 1 1 0 1 1 D1 Ｘ Ｘ 0 1 Ｘ Ｘ 1 1 D3 D2 0 0 0 1 1 0 1 1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ 12 F2 Table 7-1-4 (9) Function (＊ : Setting at reset) Setting the number of Fo loop filter delay stages ＊ 2nd-order (Z-2) 1st-order (Z-1) Setting of forced brake operation time OFF ON (5.8 ms) ON (11.6 ms) ＊ ON (23.2 ms) 1 1 1 1 Setting of convergence gain during tracking balance adjustment ×1/8192 ＊ ×1/4096 ×1/2048 ×1/1024 1 1 1 1 D6 Ｘ 0 Ｘ Ｘ Ｘ 1 Ｘ Ｘ Ｘ Ｘ Ｘ 1 Ｘ Ｘ Ｘ 1 Tracking balance adjustment output ＊Conventional method Inverted polarity D7 0 Ｘ Ｘ Ｘ 1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ 1 Ｘ Ｘ Ｘ 1 TVD output smoothing OFF ＊ ON TVD output Example of the TVD intermittent drive is as follows. Smoothing OFF TVD Smoothing ON TVD 1.45 ms 1.45 ms SDD00026AEM 1.45 ms 1.45 ms 30 MN662785TBUC (E)-2 SET1 setting Table 7-1-4 (10) Data (D7 to D0) D0 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) 13 F2 Function (＊ : Setting at reset) TVD output at the time of kick pulse output in the traverse stop state TVD output ＊No TVD output D1 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Pull-in method when turning focus on from off Conventional method ＊High-speed pull-in D2 Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ High-speed kickback ON/OFF ＊ON OFF D4 Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ Ｘ Ｘ Focus offset adjustment method With vibration ＊Without vibration D5 Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ Ｘ Ｘ Ｘ Focus offset adjustment method ＋direction (Same as MN66271) ＊−direction D6 Ｘ０ Ｘ０ Ｘ１ Ｘ１ Wait time after TCNT ＊ 50 ms 100 ms 0 ms 10 ms D3 Ｘ Ｘ ０ Ｘ Ｘ １ Ｘ Ｘ ０ Ｘ Ｘ １ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ D7 ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ DAC output limiter (FABC, TABC) Note) OFF ＊ON Note) It is recommended to turn off the high-speed kickback function while the anti-shock memory control function is in use. SDD00026AEM 31 MN662785TBUC (E)-3 SET2 setting Table 7-1-4 (11) Data (D7 to D0) D1 D0 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ １ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Address (HEX) (A7 to A0) Command (HEX) (B7 to B0) 14 F2 Function (＊ : Setting at reset) Traverse dead-zone amp Normal (Type A) ＊ ＋ side only (Type B) − side only (Type C) D2 Ｘ０ＸＸ Ｘ１ＸＸ Tracking offset adjustment wait time None ＊ 30 ms D3 Convergence judgement condition for tracking balance adjustment ＊ ±2 LSBs at TBAL output stage ±1 LSB at TE input stage ０ ＸＸＸ １ ＸＸＸ D5D4 ＸＸ００ ＸＸＸＸ Ｘ Ｘ ０ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ ０ Ｘ Ｘ Ｘ Ｘ ＸＸ１１ ＸＸＸＸ Focus balance adjustment convergence gain ＊ 1／8 1／4 1／32 1／16 D6 Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Disc detection, focus rough gain adjustment frequency 5.4 Hz ＊ 2.6 Hz D7 ０ＸＸＸ ＸＸＸＸ １ＸＸＸ ＸＸＸＸ Traverse intermittent drive ＊ Output enabled Output disabled DED0×2 D ED 0 Figure 1 Traverse dead-zone amp Type A Figure 2 Traverse dead-zone amp Type B DED0×2 Figure 3 Traverse dead-zone amp Type C Note) Refer to 7-1 (4) (F)-6 for the DED0 setting. SDD00026AEM 32 MN662785TBUC (E)-4 SET3 setting Table 7-1-4 (12) Data (D7 to D0) Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) D1 1E Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ ０ F2 Function (＊ : Setting at reset) Focus balance adjustment convergence condition ＊ ±15 LSBs ±7 LSBs D2 Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ １ Ｘ ０ Cancellation of focus balance adjustment Reset to the initial value at the start of adjustment ＊ The adjusting value is on hold D3 Ｘ Ｘ Ｘ Ｘ ０ Ｘ Ｘ ０ Ｘ Ｘ Ｘ Ｘ １ Ｘ Ｘ ０ Tracking rough gain adjustment time ＊ 134 ms 319 ms D4 Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ ０ Ｘ Ｘ Ｘ １ Ｘ Ｘ Ｘ ０ Focus search mode ＊ Conventional mode Amplitude: 1/4 D6 Ｘ ０ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Ｘ １ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Focus balance adjustment output ＊ Positive polarity (Conventional mode) Negative polarity D7 ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ Focus search frequency 1.3 Hz ＊ 2.6 Hz SDD00026AEM 33 MN662785TBUC (E)-5 Setting of soft VDET Table 7-1-4 (13) (Setting of vibration detection bandpass filter constant) Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0) Data (D7 to D0) 7C F2 Setting of HPF constant A SETV1〔D3 to D0〕 (0 to 7) Vibration detection level exponent part n setting SETV1〔D7 to D4〕 (0 to 7) Ｘ Ｘ Ｘ Ｘ D3 D2 D1 D0 D7 D6 D5 D4 Ｘ Ｘ Ｘ Ｘ 7D Ｘ Ｘ Ｘ Ｘ D3 D2 D1 D0 Setting at reset Function D7 D6 D5 D4 Ｘ Ｘ Ｘ Ｘ 3 1 Setting of LPF 2nd stage constant C SETV2〔D3 to D0〕 (0 to 7) 5 Setting of LPF 1st stage constant B SETV2〔D7 to D4〕 (0 to 7) 5 ＊ See next page for the setting of vibration detection level. ×1 / 2 ＋ TRE ＋ ＋ − Ｚ ＋ -1 ＋ ＋ Ｚ -1 ＋ ＋ Ｚ -1 − Ｚ Vibration detection signal (VDET) -1 Detection level A 1-2 / 256 HPF Ｂ 1-2 / 256 Ｃ 1-2 / 256 LPF 1st stage LPF 2nd stage ＊ Sampling frequency for filter arithmetic operation: 11.02 kHz SDD00026AEM 34 MN662785TBUC (Setting of vibration detection level) Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0) Data (D7 to D0) 1 D6 D5 D4 D3 D2 D1 D0 7B F2 Table 7-1-4 (14) Setting at reset Function Setting of VDET detecting TE threshold level (Mantissa part) VSLT (128 to 255) 230 Vibration detection level TE Vibration detection level : ±VSLT×2n 0 n=SETV1〔D7 to D4〕 VDET SDD00026AEM 35 MN662785TBUC (E)-6 SETTB setting Table 7-1-4 (15) Address Command Data ( H EX ) (HEX) Function (＊ : Setting at reset) (D7 to D0) (A7 to A0) (B7 to B0) D1 ０ Ｘ ０ Ｘ Ｘ ０ ０ Ｘ ０Ｘ０Ｘ Ｘ ０１Ｘ ０Ｘ０Ｘ ０Ｘ０Ｘ D3 ００ＸＸ １０ＸＸ D6 ０００Ｘ ０１０Ｘ Ｘ０ＸＸ Ｘ０ＸＸ 4A F2 Low-band compensation during tracking brake operation Ye s ＊ No DO countermeasure during KICK operation No ＊ Ye s Hunting countermeasure for focus balance adjustment No ＊ Ye s SDD00026AEM 36 MN662785TBUC (E)-7 Forced gain-up setting The IC can be in forced gain-up mode by accessing the data in 81h address. This mode is reset by accessing the data in 80h address. Table 7-1-4 (16) Data (D7 to D0) Address (HEX) (A7 to A0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ 81 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ 80 Command (HEX) (B7 to B0) F2 Function Focus / tracking forced gain-up setting (Data is disabled.) Focus / tracking normal gain (Data is disabled.) Note) ・The status of the VDET can be monitored through the EXT1 pin. For details, refer to 7-1 (5) (I). ・Sending a fine gain adjustment command resets the gain to the normal value. (E)-8 Software reset Accessing the data in AAh address initializes servo processing. (DSP processing starts from the top address.) Table 7-1-4 (17) Data (D7 to D0) Address (HEX) (A7 to A0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ A A Command (HEX) (B7 to B0) F2 Function Software reset (Data is disabled.) Note) Only the digital servo section is reset in the software reset operation. SDD00026AEM 37 MN662785TBUC (F) Settings for optical servo system (F)-1 Focus search setting Address (HEX) Command (HEX) (B7 to B0) (A7 to A0) Data (D7 to D0) 0 D6 D5 D4 D3 D2 D1 D0 18 D0 Ｘ Ｘ 0 Ｘ Ｘ 1 19 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Table 7-1-4 (18) F2 Function Setting at reset Focus search amplitude (CRAM2) setting 8-bit data (p-p) (40 to 127) 96 Focus search/disc detection direction (SD) settin g *FOD decrement 0 FOD increment Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D2 0 ＸＸ 1 ＸＸ Max./Min. FE value teaching during focus search *ON OFF Note) In focus search/disc detection direction setting, a value of SD will change automatically according to execution of a focus search/disc detection. Consequently, the values written by initial setting and DTMS may have changed when they are read out with DTSM. If you want to perform a focus search/disc detection from the same direction every time, it is necessary to set with DTMS every time before the focus search/disc detection. (Set D0 of SD only.) Check the value of SD with DTSM in the writing operation of SD, and confirm that only the value of set bit of D0 has changed. Note) There will be no focus pull-in operation during the first excitation period (between the first peak and second peak of triangular FOD output) of the IC in focus search operation right after the system starts. The teaching of the maximum and minimum values (FMAX and FMIN) of the FE signal will be, however, conducted. The focus will be pulled in when the S-shape signal is detected after the first excitation period. Once the focus is pulled in, the servo DSP automatically sets SD D2 to 1. Then the focus will be pulled in when the S-curve signal is detected after the first peak of excitation. After offset and focus balance adjustments, SD D2 will be automatically set to 0 and the teaching of FMAX and FMIN will be conducted again. SDD00026AEM 38 MN662785TBUC (F)-2 Setting of tracking servo fail-safe value (CRAM3) Address Command (HEX) Data (HEX) (B7 to B0) (D7 to D0) (A7 to A0) 0 D6 D5 D4 D3 D2 D1 D0 1C F2 Table 7-1-4 (19) Function Fail-safe value clip level 8-bit data (0 to 127) Setting at reset 36 Low-band component of drive output in the tracking brake mode is clipped at the specified value. (F)-3 Setting of disturbance amplitude (CRAM4) in tracking balance adjustment mode Table 7-1-4 (20) Address Command (HEX) Data Setting (HEX) Function (B7 to B0) (D7 to D0) at reset (A7 to A0) 0 D6 D5 D4 D3 D2 D1 D0 1D F2 SDD00026AEM Disturbance amplitude (one side) 8-bit data (0 to 127) Amplitude of the disturbance waves injected in the tracking balance adjustment mode is set. Actual disturbance amplitude is 1/8×CRAM4. 36 39 MN662785TBUC (F)-4 KICK setting Address Command (HEX) Data (HEX) (D7 to D0) (B7 to B0) (A7 to A0) Ｘ Ｘ Ｘ Ｘ D3 D2 D1 D0 F2 1A Table 7-1-4 (21) Setting at reset Function KICK speed (KS) setting 4-bit data (6 to 15) KICK brake timing (OFDE) setting 4-bit data (0 to 15) D7 D6 D5 D4 Ｘ Ｘ Ｘ Ｘ 6 0 ・TE cycle in the speed control mode is determined by the KICK speed setting. KS (D3 to D0)×TS TS : 11.3 ms TE ・KICK brake output timing delay time is set in the KICK brake timing setting. (1 count＝TS delay) Setting value＝0: No delay ① When OFT is turned to "L" before reaching a position of 1/4 track OFT ② When OFT is turned to "L" after passing the position of 1/4 track 1/4 track TE OFT TE Delay Delay KICK KICK Brake SDD00026AEM Brake 40 MN662785TBUC (F)-5 Traverse drive constant in tracking brake (TVG) Data (D7 to D0) Ｘ Ｘ Ｘ Ｘ D 3 D2 D 1 D 0 Address Command (HEX) (HEX) (A7 to A0) (B7 to B0) 1B Table 7-1-4 (22) Traverse drive constant TVG (1 to 15) Only in the tracking brake, traverse will be driven with the traverse error multiplied by the specified constant. F2 (F)-6 Traverse drive dead zone setting (DED0) Data (D7 to D0) 0 D6 D5 D4 D3 D2 D1 D0 15 Table 7-1-4 (23) Address Command (HEX) (HEX) (A7 to A0) (B7 to B0) 1F Setting at reset Function Setting at reset Function Traverse drive dead zone setting (one side) F2 112 DED0 (0 to 127) (F)-7 TE noise rejection width setting at track count (SETKC) Data (D7 to D0) 0 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) (HEX) (A7 to A0) (B7 to B0) 49 F2 Table 7-1-4 (24) Function Setting at reset TE noise rejection width setting at track count 3 SETKC (0 to 127) TE Ignored SETKC SETKC SDD00026AEM ※ When the TE slope is inverted and reaches the level of the SETKC, it is regarded that the TE slope has actually changed. 41 MN662785TBUC (F)-8 KICK pulse width setting (KCCNT) Table 7-1-4 (25) Data (D7 to D0) Address (HEX) (A7 to A0) Command (HEX) (B7 to B0) D7 D6 D5 D4 Ｘ Ｘ Ｘ Ｘ 4B F2 Ｘ Ｘ Ｘ Ｘ D3 D2 D1 D0 Setting at reset Function Inverted pulse width during servo pull-in operation in KICK operation. (Set value×TS＋TS/2) µs 1 KICK pulse initial accelerating time (0 to 15) (Set value×TS) µs 9 TS : 11.3 µs TE TE Inverted pulse width KICK (TRD) KICK (TRD) Brake Initial accelerating time Table 7-1-4 (26) (F)-9 KICK pulse level setting (KICK) Data (D7 to D0) Address (HEX) (A7 to A0) Command (HEX) (B7 to B0) 0 D6 D5 D4 D3 D2 D1 D0 78 F2 Function KICK pulse level setting KICK (0 to 127) 0 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) (HEX) (A7 to A0) (B7 to B0) 79 22 Table 7-1-4 (27) (F)-10 Traverse output gain setting (TRV) Data (D7 to D0) Setting at reset F2 Function Traverse output gain setting TRV (0 to 127) SDD00026AEM Setting at reset 65 42 MN662785TBUC (F)-11 Traverse fine adjustment gain setting (TRVG0) Data (D7 to D0) D7 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) (HEX) (A7 to A0) (B7 to B0) 37 Table 7-1-4 (28) Setting at reset Function Traverse gain (0 to 127) TRVG0/16 F2 18 Set the above value after setting the TRV value. (F)-12 Setting of automatic adjustment range The limits of adjustment values can be set arbitrarily in the range of 1/28 to 255/2 (or −48 dB to ＋42 dB). In order to ensure automatic gain convergence within a limited, narrow adjustment range to prevent excessive gain change, which had difficulty in convergence control, however, make sure that the maximum automatic adjustment range is ±9 dB on the basis of the gain set value. ・Tracking gain Automatic adjustment range GLT3/GLT4 to GLT1/GLT2 Address Command Data (HEX) (HEX) Function (D7 to D0) (A7 to A0) (B7 to B0) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 3D 3E D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 3F Tracking gain upper limit GLT1 (mantissa) (128 to 255) GLT2 (exponent) (0 to 7) Upper limit: GLT1/28-GLT2 Tracking gain lower limit GLT3 (mantissa) (128 to 255) GLT4 (exponent) (0 to 7) Lower limit: GLT3/28-GLT4 F2 40 ・Focus gain Automatic adjustment range GLF3/GLF4 to GLF1/GLF2 Data (D7 to D0) Command Address (HEX) (HEX) (A7 to A0) (B7 to B0) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 39 3A D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D 3 D2 D1 D0 3B 3C F2 Setting at reset 212 2 106 0 Table 7-1-4 (30) Function Focus gain upper limit GLF1 (mantissa) (128 to 255) GLF2 (exponent) (0 to 7) Upper limit: GLF1/28-GLF2 Focus gain lower limit GLF3 (mantissa) (128 to 255) GLF4 (exponent) (0 to 7) Lower limit: GLF3/28-GLF4 SDD00026AEM Table 7-1-4 (29) Setting at reset 143 4 144 1 43 MN662785TBUC (G) Access command setting Command (HEX) (B7 to B0) Data (D15 to D0) D15 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Track-count setting Function F1 KICK-count setting/KICK operation start Inner track KICK operation Outer track KICK operation F3 Track-count setting / Track counting start Inner track counting Outer track counting Kick-count setting (other than 0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 7-1-4 (31) Note) The track-count means the number of tracks until the brake operation start point is reached. TE sampling frequency in track counting is 176.4 kHz. Care must be taken so that the maximum TE frequency in track counting does not exceed one fourth of the sampling frequency. SDD00026AEM 44 MN662785TBUC (H) Spindle related settings (H)-1 Table 7-1-4 (32) Setting of spindle forced acceleration/deceleration (ECM) output level Data (D7 to D0) Address (HEX) Command (HEX) (A7 to A0) (B7 to B0) D7 D6 D5 D4 D3 D2 D1 D0 2B Setting at reset Function ECM acceleration (ACC) level setting ECM (0 to 127) F2 127 * At the time of deceleration (BREAK), 2's complement of the above setting will be output. * If the ECM value is set to 127, 128 (ALLH or ALLL) will be output. (H)-2 Setting of spindle shaft loss compensation value Data (D7 to D0) Address (HEX) Command (HEX) (A7 to A0) (B7 to B0) D7 D6 D5 D4 D3 D2 D1 D0 2C F2 Table 7-1-4 (33) Setting at reset Function Shaft loss compensation value setting SVOFS (-128 to 0) 0 * The shaft loss compensation value will be enabled only when the spindle is in free running condition (STOP). No compensation will be enabled with this value set to 0. (H)-3 Spindle fine adjustment gain setting (SPG0) Data (D7 to D0) D7 D6 D5 D4 D3 D2 D1 D0 Address (HEX) Command (HEX) (A7 to A0) (B7 to B0) 2F F2 Function Spindle gain（0 to 127） SPG0／16 Table 7-1-4 (34) Setting at reset 22 Set the above value after setting the spindle gain with the 45h command. SDD00026AEM 45 MN662785TBUC 7-1 (5) Data setting for signal processing section (A) Audio control Table 7-1-5 (1) Command (HEX) (B7 to B0) Data (D15 to D0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ 41 Symbol Function (＊： Setting at reset) BIMAIN, Bilingual setting BISUB ＊Normal stereo L-ch monaural R-ch monaural L- and R-ch reverse I NV ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ Audio output polarity selection ＊Normal Inverted Emphasis control (Note 1) MEMP ＊De-emphasis connected directly Forced ON Forced OFF ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ １ＸＸＸ Serial data output selection DEPSEL ＊Before general attenuation and de-emphasis processing After general attenuation and de-emphasis processing Internal serial data muting SMUTE ＊Disabled Enabled Note) Serial data input to the anti-shock memory controller will be muted. ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸＸＸ LRINV Selection of polarity of LRCK for DF input ＊Normal（L-ch：H） Inverted ＸＸＸＸ ＸＸＸＸ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸＸＸ ＸＸＸＸ XBS XBS mode selection ＊Disabled Enabled ASC ASC mode selection ＊Disabled Enabled LI VE LIVE mode selection ＊Disabled Enabled ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ AUDIO1, Serial data format selection AUDIO2 ＊AUDIO mode 1 AUDIO mode 2 ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ XMUTE Serial data output muting ＊Disabled Enabled Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ MMUTE Audio output muting ＊Disabled Enabled Note 1) Care must be taken during the anti-shock memory control operation since the control timing must be shifted based on the remaining memory though it is not needed during the normal operation. SDD00026AEM 46 MN662785TBUC (B) Digital audio interface control Table 7-1-5 (2) Command (HEX) (B7 to B0) Data (D15 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１１ 42 Symbol UBITC Bit U control ＊LDON control (Inverted LDON) Output enabled Output fixed at high level COPYI Generation status bit setting ＊ 0 setting 1 setting ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ TXVSEL Bit V control 1 ＊High level while the signal is attenuated Signal attenuation ignored Note 1) Soft muting is included. Note 2) Both levels will be high with the gain set to −∞ dB. ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ TMUTE ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ TXDSEL Output speed selection ＊Normal speed 2x speed Note 1) Available only if the anti-shock memory controller is turned off in 2x-speed playback mode. Note 2) Audio signal will be output at 2xspeed as well. ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸＸＸ VFREE ＸＸＸＸ ＸＸＸＸ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ ＸＸＸＸ Output control ＊Enabled Fixed at low level CATC Category code setting ＊CD mode General mode CFS1, CFS2 Clock precision setting ＊Standard mode Variable pitch mode High precision mode Not defined ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ＸＸ １ＸＸ ０ＸＸ １ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ SDD00026AEM Bit V control 3 ＊The level will be high while the signal is attenuated (including the gain setting to −∞dB) in DMUTE condition. Signal attenuation (including the gain setting to −∞ dB) with DMUTE condition ignored. XSEL ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Output data muting ＊Disabled Enabled Note 1) Only audio data is fixed at 0. Note 2) The bit V level is high. IPDISEN Bit V control 2 ＊High level when the level of IPFLAG is high IPFLAG ignored ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Function (＊： Setting at reset) 47 MN662785TBUC (C) Attenuation control Command (HEX) (B7 to B0) Data (D15 to D0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ D7 D6 D5 D4 D3 D2 D1 D0 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ００ Ｘ０１ Ｘ１０ Ｘ１１ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ 44 Ｘ Ｘ Ｘ Ｘ Symbol ATT, MUTEM 45 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ ０ ０ Ｘ Ｘ Ｘ Ｘ ０ＸＸ ０ＸＸ ０ＸＸ ０ＸＸ ００００ ００００ ０００１ ０００１ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ １ ０ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ ０ ０ Ｘ Ｘ Ｘ Ｘ ０ＸＸ ０ＸＸ ０ＸＸ ０ＸＸ ０００Ｘ ０００Ｘ ０００Ｘ ０００Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ Ｘ Ｘ Ｘ Ｘ Symbol SG0, SG1 ＸＸＸ０ Ｘ０Ｘ０ ０００Ｘ ＸＸＸＸ ＸＸＸ０ Ｘ０Ｘ１ ０００Ｘ ＸＸＸＸ ＸＸＸ０ Ｘ０１Ｘ ０００Ｘ ＸＸＸＸ ＸＸＸ０ ００ＸＸ ０００Ｘ ＸＸＸＸ ＸＸＸ０ １０ＸＸ ０００Ｘ ＸＸＸＸ ＸＸ００ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ ＸＸ１０ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ Loop gain setting ＊×1 ×2 ×4 ×1/2 PC output polarity selection ＊Normal (ON at low level) Inverted CLVSEL Selection of CLV mode transition condition (from rough to CLV) ＊ RESY: High level and rpm condition (±4.6%) RESY: High level Note) Transition from CLV to rough mode is enabled under the condition of BSSEL failure. JFMODE Analog jitter-free mode ＊Disabled Enabled ACCFIX Ｘ０Ｘ０ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ Ｘ１Ｘ０ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ ０ＸＸ０ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ １ＸＸ０ Ｘ０ＸＸ ０００Ｘ ＸＸＸＸ Function (＊： Setting at reset) FO1SEL, f0 frequency setting FO2SEL ＊ 24 Hz 6 Hz 12 Hz 3 Hz PCINV ＸＸＸ０ Ｘ００Ｘ ０００Ｘ ＸＸＸＸ ＊Normal (0 dB) Soft muting Digital attenuation Soft attenuation Table 7-1-5 (4) Command (HEX) (B7 to B0) Ｘ Ｘ Ｘ Ｘ Function (＊： Setting at reset) MCNT(7:0) Attenuation level setting Note) The attenuation level is set to n/256. Initially set to 40 (HEX). (D) Spindle control 2 Data (D15 to D0) Table 7-1-5 (3) KILL Spindle fixed in a single direction (for acceleration only) ＊Disabled Enabled Signal processing clock stop ＊Disabled Enabled CKSTOP Oscillation stop ＊Disabled Enabled Note) The IC is reset and stops. SDD00026AEM 48 MN662785TBUC (E) PWM output control (Optical servo system) Command (HEX) (B7 to B0) Data (D15 to D0) 46 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸ００ ＸＸ００ ＸＸ００ ＸＸ００ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸ００ ＸＸ００ ＸＸ００ ＸＸ００ ０ ０ １ １ ０ １ ０ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Table 7-1-5 (5) Symbol Function (＊： Setting at reset) FBAL1E, FBAL2E FBAL charge pump current source control Stop ＊×1 ×1/2 ×3/2 TBAL1E, TBAL2E TBAL charge pump current source control Stop ＊×1 ×1/2 ×3/2 MCFSEL Noise filter for microcomputer interface ＊Enabled Disabled ＸＸＸＸ ＸＸＸＸ ０Ｘ００ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １Ｘ００ ＸＸＸＸ SDD00026AEM 49 MN662785TBUC (F) Playback speed control Command (HEX) Symbol (B7 to B0) Data (D15 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ 49 2x-speed playback selection ＊Normal speed 2x speed QSEL 4x-speed playback selection (Note 4) ＊Normal speed 4x speed OVERDRV Overdrive mode (Note 4) ＊Disabled Enabled Note 1) Constantly 1.5x speed based on the speed set with DSEL and QSEL. Note 2) Available in jitter-free mode only. ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ Ｘ０００ Ｘ００１ Ｘ０１０ Ｘ０１１ Ｘ１００ Ｘ１０１ Ｘ１１０ Ｘ１１１ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Function (＊： Setting at reset) DSEL ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Table 7-1-5 (6) SVPC(2:0) Spindle speed change rate setting ＊×1 ×15/16 ×14/16 ×13/16 ×12/16 ×11/16 ×10/16 × 9/16 Note 3) Available in jitter-free mode only. Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ VCOE VCO control for jitter-free ＊OFF Oscillation ON CPOFF Charge pump current source stop (for jitter-free) ＊Disabled Enabled ＸＸＸＸ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Note 4) If the anti-shock memory controller is turned on, maximum 2.25x-speed playback in decompression mode and maximum 3x-speed playback in compression mode are guaranteed with the jitter-free function turned on. (G) DO control Table 7-1-5 (7) Data (D15 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ Command (HEX) (B7 to B0) Symbol 4A DSLDO DSL's DO processing ＊Enabled Disabled CLVDO Spindle's DO processing ＊Enabled Disabled PLLDO PLL's DO processing ＊Enabled Disabled W GEN DO with faults processing ＊Enabled Disabled ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ０ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ SDD00026AEM Function (＊： Setting at reset) 50 MN662785TBUC (H) PLL control Data (D15 to D0) Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ ０ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ Symbol 4B PLLG1, PLLG2 PLLF current setting ＊×1 (Conventional setting) ×5/4 ×1/2 ×3/4 PCKG VCO frequency selection ＊×1/2 ×1 IROFF IREF current shut off ＊Normal Shut off PLHLD PLLF current shut off by tracking failure ＊Disabled Enabled DET5T Frequency pull-in method selection ＊2T detection 5T detection ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ０ＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ １ＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸ１ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ Ｘ Ｘ ０ Ｘ Ｘ Ｘ D9 D8 D7 D6 Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸ０Ｘ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ Ｘ１ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ００ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０１ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ０ ０ １ １ ０ １ ０ １ ０ ０ ０ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Table 7-1-5 (8) Command (HEX) (B7 to B0) Function (＊： Setting at reset) FL02,FL04, Pull-in time setting with 2T or 5T detected FL08,FL16 Calculation formula ： 9×32＋nD8× 6＋ D7× ＋nD6× ＋ (pck) Note) Initially set to 32 pck FH32 Pull-in time setting with 12T detected ＊64 pck 32 pck Forced double current setting for phase PLLG comparison ＊Disabled Enabled PLLG3, PLLG4 Ｘ Ｘ Ｘ Ｘ SDD00026AEM Frequency comparison current rate selection ＊×1 ×5/4 ×1/2 ×3/4 51 MN662785TBUC (I) I/O control 1 Data (D15 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ１ Command (HEX) (B7 to B0) Symbol 4C TX T2 SROUT2 ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ Function (＊： Setting at reset) CD-TEXT data output pin selection ＊(SUBC, SBCK, NCLDCK) (TXTD, TXTCLK, DQSY) Serial output pin selection ＊(SUBC, SBCK, NCLDCK) (SRDATA, LRCK, BCLK) EXT12SEL EXT1 and EXT2 output pins selection ＊(EXT1, EXT2) (VDET, EFM) ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ０ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ Ｘ１ＸＸ PCKOUT ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ０１ＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ １１ＸＸ EXT1 output pin selection 2 ＊VDET PCK Note) Enabled only when the level of EXT12SEL is high. (J) DSL unbalance compensation control Command (HEX) (B7 to B0) Data (D15 to D0) ＸＸＸＸ Ｘ０１Ｘ ＸＸＸＸ ０ＸＸ０ ＸＸＸＸ Ｘ０１Ｘ ＸＸＸＸ １ＸＸ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ０ Ｘ０ Ｘ０ Ｘ０ １Ｘ １Ｘ １Ｘ １Ｘ ００ＸＸ ０１ＸＸ １０ＸＸ １１ＸＸ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Table 7-1-5 (9) 4D Symbol DSLBSEL DSLB1E, DSLB2E ０ ０ ０ ０ ＸＸＸＸ Ｘ０１０ ＸＸＸＸ ＸＸＸ０ ＸＸＸＸ Ｘ０１１ ＸＸＸＸ ＸＸＸ０ DSLBEN SDD00026AEM Table 7-1-5 (10) Function (＊： Setting at reset) EFM or SRF selection ＊EFM SRF Charge pump current source control ＊Shut off × 1 × 1/2 × 3/2 Compensation value counter operation control ＊Previous value kept on hold Compensation value taken in 52 MN662785TBUC (K) I/O control 2 Data (D15 to D0) ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ ０ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ １ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ ０ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ １ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ ０ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ １ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸ０ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸＸ１ ０ Ｘ Ｘ Ｘ Table 7-1-5 (11) Command (HEX) (B7 to B0) Symbol Function (＊： Setting at reset) 4E IOSTOP Output pin fixed at low level Disabled ＊Enabled Note 1) Enabled pins: SRDATA, LRCK, BCLK, IPFLAG, SUBC, NCLDCK Note 2) Serial input mode is activated if IOSTOP is disabled. EXT0,EXT1,EXT2 RDATA,LRCK,BCLK MCMSEL SMCK frequency selection 8.4672 MHz ＊4.2336 MHz DF input selection DFSEL ＊Input bypassing the anti-shock memory controller Input from the anti-shock memory controller Off-track noise filter OFTSEL ＊Disabled Enabled ＸＸ Ｘ０ ０ＸＸＸ ＸＸ０Ｘ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ ＸＸ１Ｘ ０ Ｘ Ｘ Ｘ EXT0SEL ＸＸ Ｘ０ ０ＸＸＸ Ｘ０ＸＸ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ Ｘ１ＸＸ ０ Ｘ Ｘ Ｘ DSLDR ＸＸ Ｘ０ ０ＸＸＸ ０ＸＸＸ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸＸ １ＸＸＸ ０ Ｘ Ｘ Ｘ RSEL ＸＸ Ｘ０ ０Ｘ００ ＸＸＸＸ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０Ｘ１０ ＸＸＸＸ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０ＸＸ１ ＸＸＸＸ ０ Ｘ Ｘ Ｘ MCOM4E BLKCKSEL ＸＸ Ｘ０ ００ＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ ＸＸ Ｘ０ ０１ＸＸ ＸＸＸＸ ０ Ｘ Ｘ ０ MPEGIF IPSEL EXT0 pin selection ＊Normal Serial monitor (for evaluation) DRF pin control ＊Disabled Enabled RSEL selection Bright levelÅFLow ＊Bright level：High BLKCK and SUBQ pins selection ＊(BLKCK, SUBQ) (ZBLKCK, SUBQ) (DQSY, TXTD) Note) ZBLKCK:Interpolation BLKCK, TXTD:CD-TEXT data Serial output mode selection ＊Normal Serial output mode Note) DMUTE,SUBQ,SQCK → RDATA,LRCK,BCLK ＸＸ ００ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ ＸＸ １０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ IPFLAG pin selection ＊Normal CLVS Ｘ０ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ Ｘ１ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ FLAG pin selection FLAGSEL ＊Normal Serial monitor (for evaluation) ０Ｘ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ １Ｘ Ｘ０ ０ＸＸＸ ＸＸＸＸ ０ Ｘ Ｘ Ｘ FLAGFIX SDD00026AEM FLAG0 output fixed ＊Disabled Enabled Note) FLAG0 is always output from FLAG pin. 53 MN662785TBUC (L) STAT pin control Data (D15 to D0) XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX Command (HEX) (B7 to B0) XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 70 71 72 73 74 76 77 79 7A 7B D2D1 XXX X XXX X XXXX X0 0 X XXX X XXX X XXXX X0 1 X XXX X XXX X XXXX X1 0 X XXX X XXX X XXXX X1 1 X 75 Function (＊： Setting at reset) Symbol STAT pin output selection ＊ : CRC : RESY : CLVS : NTTSTOP : SQOK : BSSEL : FCLV : SUBQ (SQCK sync) / TXTDAT : SUBQ (MCLK sync) / TXTDAT : ZDET (Zero data detection) STAT pin output setting ＊STAT pin output： 0. FLAG6 0. SENSE 0. NFLOCK 0. NTLOCK STAT pin output mode selection by MCLK (excluding the setting of SENSE(01)) 1. FLAG6 2. SENSE 3. NFLOCK 4. NTLOCK 5. SQOK 6. CRC 7. CLVS 8. NTTSTOP D0 XXX X XXX X XXXX XXX0 XXX X XXX X XXXX XXX1 XXX X XXX X XXXX XXXX Table 7-1-5 (12) Clearing FLAG6 output from STAT pin ＊Disabled Enabled (Reset of FLAG6) Disc rotation speed data output from STAT pin (8-bit data) 7E D 2D 1D 0 0 1 1 1 0 1 0 1 MDATA MCLK MLD STAT output 0 1 2 3 4 5 6 7 8 Timing chart of STAT pin output mode selection by MCLK SDD00026AEM 54 MN662785TBUC 7-1 (6) Data setting for anti-shock memory controller [1] Data write (A) Memory system command Table 7-1-6 (1) Command (HEX) (B7 to B0) Data (D7 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸ１Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ Ｘ Ｘ Ｘ Ｘ 80 Ｘ Ｘ Ｘ Ｘ Symbol Function (＊： Setting at reset) MSON ＊ Memory system stop Memory system run WAQV ＊ Q-data disabled Q-data enabled MSDCN ＊ Comparison connection aborted Direct connection 2-pair comparison connection 3-pair comparison connection ＸＸＸ０ ＸＸＸ１ ＸＸＸＸ ＸＸＸＸ MSRACL ＊ Normal operation Read address reset ＸＸ０Ｘ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ MSRDEN ＊ Decoding aborted Decoding executed Ｘ０ＸＸ Ｘ１ＸＸ ＸＸＸＸ ＸＸＸＸ MSWACL ＊ Normal operation Write address reset ０ＸＸＸ １ＸＸＸ ＸＸＸＸ ＸＸＸＸ MSWREN ＊ Encoding aborted Encoding executed (B) Expansion I/O port (I/O setting) Table 7-1-6 (2) Data (D7 to D0) Command (HEX) (B7 to B0) Symbol 81 EXT0ST Expansion I/O Port EXT0 I/O setting ＊ Input Output Function (＊： Setting at reset) Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ ＸＸＸ０ ＸＸＸ１ Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ ＸＸ０Ｘ ＸＸ１Ｘ EXT1ST Expansion I/O Port EXT1 I/O setting ＊ Input Output Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ Ｘ０ＸＸ Ｘ１ＸＸ EXT2ST Expansion I/O Port EXT2 I/O setting ＊ Input Output SDD00026AEM 55 MN662785TBUC (C) Expansion I/O port (Output data setting) Table 7-1-6 (3) Command (HEX) (B7 to B0) Data (D7 to D0) Symbol Function (＊： Setting at reset) EXT0WT Expansion I/O port EXT0 output setting ＊ L output H output ＸＸ０Ｘ ＸＸ１Ｘ EXT1WT Expansion I/O port EXT1 output setting ＊ L output H output Ｘ０ＸＸ Ｘ１ＸＸ EXT2WT Expansion I/O port EXT2 output setting ＊ L output H output Ｘ Ｘ ＸＸ Ｘ Ｘ ＸＸ ＸＸＸ０ ＸＸＸ１ Ｘ Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ Ｘ ＸＸ Ｘ Ｘ ＸＸ 82 (D) Option setting Table 7-1-6 (4) Command (HEX) (B7 to B0) Data (D7 to D0) 85 Function (＊： Setting at reset) Symbol CMOD ＊ Decompression mode 4-bit compression mode ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ ＸＸＸ１ ＸＸ０Ｘ ＸＸ１Ｘ ＸＸＸＸ ＸＸＸＸ Ｘ００Ｘ Ｘ１０Ｘ ＸＸＸＸ ＸＸＸＸ RSEL1 ＊ One DRAM used Two DRAMs used (NCAS of unused RAM is fixed at high level) ０Ｘ０Ｘ １Ｘ０Ｘ ＸＸＸＸ ＸＸＸＸ RSEL0 ＊ 1M DRAM used 4M DRAM used WSEL ＊ No window discrimination Window discrimination 98±4 CLDCK window Window discrimination 98±8 CLDCK window Window discrimination 98±28 CLDCK window ０ ０ ０ ０ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ １ １ １ １ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ０ ０ １ １ ０ １ ０ １ ＊ 16M DRAM not used 16M DRAM used (NCAS1 used as A10) 86 ０ＸＸ１ ０ＸＸ１ Ｘ０ＸＸ Ｘ１ＸＸ C2SEL ＊ Interpolated comparison Comparison without interpolation ０ＸＸ１ ０ＸＸ１ ０ＸＸＸ １ＸＸＸ CMPSEL ＊ 16-bit comparison Upper 12-bit comparison ０Ｘ０１ ０Ｘ１１ ＸＸＸＸ ＸＸＸＸ Parameter reset at start of encoding during direct connection ＊ No Yes Note) The D4 bit of the 86h command is by default set to 0. Set this bit to 1 while the memory system is running, otherwise playback data will involve noise. SDD00026AEM 56 MN662785TBUC (E) Q code input for optical digital output signal (TX) MDATA Q0 Q1 Q2 ･･･････ Q77 Q78 Q79 ････････ MCLK MLD If the anti-shock memory controller is turned on, Q code data can be set for user data on the optical digital output signal. Table 7-1-6 (5) Command (HEX) (B7 to B0) Data Symbol Q0 to Q79 (80 bits) 87 Function MCQ Q code input for TX Internal block sync signal CLDCK ･･･ ･･･ ･･･ ･･･ 16 clocks Input timing ･･･ ･･･ ･･･ 16 clocks ･･･ 16 clocks a c b Output timing A The Q code that is input into a-zone is output as bit U data during period A. Details of bit U (Q channel) --- 0 0 Q0 Sub code Sync word --- Q1 Q79 Q80 Q81 --- Q95 CRC data (16 bits) Input data 0 0 Sub code Sync word --- CRC data is generated from the arithmetic operation of input data and added. Note1) The internal block sync signal is a synchronized with a subcode sync word. Data input a b c A B BLKCK Output data A C C If no Q code is input, the previous value will be kept on hold and bit U will be output. At that time, CRC data is added with disabling data. Note2) ・Interruption is not allowed while the Q code is input, otherwise the wrong bit U will be output. ・The Q code cannot be input into a single block more than once, otherwise the wrong bit U will be output. SDD00026AEM 57 MN662785TBUC [2] Data read Read command MDATA MLD MCLK Indefinite S0 STAT pin S1 S2 S3 S4 S5 S6 S7 Min. 25 µs Figure 7-1-6 Timing chart for reading data (A) Status command Table 7-1-6 (6) Command (HEX) (B7 to B0) Output bit Symbol 90 S0 FLAG6 L: FLAG6I input normal H: FLAG6I input abnormal S1 MSOVF L: Normal H: Write overflow S4 DCOMP L: Normal H: During comparison connection S0 MSEMP L: Normal H: No enabled data S1 OVFL L: Normal H: Write overflow 91 Function SDD00026AEM 58 MN662785TBUC (B) Remaining enabled data Table 7-1-6 (7) Command (HEX) (B7 to B0) Output bit 92 S0 H: 8M bits S1 H: 4M bits S2 H: 2M bits S3 H: 1M bits S4 H: 512K bits S5 H: 256K bits S6 H: 128K bits S7 H: 64K bits S8 H: 32K bits S9 H: 16K bits S10 H: 8K bits S11 H: 4K bits S12 H: 2K bits S13 H: 1K bits S14 H: 512 bits S15 H: 256 bits Function (C) Expansion I/O port Table 7-1-6 (8) Command (HEX) (B7 to B0) Output bit 93 S5 EXT2RD Expansion I/O port EXT2 input data S6 EXT1RD Expansion I/O port EXT1 input data S7 EXT0RD Expansion I/O port EXT0 input data Symbol SDD00026AEM Function 59 MN662785TBUC 7-1 (7) Automatic adjustment Following is a list of automatic adjustment. Table 7-1-7 Command (HEX) (B7 to B0) Offset AOC1 (Note) Fo balance ABC1 Tr balance ABC2 Fo rough gain AGC1 Tr rough gain AGC2 Fo fine gain FAGC Tr fine gain TAGC F9 F7 FB FC FD FE FF Description Traverse Time required operation Averages and corrects the focus error values and tracking error values as offset when the laser is turned on or off. 50 ms FWD/REV to enabled 140 ms Inputs the disturbance into the focus servo loop, and makes corrections so that the envelope ripple for the 3T component of the RF signal in the positive and negative parts of the FE signal should be balanced. The output pin for corrections is FBAL. Within 0.5 s STOP The average tracking error value without the tracking servo is used as a balancing value to make corrections. The output pin for corrections is TBAL. Within 1s STOP FWD/REV Set Focus search is performed at approx. 5.4 Hz or enabled between 1.3 Hz, and the disturbance input amount for the fine AGC is determined using focus error S-curve 190 ms and p-p value. The gain will be unchanged. 780 ms The p-p value of the tracking error without the tracking servo determines the disturbance input amount for the fine AGC. The gain will be unchanged. Set between 135 ms and 350 ms Inputs the disturbance into the focus servo loop, and adjusts the gain crossover to the frequency set by the microcomputer command. Within 0.5 s STOP Within 0.5 s STOP Inputs the disturbance into the tracking servo loop, and adjusts the gain crossover to the frequency set by the microcomputer command. STOP Note) Do not use FAh, a conventional AOC2 command. SDD00026AEM 60 MN662785TBUC 7-2 Input timing 7-2 (1) Subcode interface A. SUBQ data read Subcode data can be read at the timing shown in the figure below. BLKCK ∼ ∼ NCLDCK 80 clocks SQOK Q1 Q2 Q3 Q4 ∼ ∼ ∼ ∼ STAT (=CRC) CRC ∼ ∼ SUBQ ∼ ∼ ∼ ∼ ∼ ∼ SQCK Q79 Q80 H: CRC=OK CRC L: CRC=NG 8.7 ms Figure 7-2-1 BLKCK, NCLDCK, SQCK, SUBQ, and CRC timing chart SDD00026AEM 61 MN662785TBUC B. Subcode data read By inputting a clock from SBCK pin, subcode data, P to W, can be read from SUBC pin. The timing is shown in the figure below. Since subcode data varies every falling edge of NCLDCK, input 8 clocks of SBCK every falling edge of NCLDCK, and switch the content of SUBC output to P to W. Then SUBC output which varies in synchronization with the falling edge of SBCK is received at the timing of the rising edge of SBCK. All subcode data can be read by repeating the operation above for each NCLDCK. By inputting SBCK, the content of FLAG output will vary. So measuring the error rate while reading subcode is not possible. Take it into consideration when designing the system. Typ. Typ. 136 µs 1.6 µs BLKCK NCLDCK SBCK SUBC S0 S1 P1 to W1 P2 to W2 P3 to W3 P4 to W4 P5 to W5 P6 to W6 P7 to W7 NCLDCK ＊ ＊ SBCK ＊ SUBC P ＊ Q R S T U V W ＊ ＊: Refer to the values specified in the PRODUCT STANDARDS. Figure 7-2-2 NCLDCK, SUBC, and SBCK timing chart SDD00026AEM 62 MN662785TBUC 7-2 (2) Serial data output A. Serial data output mode 1 By executing the following command, the BCLK signal, LRCK signal, and SRDATA signal will be output from pins 65, 66, and 67 respectively. Table 7-3-1 Command (HEX) (B7 to B0) Data (D15 to D0) 4E ＸＸＸ Ｘ Ｘ １ＸＸ ＸＸＸＸ ＸＸＸ０ Symbol MPEGIF, IOSTOP Note) X can be any value. B. Serial data output mode 2 By executing the following command, the SRDATA signal, LRCK signal, and BCLK signal will be output from pins 73, 74, and 75 respectively. Table 7-3-2 (1) Command Symbol (HEX) Data (D15 to D0) (B7 to B0) 4C Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ Ｘ ＸＸ Ｘ Ｘ １ Ｘ SROUT2 Note) X can be any value. Table 7-3-2 (2) Command (HEX) (B7 to B0) Data (D15 to D0) 4E ＸＸＸＸ ＸＸＸＸ ＸＸＸＸ ＸＸＸ０ Symbol IOSTOP Note) X can be any value. C. Serial data output selection The following command determines whether serial data in serial data output mode 1 or serial data output mode 2 is output with or without attenuation and de-emphasis. Table 7-3-3 Data (D15 to D0) ＸＸＸＸ ＸＸＸＸ ＸＸ０Ｘ ＸＸＸＸ Command (HEX) Symbol (B7 to B0) 41 ＸＸＸＸ ＸＸＸＸ ＸＸ１Ｘ ＸＸＸＸ DSPSEL Function With no attenuation or de-emphasis With attenuation and de-emphasis Note) X can be any value. SDD00026AEM 63 MN662785TBUC D. Serial data output timing The following timing chart shows the output timing of serial data. Serial data output mode 1 and 2 are the same in the output timing of serial data. Invalid SR D A T A Invalid 15 1413121110 9 8 7 6 5 4 3 2 1 0 Invalid 15 1413121110 9 8 7 6 5 4 3 2 1 0 15 LRCK BCLK L- c h R-ch L-ch 7-2 (3) Serial data input When the IC is in serial data output mode 1 or 2, the SRDATA signal, LRCK signal, and BCLK signal will be input into pins 57, 58, and 59 respectively so that IOSTOP bit will be set to 0. Therefore, handle pins 57, 58, and 59 as input pins in serial data output mode 1 or 2. The input timing of serial data is the same as the output timing of serial data. SDD00026AEM 64 MN662785TBUC PRODUCT STANDARDS A. ABSOLUTE MAXIMUM RATINGS Parameter Ta＝25°C Symbol Rating Unit Note DVDD1,2 AVDD1,2 −0.3 to ＋4.6 V DVSS1,2=0 V AVSS1,2=0 V A1 Supply voltage A2 Input voltage VI DVSS1,2−0.3 to DVDD1,2＋0.3 AVSS1,2−0.3 to AVDD1,2＋0.3 V DVSS1,2=0 V AVSS1,2=0 V A3 Output voltage VO DVSS1,2−0.3 to DVDD1,2＋0.3 AVSS1,2−0.3 to AVDD1,2＋0.3 V DVSS1,2=0 V AVSS1,2=0 V A4 Power dissipation PD 570 mW DVSS1,2=0 V AVSS1,2=0 V A5 Operating ambient temperature Topr −40 to ＋85 °C A6 Storage temperature Tstg −55 to ＋125 Note 1) The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. Note 2) Each of DVSS1, DVSS2, AVSS1, and AVSS2 pins should be directly connected to the ground and used at the same voltage. Note 3) Each of DVDD1, DVDD2, AVDD1, and AVDD2 pins should be directly connected to the specified power supply and used at the same voltage. Note 4) DVDD1, DVDD2, AVDD1, and AVDD2 should be powered up at the same time. Note 5) The operation of the audio D/A converter is not guaranteed for operations in 2x-speed playback modes (i.e., when anti-shock memory controller is not operating). Note 6) Connect a bypass capacitor (0.1 µF or more) between DVDD1 and DVSS1 pins, between DVDD2 and DVSS2 pins, between AVDD1 and AVSS1 pins, and between AVDD2 and AVSS2 pins. SDD00026AEM 65 MN662785TBUC Ta＝−40°C to ＋85°C B. OPERATING CONDITIONS DVSS1,2＝0 V AVSS1,2＝0 V Limits Parameter B1 B2 B3 B4 Symbol Digital system supply voltage Audio system supply voltage Analog system supply voltage DVDD1,2 D-RAM interface voltage Note 7) Conditions Unit Min Typ Max 3.0 3.3 3.6 V AVDD1 (Note 7) 3.0 3.3 3.6 V AVDD2 (Note 7) 3.0 3.3 3.6 V 3.6 V VDD1,2 DVDD3V It is recommended to basically use AVDD1 and AVDD2 at the same voltage as DVDD. Self-excited Oscillation DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C (Note 8) B5 Crystal frequency B6 External capacitance 1 C1 B7 External capacitance 2 C2 fxtal With no external resistor R 33.8688 MHz 10 pF 10 pF Note 8) Oscillator Circuit C2 X2 Xtal MN662785TBUC X1 C1 SDD00026AEM 66 MN662785TBUC C. ELECTRICAL CHARACTERISTICS (1) DC Characteristics DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min C1 Supply current IDD C2 Total power consumption PT C3 Supply current IDD C4 Total power consumption PT Anti-shock memory controller is not operating. No external load (in normal-speed playback mode) Ta＝25°C Anti-shock memory controller is not operating. No external load (in 2x-speed playback mode) Ta＝25°C SDD00026AEM Typ Max 23 46 mA 76 152 mW 24 48 mA 80 160 mW 67 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max Input Pins (1) ＊1 Input voltage high level Input voltage C6 low level Input leakage C7 current C5 ＊1 VIH1 2.64 DVDD1,2 V VIL1 DVSS1,2 0.66 V ±1 µA I LK1 VIN＝0 V to 3.3 V FSEL, CSEL TMOD1, TMOD2 EXT0/ISRDATA/SRMON2, EXT1/ILRCK/VDET/PCK, EXT2/IBCLK/EFM D0, D1, D2, D3, OFT, NRFDET, BDO, NTEST, MCLK, MDATA, MLD, SQCK/BCLK1/TXTCLK1, DMUTE/SRDATA1, NRST, SBCK/TXTCLK2/LRCK2 SDD00026AEM 68 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max Output Pins (1) ＊2 C8 C9 Output voltage high level Output voltage low level VOH1 IOH1＝−1 mA VOL1 IOL1＝1 mA DVDD1,2 V −0.6 0.4 V Output Pins (2) ＊3 C10 Output voltage high level C11 Output voltage low level Output leakage C12 current DVDD1,2 VOH2 IOH2＝−1 mA VOL2 IOL2＝1 mA 0.4 V ILK2 Hi-Z VO＝0 V to 3.3 V ±1 µA V −0.6 ＊2 LDON, FLAG/SRMON1, CLVS/IPFLAG, EXT0/ISRDATA/SRMON2, EXT1/ILRCK/VDET/PCK, EXT2/IBCLK/EFM, TX, BLKCK/DQSY1, SQCK/BCLK1/TXTCLK1, SUBQ/LRCK1/TXTDAT1, DMUTE/SRDATA1, STAT, SPPOL, PMCK, SMCK, SUBC/TXTDAT2/SRDATA2, SBCK/TXTCLK2/LRCK2, NCLDCK/DQSY2/BCLK2, D0, D1, NWE, NRAS, D2, D3, NCAS0, NCAS1, A8, A7, A6, A5, A4, A9, A0, A1, A2, A3 ＊2 SPOUT, TRVP, TRVM, TRP, TRM, FOP, FOM, SDD00026AEM 69 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Analog System Input Pin (1) C13 Input current IREF Analog System Input Pin (2) C14 Input signal amplitude VARF C15 Input leakage current ILKA Analog System Input Pin (3) C16 Input leakage current Internal resistance C17 between ARF and DRF Conditions Min Typ Max 25 47 80 0.5 1.0 IREF When pulled up by a 47-kΩ resistor µA ARF Input level of the EFM signal in the application circuit of the DSL circuit block V[p-p] ±1.0 µA ±1.0 µA 10 kΩ DRF ILKD RDRF Unit ARF＝1.65 V SDD00026AEM 70 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max Analog System Output Pin (1) DSLF (IREF pin is pulled up to AVDD2 by a 47-kΩ resistor.) C18 Output current (N) IDSH BDO＝L, Tracking ON-state DSLF＝1.65 V, ARF＝3.3 V 98 130 169 µA C19 Output current (P) IDSL BDO＝L, Tracking ON-state DSLF＝1.65 V, ARF＝0 V −169 −130 −98 µA Output current balance C20 in normal current mode IDSBL BDO＝L, Tracking ON-state Normal current mode −8.0 −2.0 ＋4.0 µA Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD2 by a 47-kΩ resistor.) Phase comparison C21 output current (N) IPFH BDO＝L, Tracking OFF-state 105 140 182 µA C22 output current (P) Phase comparison IPFL BDO＝L, Tracking OFF-state −182 −140 −105 µA C23 Input leakage current ILKP Hi-Z ±1 µA C24 in normal current mode Output current balance IPLBL BDO＝L, Tracking ON-state Normal current mode ＋3.0 µA PCK oscillator fVCO1 Normal- to 2x-speed jitter-free mode VCO frequency (for PCK) switching ＝×0.5 8.65 MHz C25 frequency −15.0 −6.0 4.32 Analog System Output Pin (3) VCOF (IREF pin is pulled up to AVDD2 by a 47-kΩ resistor.) Phase comparison C26 output current (N) Phase comparison C27 output current (P) IVFH 98 130 169 µA IVFL −169 −130 −98 µA C28 Input leakage current ILKV Hi-Z ±1 µA VCO oscillator fVCO4 Variable pitch jitter-free mode VCO frequency (for variable pitch jitter-free) switching＝×0.5 16.94 MHz C29 frequency 8.46 Analog System Output Pins (4) TBAL, FBAL (IREF pin is pulled up to AVDD2 by a 47-kΩ resistor.) C30 Output current (N) IBAH At default setting (×1) 23 32 41 µA C31 Output current (P) IBAL At default setting (×1) −41 −32 −23 µA SDD00026AEM 71 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz 3.3 V 47 kΩ 3.3 V IREF 0.022 µF AVDD1 220 µF VARF 1.0 V[p-p] (Typ.) AVSS1 0.001 µF ARF 100 kΩ 3.3 V DRF 100 kΩ AVDD2 DSLF 220 µF AVSS2 0.022 µF 3.3 V DVDD2 0.1 µF DVSS2 PLLF 3.3 V 390 Ω DVDD1 3.3 V 0.22 µF DVDD3V VCOF 0.01 µF 0.1 µF 0.1 µF DVSS1 2.2 kΩ 0.47 µF DSL／PLL Block Recommended Circuit Diagram SDD00026AEM 72 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Analog System Input Pins (4) C32 C33 Input voltage high level Input voltage low level T yp Max TE, FE, RFENV V I H4 0.9AVDD2 V I L4 0.1AVDD2 SDD00026AEM V V 73 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max A/D Converter (for Servo) C34 Resolution Integral C35 nonlinearity Differential C36 nonlinearity RES INL DNL A/D output=99 to 66 (2's complement ) SDD00026AEM 8 bit ±2 LSB ±3 LSB 74 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions D/A Converter Analog Characteristics Unit Min T yp Max (Note 9), (Note 12) C37 Signal-to-noise ratio S/N EIAJ 90 97 dB C38 Dynamic range D.R. EIAJ 86 94 dB THD+N EIAJ C39 Total harmonic distortion 0.005 0.009 C40 Crosstalk EIAJ C41 Output level 1 Reference input signal of 1 kHz Full scale (Note 10) C42 Output level difference Difference of OUTL and OUTR pins at output level 1. 20 log (VR/VL) C43 Output level 2 Reference input signal of 1 kHz Full scale (Note 11) 80 89 1.04 1.33 −0.99 0.69 % dB 1.62 Vrms ＋0.99 dB 1.07 Vrms 0.88 Note 9) The analog characteristics indicate the values measured by inserting a 15-Ω resistor between the AVDD1 pin and power supply. The typical values are only reference values. They are not guaranteed. Note 10) The output level 1 shows the measured value at the output pins of the application circuit. Note 11) Output level 2 is calculated by taking the measured value of output level 1, dividing it by the external circuit gain of the application circuit, and converting the result to the value at the output pin of this IC. Note 12) The D/A converter always operates in the normal-speed playback mode. SDD00026AEM 75 SDD00026AEM DVSS AVSS2 0.1 µF AVSS2 DVDD DVDD1 MN662785TBUC DVDD2 0.1 µF DVSS1 DVSS2 0.1 µF DVDD AVDD2 AVDD2 OUTR AVSS1 OUTL AVDD1 0.0018 µF 1 kΩ 0.1 µF 0.0018 µF 1 kΩ AVSS1 100 µF − ＋ 15 Ω AVDD1 ＋ − ＋ − DVSS 100 pF 47 kΩ 47 kΩ 47 kΩ 100 pF 22 µF 47 kΩ 47 kΩ 47 kΩ 22 µF 2.2 kΩ 1.5 kΩ − ＋ 100 pF 2.2 kΩ 1.5 kΩ − ＋ 100 pF 560 Ω 560 Ω 0.001 µF 22 µF 0.001 µF 22 µF 47 kΩ 47 kΩ MN662785TBUC [D/A Converter Application Circuit] 76 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz (2) AC characteristics Limits Parameter Symbol Conditions Unit Min Typ Max Reset Timing (Note 13) C44 NRST pulse width tNRSTL ms 200 Power Supply Ripple Noise (Note 14) C45 Ripple amplitude VRIP 15 mV[p-p] Ripple noise C46 amplitude V NZ 50 mV[p-p] Note 13) When the power is turned on, reset with the NRST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within ±10% of error of the specified oscillator frequency. When designing, be careful to eliminate noise from the reset line as much as possible. tNRSTL NRST Note 14) 0.2VDD 0.2VDD The permissible ripple and noise of power supply to this IC are guaranteed on condition that the ripple frequency range is between 50 Hz and 100 Hz, the noise frequency is at 500 kHz, and that both ripple and noise are sine wave signals as shown below. Pay utmost attention to these ripple signal and noise signal because they may exceed the permissible values under the influence of the location of peripheral parts. Noise frequency: 500 kHz VRIP VNZ Ripple frequency: 50 Hz to 100 Hz SDD00026AEM 77 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min T yp Max C47 Rise time tRA 100 ns C48 Fall time tFA 100 ns C49 Rise time tRB 50 ns C50 Fall time tFB 50 ns MCLK MLD 0.8VDD 0.2VDD 0.8VDD 0.2VDD tRA SBCK tFA 0.8VDD 0.2VDD 0.8VDD 0.2VDD tRB tFB SDD00026AEM 78 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min T yp Max Microcomputer Instruction Input Timing 1.1 C51 Clock frequency fMCLK C52 Clock pulse width tCH,CL 300 ns C53 Data setup time tDSU 300 ns C54 Data hold time tDH 300 ns C55 Delay time t LD D 300 ns C56 Latch pulse width tLDW 0.5 5 MHz µs 1/f MCLK MCLK tCH tCL MDATA tDSU tDH MLD tLDD SDD00026AEM tLDW 79 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Subcode Interface (1) Typ Max (FSEL＝L) C57 Clock width tCK, tSQ 700 ns High-level C58 pulse width Low-level C59 pulse width tCKH, tSQH 300 ns tCKL, tSQL 300 ns C60 Delay time tSBD, tSQD 250 ns tSD 150 ns C61 Setup delay time Subcode Interface (2) (FSEL＝H) C62 Clock width tCK, tSQ 500 ns High-level C63 pulse width Low-level C64 pulse width tCKH, tSQH 200 ns tCKL, tSQL 200 ns C65 Delay time tSBD, tSQD 150 ns tSD 150 ns C66 Setup delay time SDD00026AEM 80 MN662785TBUC tCK tCKL SBCK tCKH SUBC tSD tSBD NCLDCK tSQ tSQL tSQH SQCK SUBQ tSQD SDD00026AEM 81 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min STAT output Interface (1) Typ Max (FSEL＝L) C67 Clock width tMT 909 ns C68 High-level pulse width tMTH 300 ns C69 Low-level pulse width tMTL 300 ns C70 Delay time tMTD STAT output Interface (2) 250 ns (FSEL＝H) C71 Clock width tMT 909 ns C72 High-level pulse width tMTH 300 ns C73 Low-level pulse width tMTL 300 ns C74 Delay time tMTD 150 ns tMT tMTL tMTH MCLK STAT tMTD SDD00026AEM 82 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min STAT output Interface (3) (FSEL＝L) Typ Max (Note 15) C75 Clock width tMT 909 ns C76 High-level pulse width tMTH 300 ns C77 Low-level pulse width tMTL 300 ns C78 Delay time tMTD STAT output Interface (4) 250 (FSEL＝H) ns (Note 15) C79 Clock width tMT 909 ns C80 High-level pulse width tMTH 300 ns C81 Low-level pulse width tMTL 300 ns C82 Delay time tMTD 150 ns Note 15) STAT output data switching with MCLK when using 75h command tMT tMTH tMTL MCLK STAT tMTD SDD00026AEM 83 MN662785TBUC VDD＝3.3 V, VSS＝0 V AVDD＝3.3 V, AVSS＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max D/A output Interface (1) C83 Clock width tBCLK 354 ns C84 High-level pulse width tBCLKH 177 ns C85 Low-level pulse width tBCLKL 177 ns C86 Setup time tST 70 ns C87 Hold time tHD 70 ns Normal-speed playback mode D/A output Interface (2) C88 Clock width tBCLK 177 ns C89 High-level pulse width tBCLKH 88.5 ns C90 Low-level pulse width tBCLKL 88.5 ns C91 Setup time tST 50 ns C92 Hold time tHD 50 ns 2x-speed playback mode tBCLK tBCLKL tBCLKH BCLK1/BCLK2 SRDATA1/SRDATA2 LRCK1/LRCK2 tST SDD00026AEM tHD 84 MN662785TBUC VDD＝3.3 V, VSS＝0 V AVDD＝3.3 V, AVSS＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max D/A converter input timing C93 BCLK frequency C94 BCLK pulse width C95 fBCLK 4 MHz tCH, tCL 100 ns Data setup time tDSU 65 ns C96 Data hold time tDH 65 ns C97 LRCK frequency fLRCK C98 BCLK-LRCK timing tBL, tLB kHz 44.1 ns 65 1/fBCLK IBCLK tCH tCL ISRDATA tDSU tDH ILRCK tBL tLB tBL tLB 1/fLRCK SDD00026AEM 85 MN662785TBUC DVDD1,2＝3.3 V, DVSS1,2＝0 V AVDD1,2＝3.3 V, AVSS1,2＝0 V Ta＝−40°C to ＋85°C fX1＝33.8688 MHz Limits Parameter Symbol Conditions Unit Min Typ Max DRAM Interface C99 NRAS low-level pulse width trasl C100 NRAS high-level pulse width trash C101 NCAS0 / NCAS1 low-level pulse tcasl C102 tcash width NCAS0 / NCAS1 high-level pulse width tcy 6 tcy 2 tcy 4 tcy 4 C103 NRAS address setup time trads 1 tcy C104 NCAS0 / NCAS1 address hold time tradh 1 tcy C105 NCAS0 / NCAS1 address setup time tcads 2 tcy C106 NCAS0 / NCAS1 address hold time tcadhw 3 tcy C107 NCAS0 / NCAS1 data setup time tcwds 3 tcy C108 NCAS0 / NCAS1 data valid time tcadv 120 ns C109 NRAS data valid time tradv 300 ns C110 Data hold time tcadhr 0 ns C111 NWE delay time twcd 3 tcy C112 NWE pulse width twel 5 tcy C113 tref 16 Mbits, full bits 5.9 ms C114 Refresh period tref 16 Mbits, 4-bit compression 23.3 ms C115 tref 4 Mbits, full bits 3.0 ms tref 4 Mbits, 4-bit compression 11.7 ms C117 tref 1 Mbit, full bits 1.5 ms C118 tref 1 Mbit, 4-bit compression 5.9 ms C116 (Playback fs＝44.1 kHz) Memory system ON with decode sequence executed. tcy: One system clock cycle which is indicated as 1/(16.9344 MHz) seconds. SDD00026AEM 86 MN662785TBUC DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A9, D0 to D3) ・Write Timing trash trasl NRAS tcash trcd tcasl NCAS0 (NCAS1) trads tradh tcads A0 to A9 tcwds tcadhw D0 to D3 (WRITE) tcwdh twcd NWE (WRITE) twel ・Read Timing trash trasl NRAS tcash trcd tcasl NCAS0 (NCAS1) trads tradh tcads A0 to A9 tcadv tcadhr tradv D0 to D3 (READ) NWE (READ) "H" SDD00026AEM 87 MN662785TBUC Package Dimensions (Unit: mm) • LQFP080-P-1414A (lead-free package) 16.00±0.20 14.00±0.20 60 41 40 80 21 0.30±0.05 0.13 M 0.10 16.00±0.20 (1.00) 0.15±0.05 0.65 0.10±0.10 (0.825) 20 1.70 max. 1 1.40±0.10 14.00±0.20 (0.825) 61 0° to 10° 0.50±0.20 Seating plane SDD00026AEM 88 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book. (4) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (5) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 MAY