ISL6525 TM Data Sheet March 2001 Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller The ISL6525 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N Channel MOSFETs in a synchronous-rectified buck topology. The ISL6525 integrates all of the control, output adjustment, monitoring and protection functions into a single package. A programmable delay time for the PGOOD signal makes it especially suitable for the VTT regulation in VRM8.5 applications. The output voltage of the converter can be precisely regulated to as low as 1.20V, with a maximum tolerance of ±1% over temperature and line voltage variations. The ISL6525 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The ISL6525 protects against over-current conditions by inhibiting PWM operation. The ISL6525 monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. File Number 4998.1 Features • Drives Two N-Channel MOSFETs • Operates From +5V or +12V Input • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation - 1.20V Internal Reference - ±1% Over Line Voltage and Temperature • Programmable delay for PGOOD signal • Over-Current Fault Monitor - Does Not Require Extra Current Sensing Element - Uses MOSFETs rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to Over 1MHz • 14 Pin, SOIC Package Applications • Power Supply for Various Microprocessors • VTT Regulation for VRM8.5 Ordering Information • High-Power 5V to 3.xV DC-DC Regulators PART NUMBER ISL6525CB TEMP. RANGE (oC) 0 to 70 PACKAGE 14 Ld SOIC PKG. NO. M14.15 • Low-Voltage Distributed Power Supplies Pinout ISL6525 (SOIC) TOP VIEW 1 RT 1 14 DELAY OCSET 2 13 VCC SS 3 12 LGATE COMP 4 11 PGND FB 5 10 BOOT GND 6 9 UGATE PGOOD 7 8 PHASE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved ISL6525 Typical Application 12V +5V OR +12V VCC OCSET SS MONITOR AND PROTECTION BOOT RT OSC UGATE PHASE ISL6525 +VO REF FB PVCC +12V LGATE - + + - PGND COMP GND Block Diagram VCC POWER-ON RESET (POR) 110% + DELAY - PGOOD 90% VCC 10µA + - 10µA SOFTSTART + - OCSET 200µA OVERCURRENT BOOT 4V UGATE REFERENCE PHASE PWM COMPARATOR DACOUT + - + - ERROR AMP FB SS GATE INHIBIT CONTROL LOGIC PWM LGATE PGND COMP GND OSCILLATOR RT 2 ISL6525 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . +15.0V Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead tips only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS EN = VCC; UGATE and LGATE Open - 5 - mA EN = 0V - 50 100 µA Rising VCC Threshold VOCSET = 4.5VDC - - 10.4 V Falling VCC Threshold VOCSET = 4.5VDC 8.2 - - V Enable - Input threshold Voltage VOCSET = 4.5VDC 0.8 - 2.0 V - 1.27 - V VCC SUPPLY CURRENT Nominal Supply ICC Shutdown Supply POWER-ON RESET Rising VOCSET Threshold OSCILLATOR Free Running Frequency RT = OPEN, VCC = 12 185 200 215 kHz Total Variation 6kΩ < RT to GND < 200kΩ -15 - +15 % - 1.9 - VP-P 1.188 1.20 1.212 V - 88 - dB - 15 - MHz - 6 - V/µs 350 500 - mA - 5.5 10 W 300 450 - mA - 3.5 6.5 W 170 200 230 µA - 10 - µA 5.5 10 14.5 µA - 2 - V ∆VOSC Ramp Amplitude RT = OPEN REFERENCE Reference Voltage ERROR AMPLIFIER DC Gain Gain-Bandwidth Product GBW Slew Rate SR COMP = 10pF GATE DRIVERS Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V Upper Gate Sink RUGATE ILGATE = 0.3A Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V Lower Gate Sink RLGATE ILGATE = 0.3A IOCSET VOCSET = 4.5VDC PROTECTION OCSET Current Source Soft Start Current ISS PGOOD DELAY Discharge Current Source NMOS gate threshold voltage 3 ISL6525 Typical Performance Curves 70 RT PULLUP TO +12V 1000 60 CGATE = 3300pF IVCC (mA) RESISTANCE (kΩ) 80 100 RT PULLDOWN TO VSS 50 40 CGATE = 1000pF 30 20 10 CGATE = 10pF 10 10 100 SWITCHING FREQUENCY (kHz) 1000 FIGURE 1. RT RESISTANCE vs FREQUENCY 0 100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) 900 1000 FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY Functional Pin Descriptions GND (Pin 6) RT (Pin 1) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 6 5 • 10 Fs ≈ 200kHz + --------------------R T ( kΩ ) (RT to GND) Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation.: 7 4 • 10 Fs ≈ 200kHz – --------------------R T ( kΩ ) (RT to 12V) PGOOD (Pin 7) PGOOD is an open-drain output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within ±10% of the set voltage. A delay time can be programmed using the DELAY pin (pin 14). See Pin 14 description for more information. PHASE (Pin 8) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. UGATE (Pin 9) OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200µA current source (IOCS), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: I OCS • R OCSET I PEAK = -------------------------------------------r DS ( ON ) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. BOOT (Pin 10) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. PGND (Pin 11) An over-current trip cycles the soft-start function. This is the power ground connection. Tie the lower MOSFET source to this pin. SS (Pin 3) LGATE (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 10µA current source, sets the softstart interval of the converter. Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. COMP (Pin 4) and FB (Pin 5) Provide a 12V bias supply for the chip to this pin. COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. 4 VCC (Pin 13) DELAY (Pin 14) This pin is used to program the delay of the PGOOD (pin 7) signal by placing a capacitor between this pin and GND or VCC. The external capacitor only delays the rising edge of ISL6525 Initialization The ISL6525 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see overcurrent protection). The POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. Soft Start The POR function initiates the soft start sequence. An internal 10µA current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft start interval with CSS = 0.1µF. Initially the clamp on the error amplifier (COMP pin) controls the converter’s output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator’s triangle wave. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2 . With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the reference voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The over-current function protects the converter from a shorted output by using the upper MOSFETs on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200µA (typical) current sink develops a voltage across ROCSET that is reference to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10µA current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this operation with an overload condition. Note that, in this particular application, the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured average input power for the conditions of Figure 4 is 2.5W. SOFT-START Functional Description Over-Current Protection OUTPUT INDUCTOR PGOOD signal, not the falling edge. An internal hysteresis guarantees glitch-free transition of PGOOD. Refer to Programming PGOOD Delay Time section for more information. 4V 2V 0V 15A 10A 5A 0A TIME (20ms/DIV.) FIGURE 4. OVER-CURRENT OPERATION SOFT-START (1V/DIV.) The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET • R OCSET I PEAK = --------------------------------------------------r DS ( ON ) OUTPUT VOLTAGE (1V/DIV.) 0V 0V t1 t2 t3 TIME (5ms/DIV.) FIGURE 3. SOFT-START INTERVAL where IOCSET is the internal OCSET current source (200µA - typical). The OC trip point varies mainly due to the MOSFETs rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 5 ISL6525 3. Determine PEAK for I PEAK > I OUT ( MAX ) + ( ∆I ) ⁄ 2 , where ∆I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Programming PGOOD Delay Time The PGOOD rising edge delay can be programmed by connecting a small capacitor CDELAY between the DELAY pin and GND. The rising-edge delay is determined by the 10µA discharging current source IDISCH , the voltage difference between VCC and the gate threshold voltage VTH of the opendrain FET, and the capacitor value. The delay time tDELAY can be calculated with the following equation, C DELAY ( VCC – V TH ) t DELAY = ----------------------------------------------------------I DISCH Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL6525 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6525 must be sized to handle up to 1A peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. +VIN BOOT D1 Q1 CBOOT SS VOUT PHASE ISL6525 +12V VTH is typically 2V, VCC is 12V, and IDISCH is 10µA. Thus, 1nF of CDELAY leads to 1ms of delay time typically. LO LOAD 2. The minimum IOCSET from the specification table. CO Q2 VCC CVCC CSS GND Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES VIN OSC DRIVER PWM COMPARATOR LO - ∆VOSC DRIVER + VOUT PHASE CO ESR (PARASITIC) VIN ZFB VE/A ISL6525 - ZIN + Q1 LO VOUT PHASE REFERENCE DETAILED COMPENSATION COMPONENTS CIN LGATE ERROR AMP Q2 D2 CO ZFB LOAD UGATE PGND C1 RETURN FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 6 should be located as close together as possible. 6 VOUT C2 ZIN C3 R2 R3 R1 COMP FB + ISL6525 REF FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN ISL6525 Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Modulator Break Frequency Equations 1 F LC = --------------------------------------2π • L O • C O 1 F ESR = --------------------------------------------2π • ( ESR • C O ) constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 100 FZ1 FZ2 FP1 FP2 80 OPEN LOOP ERROR AMP GAIN 60 GAIN (dB) Feedback Compensation 40 20 20LOG (R2/R1) 20LOG (VIN/∆VOSC) 0 COMPENSATION GAIN MODULATOR GAIN -20 CLOSED LOOP GAIN -40 FLC -60 10 100 1K FESR 10K 100K 1M 10M FREQUENCY (Hz) The compensation network consists of the error amplifier (internal to the ISL6525) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: Component Selection Guidelines Compensation Break Frequency Equations Output Capacitor Selection 1 F Z1 = ---------------------------------2π • R 2 • C1 1 F P1 = ------------------------------------------------------C1 • C2 2π • R2 • ---------------------- C1 + C2 1 F Z2 = -----------------------------------------------------2π • ( R1 + R3 ) • C3 1 F P2 = ---------------------------------2π • R3 • C3 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak do to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is 7 FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0µF ceramic capacitors in the 1206 surface-mount package. Pentium® is a registered trademark of Intel Corporation. ISL6525 Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT ∆I = -------------------------------- • ---------------Fs x L V IN ∆VOUT = ∆I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6525 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = -------------------------------V IN – V OUT L O × I TRAN t FALL = ------------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these 8 equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The ISL6525 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET exhibits switching losses, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on. PUPPER = IO2 x rDS(ON) x D + 1 Io x VIN x tSW x Fs 2 PLOWER = IO2 x rDS(ON) x (1 - D) where: D is the duty cycle = VO / VIN, tSW is the switching interval, and Fs is the switching frequency. ISL6525 These equations assume linear voltage-current transitions and do not adequately model power loss due the reverserecovery of the lower MOSFETs body diode. The gate-charge losses are dissipated by the ISL6525 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. power and +12 VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to PVCC. +12V +5V OR LESS VCC ISL6525 BOOT Q1 UGATE Standard-gate MOSFETs are normally recommended for use with the ISL6525. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFETs absolute gate-tosource voltage rating determine whether logic-level MOSFETs are appropriate. PVCC + +12V DBOOT + VCC +5V OR +12V VD BOOT ISL6525 CBOOT UGATE PVCC + NOTE: VG-S ≈ VCC - VD +5V OR +12V Q2 LGATE D2 NOTE: VG-S ≈ PVCC PGND GND FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION Figure 10 shows the upper gate drive supplied by a direct connection to VCC . This option should only be used in converter systems where the main input voltage is +5 VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main 9 Q2 D2 NOTE: VG-S ≈ PVCC GND FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION Schottky Selection Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency could slightly decrease as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. ISL6525 DC-DC Converter Application Circuit Q1 PHASE +5V OR +12V LGATE PGND Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC . The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. A logic-level MOSFET can only be used for Q1 if the MOSFETs absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . For Q2, a logic-level MOSFET can be used if its absolute gate-tosource voltage rating exceeds the maximum voltage applied to PVCC. NOTE: VG-S ≈ VCC - 5V PHASE The figure below shows an application circuit of a DC-DC converter. Detailed information on the circuit, including a complete Bill-of-Materials and circuit board description, can be found in application note AN9916. ISL6525 12VCC VIN CIN 1µF 330µF/25V V OUT CDELAY 1000pF 1µF VCC 10K PGOOD DELAY 7 13 6 14 MONITOR AND PROTECTION SS 3 4.99K 10 BOOT RT 1 9 UGATE Q1 OSC 0.1µF U1 ISL6525 SPARE REF 0.1µF L1 8 PHASE VOUT 13 VCC 12 LGATE - + + 5 FB 1N4148 2 OCSET 11 PGND - 4 6 COMP SPARE Q2 GND 33pF 20K 6.8nF C16 1K SPARE SPARE Component Selection Notes: CIN - 330µF 25W VDC, Rubycon ZA series or equivalent COUT - 1000µF 6.3W VDC, Rubycon ZA series or equivalent L1 - Core: Micrometals T44-52; Winding: 12 Turns of 19AWG Q1 - Intersil MOSFET; HUF76121D Q2 - Intersil MOSFET; HUF76129D FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT 10 COUT 1000µF ISL6525 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA H 0.25(0.010) M 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- α e B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e A1 B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 14 0o 14 8o 0o 7 8o Rev. 0 12/93 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 11 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369