ISL28470EVAL1Z Evaluation Board User’s Guide ® Application Note February 12, 2007 Introduction V+ The ISL28470EVAL1Z evaluation board is a design platform containing all the circuitry needed to characterize critical performance parameters of the ISL28470 Quad Instrumentation Amplifier using a variety of user defined test circuits. AN1289.0 GND J3 V+ J2 C2 + 4.7µF The ISL28470 is a quad channel instrumentation amplifier optimized for 2.4V to 5V single supplies. The device features an Input Range Enhancement Circuit (IREC) which maintains CMRR performance for input voltages equal to the positive supply and down to 50mV above the negative supply rail. The input signal is capable of swinging above the positive supply rail and to the negative supply with only a slight degradation of the CMRR performance. The output operation is rail to rail. The ISL28270 is compensated for a minimum gain of 100. R1 0 0 2 1 V- C1 + 4.7µF D1 2 R3 0 2 VP J1 R2 D2 1 R4 V- C9 1 0.1µF 2 C10 1 0 VM 0.1µF FIGURE 1. POWER SUPPLY CIRCUIT Reference Documents Power Supplies (Refer to Figure 1) • ISL28470 Data Sheet, FN6260 External power connections are made through the +V, -V and Ground connections on the evaluation board. For single supply operation, the -V and Ground pins are tied together to the power supply negative terminal. For split supplies, +V and -V terminals connect to their respective power supply terminals. De-coupling capacitors, C1 and C2, connect to ground through R1 and R2, 0Ω resistors. Resistors R3 and R4 are 0Ω but can be changed by the user to provide power supply filtering, or to reduce the voltage rate-of-rise to less than ±1V/µs. Anti-reverse diodes D1 and D2 protect the circuit in the case of accidental polarity reversal. Evaluation Board Key Features The ISL28470EVAL1Z is designed to be operated from a single supply (+2.4VDC to +5VDC), or from split supplies (±1.2VDC to ±2/5V). The board is configured for 4 independent instrumentation amplifiers connected for a closed loop gain of 101 with inverting and non-inverting high impedance terminated with 100k resistors to ground. Each amplifier contains it’s own VREF input to establish an input common mode reference. An ENABLE select switch is provided for each amplifier to be used to save power by powering the device down. VP ENABLE IN+(x) IN+ IN+ 1/4 ISL28470 + IN- IN- 0Ω VOUT(x) 100kΩ IN-(x) FB+ + -V VCM FB- 10kΩ 100kΩ VREF(x) VREF RG RF 1kΩ 100kΩ VM GND FIGURE 2. BASIC AMPLIFIER CONFIGURATION 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1289 Amplifier Configuration (Figure 2) VREFA The schematic of each of the 4 Op Amps with the components supplied is shown in Figure 2. The circuit implements a differential input instrumentation amp with a closed loop gain of 101. The circuit can operate from a single 2.4VDC to +5VDC supply, or from dual supplies from ±1.2VDC to ±2.5VDC.The output common mode reference is applied to the VREF pin, and has a range from ground (VM) to VP. R6 V- DNP R5 V+ DNP VREFA C3 J8 User-selectable Options (Figure 3) Component pads are included to enable a variety of userselectable circuits to be added to the amplifier differential inputs, the VREF input, and the amplifier feedback loop. A voltage divider and filter option can be added to establish a power supply tracking common mode reference at the VREF input, or a coaxial connection to the ISL28470 FB+ pin can be made at the FB+ BNC connector. The differential inputs have additional resistor placements for adding input attenuation, or to establish input DC offsets through the VREF pin. 1 J4 OPEN R13 R15 DNP DNP FB+A J9 R18 J10 0 R19 DNP R21 -INA +INA 0 R22 DNP R14 0 VREFA R17 R16 DNP 1k R20 100k R23 100k FIGURE 3. COMPONENT-SELECTABLE OPTIONS ISL28470EVAL1Z Components Parts List DEVICE # DESCRIPTION COMMENTS C1, C2 CAP-TANTALUM, SMD, D,4.7µF, 50V, 10%, LOW ESR, ROHS Power Supply Decoupling C7, C8 CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R, ROHS Power Supply Decoupling C9, C10 CAP, SMD, 0805, 0.1µF, 25V,10%, X7R, ROHS Power Supply Decoupling C3-C6 CAP, SMD, 0805, DNP-PLACE HOLDER, ROHS Optional VREF Filter Not Populated C11-C18 CAP, SMD, 0805, DNP-PLACE HOLDER, ROHS Optional Amplifier Feedback Caps Not Populated D1, D2 DIODE-RECTIFIER, SMD, MELF, 2 Ld, 50V, 1A, GPP, ROHS Reverse Power Protection U1 ISL28470FAZIC INSTRUMENTATION AMP, 28P, QSOP, ROHS R13, R14-R16, R19, R22, R24-R27, R30, R33, RESISTOR, SMD, 0603, 0.1%, MF, DNP-PLACE HOLDER R35-R38,R41, R44, R46-R49, R52, R55, R69, R71, R73, R75 User Selectable Resistors Not Populated R18, R21, R29, R32, R40, R43, R51, R54, R58, RES, SMD, 0603, 0Ω, 1/16W, TF, ROHS R60, R63, R66 0Ω User Selectable Resistors R17, R28, R39, R50 RES, SMD, 0603, 1k, 1/10W, 1%, TF, ROHS RG Gain Resistors R59, R61, R65, R67, R70, R72, R74, R76 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS R20, R23, R31, R34, R42, R45, R53, R56, R57, RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS R62, R64, R68 RF Gain Resistors R1-R4 RES, SMD, 0805, 0Ω, 1/8W, TF, ROHS 0Ω User Selectable Resistors R5-R12 RES, SMD, 0805, DNP-PLACE HOLDER, ROHS User Selectable Resistors Not Populated S1-S4 SWITCH-SEALED MINI TOGGLE, TH, 3P, SP, ON/NONE/ON, Enable/Disable Select Switches GOLD 2 AN1289.0 February 12, 2007 Application Note 1289 ISL28470EVAL1Z Top View 3 AN1289.0 February 12, 2007 Application Note 1289 ISL28470EVAL1Z Schematic Diagram ZONE J3 DNP VREFC R7 V+ V- R6 DNP DNP VREFB J2 V+ C2 R5 DNP V+ 4.7UF 1 VREFA VP 2 R1 0 2 1 C9 1 J17 FB+D J18 -IND J19 +IND C10 1 VM 0.1UF R16 DNP 2 R51 0 R54 0 VREFD R50 1K J20 R59 10K C12 1 OPEN 2 VOUT B R61 10K R62 100K C13 2 1 OPEN J22 R63 0 VOUT C R65 10K R64 100K C15 OPEN R38 DNP J23 R66 0 R68 100K C17 OPEN R70 10K S1 R72 10K R74 10K R76 10K R69 DNP 3 2 ENABLE VP 1 ENA VOUT D R67 10K Generic Pack. M28.15 VOUT A J21 R60 0 C14 1 OPEN SSOP28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 2 R31 100K R34 100K R48 DNP U1 0.01UF C16 OPEN R27 DNP R25 0 R30 DNP R46 DNP VM C8 C7 0.01UF R57 100K C11 2 1 OPEN C18 OPEN R43 0 R39 1K VP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R49 DNP J16 +INC VREFC R42 100K R40 0 R37 DNP R45 100K R35 DNP J15 -INC 2 DISABLE R53 100K J14 R28 1K R56 100K FB+C R33 DNP +INB R32 0 R36 0 J13 R29 0 VREFB R41 DNP -INB D1 R58 R26 DNP R44 DNP J12 R24 DNP R47 0 FB+B 0 J11 V- C1 4.7UF R21 R52 DNP J10 +INA DATE 1K R55 DNP -INA VREFA R17 R20 100K R18 0 R23 100K J9 R15 DNP R19 DNP R13 DNP R22 DNP J8 R14 0 0.1UF FB+A DESCRIPTION J1 R2 0 D2 LTR V- R4 0 V- R8 C3 OPEN VREFD R9 V+ DNP C5 OPEN C6 OPEN DNP C4 OPEN R11 V+ V- R10 DNP DNP V- R12 GND R3 0 VREFA J4 J6 VREFB 1 VREFC J5 VREFD J7 V+ S2 R71 DNP ENABLE VP ENB S3 DISABLE R73 DNP ENABLE VP DISABLE ENC S4 R75 DNP REV: TITLE: ENABLE ISL28470EVAL1Z VP END DISABLE ENGINEER: ROBERT POSPISIL DRAWN BY: Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 4 AN1289.0 February 12, 2007 DATE 01 SHEE