INTERSIL ISL28470EVAL1Z

ISL28270, ISL28273, ISL28470
®
Data Sheet
April 13, 2007
Micropower, Single Supply, Rail-to-Rail
Input and Output (RRIO) Instrumentation
Amplifier
The ISL28270 and ISL28273 are dual channel micropower
instrumentation amplifiers (in-amps) and the ISL28470 is a
Quad-channel in-amp optimized for low 2.4V to 5V single
supplies.
All three devices feature an Input Range Enhancement
Circuit (IREC) which maintains CMRR performance for input
voltages equal to the positive supply and down to 50mV
above the negative supply rail. The input signal is capable of
swinging above the positive supply rail and to 10mV above
the negative supply with only a slight degradation of the
CMRR performance. The output operation is rail to rail.
FN6260.2
Features
• 60µA supply current per channel ISL28270
• 150µV max offset voltage
• 2nA max input bias current ISL28270
• 110dB CMRR, PSRR
• 0.7µV/°C offset voltage temperature coefficient
• 240kHz -3dB bandwidth (G = 100) ISL28270, ISL28470
• 230kHz -3dB bandwidth (G = 10) ISL28273
• 0.5V/µs slew rate
• Single supply operation
• Rail-to-rail input and output (RRIO)
The ISL28273 is compensated for a minimum gain of 10 or
more. For higher gain applications, the ISL28270 and
ISL28470 are compensated for a minimum gain of 100. The
in-amps have bipolar input devices for best offset and
excellent 1/f noise performance. The amplifiers can be
operated from one lithium cell or two Ni-Cd batteries.
• Input is capable of swinging above V+ and below V(ground sensing)
Ordering Information
Applications
PART NUMBER
(Note)
PART
MARKING
TAPE &
REEL
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28270IAZ
(Note)
28270 IAZ
97/Tube 16 Ld QSOP MDP0040
(Pb-free)
ISL28270IAZ-T13
(Note)
28270 IAZ
13”
16 Ld QSOP MDP0040
(1k pcs) (Pb-free)
Coming Soon
ISL28273FAZ
(Note)
28273 FAZ
97/Tube 16 Ld QSOP MDP0040
(Pb-free)
Coming Soon
ISL28273FAZ-T7
(Note)
28273 FAZ
ISL28470FAZ
(Note)
ISL28470FAZ
48/Tube 28 Ld QSOP M28.15
(Pb-free)
ISL28470FAZ-T7
(Note)
ISL28470FAZ
7”
28 Ld QSOP M28.15
(1k pcs) (Pb-free)
7”
16 Ld QSOP MDP0040
(1k pcs) (Pb-free)
• Output sources and sinks ±29mA load current
• 0.5% gain error
• Pb-free plus anneal available (RoHS compliant)
• Battery or solar-powered systems
• Strain gauge
• Sensor signal conditioning
• Medical devices
• Industrial instrumentations
Related Literature
• AN1290, ISL2827xINEVAL1Z Evaluation Board User’s
Guide
• AN1298, Instrumentation Amplifier Application Note
ISL28270INEVAL1Z Evaluation Platform
(Note)
ISL28273INEVAL1Z Evaluation Platform
Coming Soon
ISL28470EVAL1Z
Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL28270, ISL28273, ISL28470
Pinouts
ISL28470
(28 LD QSOP)
TOP VIEW
ISL28270, ISL28273
(16 LD QSOP)
TOP VIEW
16 V+
OUT_A 1
OUT_A 2
15 OUT_B
FB+_A 2
FB+_A 3
14 FB+_B
FB-_A 3
26 FB-_D
NC 1
-+
+ -
28 OUT_D
+ -
-+
27 FB+_D
FB-_A 4
13 FB-_B
IN-_A 4
25 IN-_D
IN-_A 5
12 IN-_B
IN+_A 5
24 IN+_D
IN+_A 6
11 IN+_B
EN_A 6
23 EN_D
EN_A 7
10 EN_B
V- 7
9
V- 8
NC
22 V-
EN_B 8
21 EN_C
IN+_B 9
20 IN+_C
IN-_B 10
19 IN-_C
18 FB-_C
FB-_B 11
FB+_B 12
OUT_B 13
NC 14
2
+ -
- +
17 FB+_C
16 OUT_C
15 NC
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs
Input Current (IN, FB) ISL28270, ISL28470 . . . . . . . . . . . . . . . 5mA
Differential Input Voltage (IN, FB) ISL28270, ISL28470 . . . . . . 0.5V
Input Current (IN, FB) ISL28273 . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input (IN, FB) Voltage ISL28273 . . . . . . . . . . . . . . . 1.0V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance
θJA (°C/W)
16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . .
112
28 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . .
79
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VOS
TCVOS
IOS
V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +125°C.
DESCRIPTION
Input Offset Voltage
CONDITIONS
ISL28270, ISL28470
MIN
TYP
MAX
UNIT
-150
-225
±35
150
225
µV
ISL28273
TBD
µV
Input Offset Voltage Temperature
Coefficient
Temperature = -40°C to +125°C
0.7
µV/°C
Input Offset Current between IN+ and
IN-, and between FB+ and FB-
ISL28270
-1
-1.5
±0.25
1
1.5
nA
ISL28470
-1.5
-2.0
±0.25
1.5
2
nA
ISL28273
IB
Input Bias Current (IN+, IN-, FB+, and
FB- terminals)
TBD
ISL28270
-2.0
-2.5
±0.5
2.0
2.5
nA
ISL28470
-2.5
-3.0
±0.5
2.5
3.0
nA
ISL28273
eN
Input Noise Voltage
TBD
nA
3.5
µVP-P
3.5
µVP-P
60
nV/√Hz
210
nV/√Hz
0.48
pA/√Hz
0.65
pA/√Hz
ISL28270, ISL28470
3
MΩ
ISL28273
15
MΩ
ISL28270, ISL28470
f = 0.1Hz to 10Hz
ISL28273
Input Noise Voltage Density
ISL28270, ISL28470
fo = 1kHz
ISL28273
iN
Input Noise Current Density
ISL28270, ISL28470
fo = 1kHz
ISL28273
RIN
VIN
Input Resistance
Input Voltage Range
3
nA
V+ = 2.4V to 5.0V
0
V+
V
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Electrical Specifications
PARAMETER
CMRR
V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
Common Mode Rejection Ratio
CONDITIONS
ISL28270
VCM = 0.05V to 5V
MIN
TYP
90
TBD
110
dB
TBD
dB
90
85
110
dB
90
TBD
110
dB
TBD
dB
110
dB
+0.5
%
TBD
%
ISL28273
ISL28470
PSRR
Power Supply Rejection Ratio
ISL28270
V+ = 2.4V to 5V
ISL28273
ISL28470
EG
Gain Error
ISL28270, ISL28470
90
65
RL = 100kΩ to 2.5V
ISL28273
VOUT
Maximum Voltage Swing
Output low, 100kΩ to 2.5V
Output low, 1kΩ to 2.5V
SR
-3dB BW
IS,DIS
4
10
mV
130
250
300
mV
4.990
4.996
V
Output high, 1kΩ to GND
4.75
4.70
4.88
V
Slew Rate
RL = 1kΩ to GND
0.3
0.25
0.5
-3dB Bandwidth
ISL28270, ISL28470
Supply Current, Enabled
Supply Current, Disabled
Gain = 100
240
kHz
Gain = 200
84
kHz
Gain = 500
30
kHz
Gain = 1000
13
kHz
Gain = 10
265
kHz
Gain = 20
100
kHz
Gain = 50
25
kHz
Gain = 100
13
kHz
156
195
µA
ISL28470 - A, B, C and D channels enabled,
EN = V-
260
335
µA
ISL28270 - Both A and B channels disabled,
EN = V+
4
7
9
µA
ISL28470 - A, B, C and D channels disabled,
EN = V+
10
12
15
µA
VENL
EN Pin for Power-On
IENH
EN Input Current High
EN = V+
IENL
EN Input Current Low
EN = V-
4
V/µs
120
EN Pin for Shut-down
Minimum Supply Voltage
0.7
0.75
ISL28270 - Both A and B channels enabled,
EN = V-
VENH
V+
UNIT
Output high, 100kΩ to 2.5V
ISL28273
IS,EN
MAX
2
2.4
V
0.8
V
0.8
1
1.3
µA
26
50
100
nA
V
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Electrical Specifications
PARAMETER
ISC
V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
CONDITIONS
Short Circuit Output Current
V+ = 5V, RLOAD = 10Ω
MIN
TYP
±20
±18
±29
mA
±8
mA
V+ = 2.4V, RLOAD = 10Ω
MAX
UNIT
Typical Performance Curves
90
70
COMMON-MODE INPUT = VS+
GAIN = 10,000V/V
80
GAIN = 1000
50
GAIN = 2,000V/V
GAIN (dB)
GAIN (dB)
GAIN = 5,000V/V
70
GAIN = 1,000V/V
60
GAIN = 500V/V
50
20
10
1E+00
30
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
60
50
GAIN (dB)
GAIN (dB)
GAIN = 2,000V/V
GAIN = 1,000V/V
GAIN = 500V/V
50
GAIN = 200V/V
30
40
30
20
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 3. ISL28270, ISL28470 FREQUENCY RESPONSE vs
CLOSED LOOP GAIN (V+ = 5V, VCM = 1/2V+)
5
1E+03
1E+04
1E+05
1E+06
COMMON-MODE INPUT = 1/2V+
GAIN = 1000
GAIN = 200
GAIN = 100
GAIN = 50
GAIN = 100V/V
40
1E+02
GAIN = 500
GAIN = 5,000V/V
60
1E+01
70
GAIN = 10,000V/V
80
GAIN = 10
FIGURE 2. ISL28273 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN (VCM = V+)
COMMON-MODE INPUT = 1/2VS
70
GAIN = 50
FREQUENCY (Hz)
FIGURE 1. ISL28270, ISL28470 FREQUENCY RESPONSE vs
CLOSED LOOP GAIN (V+ = VCM = 5V)
90
GAIN = 100
GAIN = 20
GAIN = 100V/V
1
GAIN = 500
GAIN = 200
40
30
GAIN = 200V/V
40
COMMON-MODE INPUT = V+
60
10
1E+00
GAIN = 20
GAIN = 10
1E+01
1E+02
1E+03
1E+04
FREQUENCY (Hz)
1E+05
1E+06
FIGURE 4. ISL28273 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN (VCM = 1/2V+)
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Typical Performance Curves (Continued)
90
70
COMMON-MODE INPUT = VM +10mV
GAIN = 10,000V/V
80
COMMON-MODE INPUT = VM +10mV
GAIN = 1000
60
GAIN = 500
GAIN = 5,000V/V
GAIN = 2,000V/V
50
GAIN (dB)
GAIN (dB)
70
GAIN = 1,000V/V
60
GAIN = 500V/V
50
30
GAIN = 100V/V
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1E+01
1E+02
1E+03
1E+04
FREQUENCY (Hz)
20
V+ = 3.3V
GAIN (dB)
VS = 3.3V
25
VS = 2.4V
20
AV = 100
RL = 10kΩ
CL = 10pF
RF/RG = 99.02
RF = 221kΩ
RG = 2.23kΩ
0
100
1k
15
10
5
10k
100k
V+ = 2.4V
AV = 10
R = 10kΩ
CL = 10pF
RF/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1M
1k
FIGURE 7. ISL28270, ISL28470 FREQUENCY RESPONSE vs
SUPPLY VOLTAGE
100k
1M
FIGURE 8. ISL28273 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
50
30
CL = 100pF
25
45
CL = 470pF
CL = 47pF
CL = 820pF
20
40
GAIN (dB)
GAIN (dB)
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
CL = 220pF
30
1E+06
V+ = 5V
VS = 5V
30
35
1E+05
FIGURE 6. ISL28273 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN (VCM = V-)
35
GAIN (dB)
GAIN = 10
25
40
5
GAIN = 20
10
1E+00
1M
45
10
GAIN = 50
20
FIGURE 5. ISL28270, ISL28470 FREQUENCY RESPONSE vs
CLOSED LOOP GAIN (V+ = 5V, VCM = 10mV)
15
GAIN = 100
40
30
GAIN = 200V/V
40
GAIN = 200
CL = 56pF
AV = 100
VS = ±2.5V
RL = 10kΩ
RF/RG = 99.02
RF = 221kΩ
RG = 2.23kΩ
25
100
CL = 27pF
15
CL = 2.7pF
10
5
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 9. ISL28270, ISL28470 FREQUENCY RESPONSE vs
CLOAD
6
AV = 10
V+ = 5V
RL = 10kΩ
RF/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. ISL28273 FREQUENCY RESPONSE vs CLOAD
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Typical Performance Curves (Continued)
120
90
80
70
60
80
60
CMRR (dB)
CMRR (dB)
100
CMRR
40
CMRR
50
40
30
20
10
20
0
0
10
100
1k
10k
100k
-10
1M
10
100
FREQUENCY (Hz)
10k
1M
100k
FIGURE 12. ISL28273 CMRR vs FREQUENCY
FIGURE 11. ISL28270, ISL28470 CMRR vs FREQUENCY
140
90
80
120
PSRR+
70
PSRR+
100
60
PSRR (dB)
PSRR (dB)
1k
FREQUENCY (Hz)
80
PSRR-
60
40
50
PSRR-
40
30
20
20
0
10
10
100
1k
10k
FREQUENCY (Hz)
100k
0
10
1M
FIGURE 13. ISL28270, ISL28470 PSRR vs FREQUENCY
100k
1M
2.5
INPUT VOLTAGE NOISE (μV/√Hz)
INPUT VOLTAGE NOISE (nV/√Hz)
1k
10k
FREQUENCY (Hz)
FIGURE 14. ISL28273 PSRR vs FREQUENCY
250
200
150
100
50
100
1
10
100
1k
10k
FREQUENCY (Hz)
FIGURE 15. ISL28270, ISL28470 INPUT VOLTAGE NOISE
SPECTRAL DENSITY (GAIN = 100)
7
100k
2.0
1.5
1.0
0.5
0.0
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 16. ISL28273 INPUT VOLTAGE NOISE SPECTRAL
DENSITY (GAIN = 10)
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Typical Performance Curves (Continued)
5.0
4.5
0.9
CURRENT NOISE (pA/√Hz)
CURRENT NOISE (pA/√Hz)
1.0
0.8
0.7
0.6
0.5
0.4
0.3
1
10
100
1k
10k
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100k
1
10
100
FREQUENCY (Hz)
100k
FIGURE 18. ISL28273 INPUT CURRENT NOISE SPECTRAL
DENSITY (GAIN = 10)
VOLTAGE NOISE (0.5µV/DIV)
TIME (1s/DIV)
TIME (1s/DIV)
FIGURE 19. ISL28270, ISL28470 0.1 Hz TO 10Hz INPUT
VOLTAGE NOISE (GAIN = 100)
FIGURE 20. ISL28273 0.1 Hz TO 10Hz INPUT VOLTAGE NOISE
(GAIN = 10)
400
140
n = 930
135
350
MAX
n = 930
MAX
130
125
300
CMRR (dB)
CURRENT (µA)
10k
VOLTAGE NOISE (0.5µV/DIV)
FIGURE 17. ISL28270, ISL28470 INPUT CURRENT NOISE
SPECTRAL DENSITY (GAIN = 100)
250
200
MEDIAN
120
115
110
105
MEDIAN
MIN
100
150
MIN
MIN
100
-40
1k
FREQUENCY (Hz)
-20
0
95
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 21. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V
ENABLED (RL = INF)
8
90
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 22. CMRR vs TEMPERATURE (VCM = +2.5V TO -2.5V)
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Typical Performance Curves (Continued)
4.90
165
n = 930
155
n = 930
4.89
MAX
145
MAX
MEDIAN
115
105
VOUT (V)
125
OU
PSRR (dB)
135
4.88
4.87
MEDIAN
95
4.86
85
MIN
MIN
75
4.85
-40
65
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 24. POSITIVE VOUT vs TEMPERATURE (RL = 1k,
VS = ±2.5V)
FIGURE 23. PSRR vs TEMPERATURE (VS = ±2.5V)
170
4.9964
n = 930
n = 930
4.9962
160
4.9960
MAX
MEDIAN
140
130
120
MAX
4.9958
4.9956
VOUT (V)
VOUT (mV)
150
4.9954
4.9952
MIN
MEDIAN
4.9950
4.9948
110
MIN
4.9946
100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
4.9944
-40
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 25. NEGATIVE VOUT vs TEMPERATURE (RL = 1k,
VS = ±2.5V)
FIGURE 26. POSITIVE VOUT vs TEMPERATURE (RL = 100k,
VS = ±2.5V)
4.502
n = 930
MAX
4.002
VOUT (mV)
MEDIAN
3.502
MIN
3.002
2.502
2.002
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 27. NEGATIVE VOUT vs TEMPERATURE (RL = 100k, VS = ±2.5V)
9
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Pin Descriptions
ISL28270
ISL28273
ISL28470
16 Ld QSOP 16 Ld QSOP 28 Ld QSOP
PIN NAME
EQUIVALENT
CIRCUIT
PIN FUNCTION
2, 15
2, 15
1, 13
16, 28
OUT_A,B
C_D
Circuit 3
Output Voltage. A complementary Class AB common-source output
stage drives the output of each channel. When disabled, the outputs are
in a high impedance state
3, 14
3, 14
2, 12
17, 27
FB+_A,B
C_D
Circuit 1A,
Circuit 1B
Positive Feedback high impedance terminals. ISL28270 and ISL28470
input circuit is shown in Circuit 1A, and the ISL28273 input circuit is
shown in Circuit 1B.
ISL28273: to avoid offset drift, it is recommended that the terminals of
the ISL28273 are not overdriven beyond 1V and the input current must
never exceed 5mA.
4, 13
4, 13
3, 11
18, 26
FB-_A,B
C_D
Circuit 1A,
Circuit 1B
Negative Feedback high impedance terminals. The FB- pins connect to
an external resistor divider to individually set the desired gain of the inamp. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the
ISL28273 input circuit is shown in Circuit 1B.
ISL28273: to avoid offset drift, it is recommended that the terminals of
the ISL28273 are not overdriven beyond 1V and the input current must
never exceed 5mA.
5, 12
5, 12
4, 10
19, 25
IN-_A,B
C_D
Circuit 1A,
Circuit 1B
High impedance Inverting input terminals. Connect to the low side of the
input source signal. ISL28270 and ISL28470 input circuit is shown in
Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.
ISL28273: to avoid offset drift, it is recommended that the terminals of
the ISL28273 are not overdriven beyond 1V and the input current must
never exceed 5mA.
6, 11
6, 11
5, 9
20, 24
IN+_A,B
C_D
Circuit 1A,
Circuit 1B
High impedance Non-inverting input terminals. Connect to the high side
of the input source signal. ISL28270 and ISL28470 input circuit is shown
in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B.
ISL28273: to avoid offset drift, it is recommended that the terminals of
the ISL28273 are not overdriven beyond 1V and the input current must
never exceed 5mA.
7, 10
7, 10
6, 8
21, 23
EN_A,B
C_D
Circuit 2
Active LOW logic pins. When pulled above 2V, the corresponding
channel turns off and OUT is high impedance. A channel is enabled
when pulled below 0.8V. Built-in pull downs define each EN pin LOW
when left floating.
16
16
7
V+
Circuit 4
Positive Supply terminal shared by all channels.
8
8
22
V-
Circuit 4
Negative Supply terminal shared by all channels. Grounded for single
supply operation.
1, 9
1, 9
14,15
NC
No Connect, pins can be left floating or grounded
V+
V+
V+
IN+
FB+
INFB-
LOGIC
PIN
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
V-
V-
CIRCUIT 1A
V+
CIRCUIT 2
VCIRCUIT 3
CIRCUIT 4
V+
INFB-
IN+
FB+
V-
CIRCUIT 1B
10
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Application Information
Product Description
The ISL28270 and ISL28273 are dual channel micropower
instrumentation amplifiers (in-amps) and the ISL28470 is a
Quad-channel which delivers rail-to-rail input amplification
and rail-to-rail output swing. The in-amps also deliver
excellent DC and AC specifications while consuming only
about 60µA per channel. Because the independent pair of
feedback terminals set the gain and adjust the output 0 level,
the ISL28270, ISL28273 and ISL28470 achieve high CMRR
regardless of the tolerance of the gain setting resistors. The
ISL28270 and ISL28470 are internally compensated for a
minimum gain of 100. The ISL28273 is internally
compensated for a minimum gain of 10.
EN pins are available to independently enable or disable a
channel. When all channels are off, current consumption is
down to typically 4µA.
Input Protection
All input terminals and feedback terminals have internal ESD
protection diodes to both positive and negative supply rails,
limiting the input voltage to within one diode beyond the
supply rails. Input signals originating from low impedance
sources should have current limiting resistors in series with
the IN+ and IN- pins to prevent damaging currents during
power supply sequencing and other transient conditions.
The ISL28270 and ISL28470 have additional back-to-back
diodes across the input terminals and also across the
feedback terminals. If overdriving the inputs is necessary,
the external input current must never exceed 5mA. External
series resistors may be used as an external protection to
limit excessive external voltage and current from damaging
the inputs. On the other hand, the ISL28273 has no clamps
to limit the differential voltage on the input terminals allowing
higher differential input voltages at lower gain applications. It
is recommended, however, that the terminals of the
ISL28273 are not overdriven beyond 1V to avoid offset drift.
Input Stage and Input Voltage Range
The input terminals (IN+ and IN-) of the in-amps are a single
differential pair of bipolar PNP devices aided by an Input Range
Enhancement Circuit (IREC), to increase the headroom of
operation of the common-mode input voltage. The feedback
terminals (FB+ and FB-) also have a similar topology. As a
result, the input common-mode voltage range is rail-to-rail
regardless of the feedback terminal settings and regardless of
the gain settings. They are able to handle input voltages that
are at or slightly beyond the supply and close to ground making
these in-amps well suited for single 5V down to 2.4V supply
systems. There is no need to bias the common-mode input to
achieve symmetrical input voltage. It is recommended,
however, that the common-mode input be biased at least 10mV
above the negative supply rail to achieve top performance. See
“Input Bias Cancellation/Compensation” on page 11.
11
The IREC enables rail-to-rail input amplification without the
problems usually associated with the dual differential stage
topology. The IREC ensures that there are no drastic
changes in offset voltage over the entire range of the input.
See Input Offset Voltage vs Common-Mode Input Voltage in
performance charts. IREC also cures the abrupt change and
even reverse polarity of the input bias current over the whole
range of input.
Input Bias Cancellation/Compensation
All three parts have an Input Bias Cancellation/Compensation
Circuit for both the input and feedback terminals (IN+, IN-, FB+
and FB-), achieving a low input bias current throughout the
input common-mode range and the operating temperature
range. While the PNP bipolar input stages are biased with an
adequate amount of biasing current for speed and increased
noise performance, the Input Bias Cancellation/Compensation
Circuit sinks most of the base current of the input transistors
leaving a small portion as input bias current, typically 500pA. In
addition, the Input Bias Cancellation/Compensation Circuit
maintains a smooth and flat behavior of input bias current over
the common mode range and over the operating temperature
range. The Input Bias Cancellation/Compensation Circuit
operates from input voltages of 10mV above the negative
supply to input voltages slightly above the positive supply.
Output Stage and Output Voltage Range
A Class AB common-source output stage drives the output.
The pair of complementary MOSFET devices drive the
output VOUT to within a few millivolts of the supply rails. At a
100kΩ load, the PMOS sources current and pulls the output
up to 4mV below the positive supply. The NMOS sinks
current and pulls the output down to 4mV above the negative
supply, or ground in the case of a single supply operation.
The current sinking and sourcing capability are internally
limited to 29mA. When disabled, the outputs are in a high
impedance state.
Gain Setting
VIN (the potential difference across IN+ and IN-), is
replicated (less the input offset voltage) across FB+ and FB-.
The function of the in-amp is to maintain the differential
voltage across FB- and FB+ equal to IN+ and IN-; (FB- FB+) = (IN+ - IN-). Consequently, the transfer function can
be derived. The in-amp gain is set by two external resistors,
the feedback resistor RF, and the gain resistor RG.
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
2.4V TO 5V
IN+
IN+
IN-
IN-
V+
+
EN
EN
-
FB+
FB-
VCM
ISL28270
VOUT
+
-
RG
V-
an economical resistor divider can be used to set the voltage
at the REF terminal without degrading or affecting the CMRR
performance. Any voltage applied to the REF terminal will
shift VOUT by VREF times the closed loop gain, which is set
by resistors RF and RG. See Figure 29.
The FB+ pin can also be connected to the other end of
resistor, RG. See Figure 30. Keeping the basic concept that
the in-amp maintains constant differential voltage across the
input terminals and feedback terminals (FB- - FB+) =
(IN+ - IN-), the transfer function of Figure 30 can be derived.
RF
2.4V TO 5V
IN+
IN+
FIGURE 28. GAIN IS SET BY TWO EXTERNAL RESISTORS,
RF AND RG
ININ-
FB+
V IN = IN+ – IN-
FBVCM
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ V IN
R
⎝
G⎠
(EQ. 1)
In Figure 28, the FB+ pin and one end of resistor RG are
connected to GND. With this configuration, the gain equation
(Equation 1) is only true for a positive swing in VIN; negative
input swings will be ignored because the output will be at
ground.
Unlike a three op-amp in-amp realization, a finite series
resistance seen at the REF terminal does not degrade the
high CMRR performance, eliminating the need for an
additional external buffer amplifier. Figure 29 uses the FB+
pin to provide a high impedance REF terminal.
2.4V to 5V
IN+
IN+
INFB+
FB-
2.9V to 5V
VCM
V+
+
ISL28270
EN
EN
VOUT
+
-
V-
R1
REF
R2
EN
ISL28270
VOUT
+
-
V-
RS
VREF
RG
RF
FIGURE 30. REFERENCE CONNECTION WITH AN
AVAILABLE VREF
V IN = IN+ – IN-
Reference Connection
IN-
V+
+
EN
RG
RF
FIGURE 29. GAIN SETTING AND REFERENCE CONNECTION
RS + RF
V OUT = 1 + ---------------------- + V REF
RG
(EQ. 3)
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ ( V IN ) + ( V REF )
R
⎝
G⎠
(EQ. 4)
A finite resistance RS in series with the VREF source, adds
an output offset of VIN*(RS/RG). As the series resistance RS
approaches zero, Equation 3 is simplified to Equation 4 for
Figure 30. VOUT is simply shifted by an amount VREF.
External Resistor Mismatches
Because of the independent pair of feedback terminals
provided by the in-amps, the CMRR is not degraded by any
resistor mismatches. Hence, unlike a three op-amp and
especially a two op-amp in-amp realization, the ISL28270,
ISL28273 and ISL28470 reduce the cost of external
components by allowing the use of 1% or more tolerance
resistors without sacrificing CMRR performance. The CMRR
will be typically 110dB regardless of the tolerance of the
resistors used. Instead, a resistor mismatch results in a
higher deviation from the theoretical gain - gain Error.
.
Gain Error and Accuracy
V IN = IN+ – INRF ⎞
RF ⎞
⎛
⎛
V OUT = ⎜ 1 + --------⎟ ( V IN ) + ⎜ 1 + --------⎟ ( V REF )
R
R
⎝
⎝
G⎠
G⎠
(EQ. 2)
The FB+ pin is used as a REF terminal to center or to adjust
the output. Because the FB+ pin is a high impedance input,
12
The gain error indicated in the “Electrical Specifications”
Table on page 3 is the inherent gain error alone. The gain
error specification listed does not include the gain error
contributed by the resistors. There is an additional gain error
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
due to the tolerance of the resistors used. The resulting
non-ideal transfer function effectively becomes Equation 5:
pulled above 2V, and will power up when the EN bar is pulled
below 0.8V.
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ × [ 1 ± ( E RG + E RF + E G ) ] × V IN
R
⎝
G⎠
Unused Channels
(EQ. 5)
Where:
ERG = Tolerance of RG
ERF = Tolerance of RF
EG
= Gain Error of the ISL28270
The term [1 - (ERG +ERF +EG)] is the deviation from the
theoretical gain. Thus, (ERG +ERF +EG) is the total gain
error. For example, if 1% resistors are used, the total gain
error would be as follows in Equation 6:
TotalGainError = ± ( E RG + E RF + E G ( typical ) )
The ISL28270, ISL28273 and ISL28470 are Dual-channel
and Quad-channel op-amps. If the application only requires
one channel when using the ISL28270, ISL28273 or less
than 4-channels when using the ISL28470, the user must
configure the unused channel(s) to prevent them from
oscillating. The unused channel(s) will oscillate if the input
and output pins are floating. This will result in higher than
expected supply currents and possible noise injection into
the channel being used. The proper way to prevent this
oscillation is to short the output to the negative input and
ground the positive input (as shown in Figure 31).
(EQ. 6)
TotalGainError = ± ( 0.01 + 0.01 + 0.005 ) = ± 2.5%
IN+
Disable/Power-Down
1/2 ISL28270, ISL28273
1/4 ISL28470
+
IN-
The ISL28270, ISL28273 and ISL28470 have an
enable/disable pin for each channel. They can be powered
down to reduce the supply current to typically 4µA when all
channels are off. When disabled, the corresponding output is
in a high impedance state. The active low EN pin has an
internal pull down and hence can be left floating and the
in-amp enabled by default. When the EN is connected to an
external logic, the in-amp will shutdown when the EN pin is
FB+
FB-
RG
+
-
RF
FIGURE 31. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
13
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
INDEX
AREA
H
0.25(0.010) M
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
E
1
2
INCHES
GAUGE
PLANE
-B-
SYMBOL
3
L
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
α
e
B
0.17(0.007) M
A2
A1
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.386
0.394
9.81
10.00
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
α
28
0°
28
8°
0°
7
8°
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
14
FN6260.2
April 13, 2007
ISL28270, ISL28273, ISL28470
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
FN6260.2
April 13, 2007