Clock Generator for Cavium Processors ICS8430S07I DATA SHEET General Description Features The ICS8430S07I is a PLL-based clock generator specifically designed for Cavium Networks SoC HiPerClockS™ processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN3005/CN3010/CN3020 processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the ICS8430S07I supports telecommunication, networking, and storage requirements. • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock references for GbE PHY • Selectable external crystal or differential (single-ended) input source • Crystal oscillator interface designed for 25MHz, parallel resonant crystal • Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.78ps (typical), QD output • Output supply: LVPECL – 3.3V Core LVCMOS – Core/Output 3.3V/3.3V 3.3V/2.5V • • -40°C to 85°C ambient operating temperature ICS Applications Networking, control and storage equipment, including routers, switches, application-aware gateways, triple-play gateways, WLAN and 3G/4G access and aggregation devices, storage arrays, storage networking equipment, servers, and intelligent NICs Available in lead-free (RoHS 6) package 802.11 a/b/g/n wireless for home data and multi-media distribution QoS for high quality Voice, Video, and Data Service Next-generation PON, VDSL2, and Cable Networks VDDO_D QD GND Consumer Space Media Server VDDO_REF Pin Assignment QREF2 Audio/Video Storage and Distribution QREF1 High-performance NAS QREF0 • • • • • • Systems using CN30XX MIPS64 Broadband Processors VDDO_REF • • 32 31 30 29 28 27 26 25 ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 nXTAL_SEL 5 CLK 6 nCLK 7 GND 8 1 9 10 11 12 13 14 15 16 24 VDDO_C 23 QC 22 CORE_SEL 21 GND 20 GND 19 MR/ nOE_ REF 18 QB 17 VDDO_B VDDA 4 VDD XTAL_ OUT 32- Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View QA 3 nQA XTAL_IN ICS8430S07I DDR_SEL0 2 DDR_SEL1 nPLL_SEL PCI_SEL0 1 PCI_SEL1 VDD ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Block Diagram nPLL_SEL PD nXTAL_SEL PD 00 = 133.333MHz 01 = 100.000MHz 10 = 83.333MHz 11 = 125.000MHz DDR533, DDR400, or QA DDR667 Reference nQA Clock (LVPECL) 0 = 50.000MHz 1 = 33.333MHz QB Processor Core Clock (LVCMOS) 00 = 133.333MHz 01 = 100.000MHz 10 = 66.667MHz 11 = 33.333MHz QC PCI or PCI-X Clock (LVCMOS) 125MHz GbE CLK QD Gigabit Ethernet MAC Clock (LVCMOS) XTAL_IN 25MHz XTAL_OUT OSC 0 1 PLL 0 1 CLK PD 25MHz nCLK PU/PD DDR_SEL1:0 PD CORE_SEL PD QREF0 Clock Output Control Logic 25MHz GbE CLK PCI_SEL1:0 PD \ \ Gigabit Ethernet QREF1 / PHY Clocks / (LVCMOS) QREF2 MR/nOE_REF PD ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 2 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 1. Pin Descriptions Number Name 1, 15 VDD Type Description Power Core supply pins. PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, bypasses the PLL. LVCMOS/LVTTL interface levels. 2 nPLL_SEL Input Pulldown 3, 4 XTAL_IN, XTAL_OUT Input 5 nXTAL_SEL Input Pulldown Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when HIGH. LVCMOS/LVTTL interface levels. 6 CLK Input Pulldown Non-inverting differential clock input. 7 nCLK Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 8, 20, 21, 27 GND Power 9, 10 PCI_SEL1, PCI_SEL0 Input Pulldown Selects the PCI/PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. 11, 12 DDR_SEL1, DDR_SEL0 Input Pulldown Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 13, 14 nQA, QA Output Differential output pair. LVPECL interface levels. 16 VDDA Power Analog supply pin. 17 VDDO_B Power Bank B output supply pin. 3.3 V or 2.5V supply. 18, 23, 26, 29, 30, 31 QB, QC, QD, QREF2, QREF1, QREF0 Output Single-ended outputs. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Power supply ground. 19 MR/nOE_REF Input Pulldown Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the QREF[2:0] outputs are in high impedance (HI-Z). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/ LVTTL interface levels. 22 CORE_SEL Input Pulldown Selects the processor core clock output frequency. The output frequency is 50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. 24 VDDO_C Power 25 VDDO_D Power Bank D output supply pin. 3.3 V or 2.5V supply. 28, 32 VDDO_REF Power REF bank output supply pins. 3.3 V or 2.5V supply. Bank C output supply pin. 3.3 V or 2.5V supply. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor Output Impedance Typical Maximum Units 2 pF VDD, VDDO_X = 3.465V 4 pF VDD = 3.465V, VDDO_X = 2.625V 4 pF 51 kΩ 51 kΩ RPULLDOWN Input Pulldown Resistor ROUT Minimum QB, QC, QD, QREF[0:2] VDDO_X = 3.465V 15 Ω QB, QC, QD, QREF[0:2] VDDO_X = 2.625V 20 Ω NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF. Function Tables Table 3A. QB Output Control Input Function Table Input Output Frequency CORE_SEL QB 0 (default) 50MHz 1 33.333MHz Table 3B. QA Output Control Input Function Table Inputs Output Frequency DDR_SEL1 DDR_SEL0 QA, nQA 0 (default) 0 (default) 133.333MHz 0 1 100.000MHz 1 0 83.333MHz 1 1 125.000MHz Table 3C. QC Output Control Input Function Table Inputs Output Frequency PCI_SEL1 PCI_SEL0 QC 0 (default) 0 (default) 133.333MHz 0 1 100.000MHz 1 0 66.6667MHz 1 1 33.333MHz ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 4 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to VDD + 0.5V Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 39.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.20 3.3 VDD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 170 mA IDDA Analog Supply Current 20 mA IDDO_X Output Supply Current 25 mA NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF. NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF. Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.20 3.3 VDD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 160 mA IDDA Analog Supply Current 20 mA IDDO_X Output Supply Current 20 mA NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF. NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 150 µA Input High Current nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF VDD = VIN = 3.465V IIL Input Low Current nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF VDD = 3.465V, VIN = 0V -10 µA V Output High Voltage; NOTE 1 VDDO_X = 3.465V 2.6 VOH VDDO_X = 2.625V 1.8 V VOL Output Low Voltage: NOTE 1 IIH VDDO_X = 3.465V or 2.625V 0.6 V NOTE 1: Outputs terminated with 50Ω to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram. Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD – 0.85 V CLK/nCLK Minimum Typical VDD = VIN = 3.465V Maximum Units 150 µA CLK VDD = 3.465V, VIN = 0V -10 µA nCLK VDD = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VDD – 1.4 VDD – 0.8 V VDD – 2.0 VDD – 1.7 V 0.55 1.0 V NOTE 1: Outputs terminated with 50Ω to VDD – 2V. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 6 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF 300 µW Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 7 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions QA/nQA Output Frequency DDR_SEL[1:0] = 00 Typical Maximum Units 133.333 MHz QA/nQA DDR_SEL[1:0] = 01 100 MHz QA/nQA DDR_SEL[1:0] = 10 83.333 MHz QA/nQA DDR_SEL[1:0] = 11 125 MHz CORE_SEL = 0 50 MHz QB fMAX Minimum QB CORE_SEL = 1 33.333 MHz QC PCI_SEL[1:0] = 00 133.333 MHz QC PCI_SEL[1:0] = 01 100 MHz QC PCI_SEL[1:0] = 10 66.667 MHz QC PCI_SEL[1:0] = 11 33.333 MHz QD 125 MHz QREF[0:2] 25 MHz tsk(b) Bank Skew; NOTE 2, 4 QREF[0:2] 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 QREF[0:2] 400 ps QB, QC, 270 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4, 5 QA/nQA measured at crosspoint QD 95 ps 200 ps tjit(per) Period Jitter (pk-pk); NOTE 4 QA/nQA measured at crosspoint -90 90 ps tjit(hper) Half-period Jitter (pk-pk) QA/nQA measured at crosspoint -90 90 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 QREF[0:2] 25MHz (10kHz to 5MHz) QD 125MHz (1.875MHz to 20MHz) QB tR / tF odc Output Rise/Fall Time Output Duty Cycle 0.73 ps 0.78 ps 100 450 ps 100 300 ps 100 450 ps QD 100 450 ps QA/nQA 49 51 % QB, QC, QD, QREF[0:2] 45 55 % QA/nQA QC, QREF[0:2] 20% to 80% NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: All outputs running at corresponding fMAX. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 8 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS ➝ Typical Phase Noise at 125MHz (QD output @ 3.3V) GbE Filter ➝ Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.78ps (typical) ➝ Raw Phase Noise Data Phase Noise Result by adding a GbE filter to raw data Offset Frequency (Hz) ➝ Typical Phase Noise at 25MHz (QREF output @ 3.3V) GbE Filter ➝ Raw Phase Noise Data ➝ Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.73ps (typical) Phase Noise Result by adding a GbE filter to raw data Offset Frequency (Hz) ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information 2V 1.65V±5% 2V 1.65V±5% VDD Qx SCOPE VDD, SCOPE VDDO_X VDDA VDDA Qx LVCMOS LVPECL GND nQx VEE -1.65V±5% -1.3V±0.165V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.05V±5% 1.25V±5% VDD 2.05V±5% SCOPE VDD nCLK VDDO_X V PP Qx LVCMOS VDDA V Cross Points CMR CLK GND GND - -1.25V±5% 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Differential Input Level VOH nQA QA ➤ ➤ t half period n t half period 1 fo n+1 VREF ➤ ➤ VOL ➤ ➤ t jit(hper) = t half period n — 1 t jit (pk-pk) 2*fo Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) 10,000 cycles Half Period Jitter ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 Period Jitter 10 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information, continued VDDO_REF 2 QREF[0:2] Par t 1 V DDO_REF Q_REFx VDDO_REF 2 QREF[0:2] 2 Par t 2 V DDO_REF Q_REFy 2 tsk(pp) tsk(b) LVCMOS Bank Skew LVCMOS Part-to-Part Skew nQA V tcycle n+1 ➤ ➤ ➤ ➤ DDOX 2 DDOX 2 ➤ ➤ tcycle n V V DDOX QB:QD, QREF[0:2] QA ➤ tcycle n 2 tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles LVPECL Cycle-to-Cycle Jitter LVCMOS Cycle-to-Cycle Jitter Noise Power Phase Noise Plot nQA 80% 80% VSW I N G Phase Noise Mask QA:QD, QREF[0:2] 20% 20% tR f1 Offset Frequency tF f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 Output Rise/Fall Time 11 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information, continued nQA V DDOX QB:QD, QREF[0:2] 2 QA t PW t PW t odc = t PERIOD t PW PERIOD t PW odc = x 100% x 100% t PERIOD t PERIOD LVCMOS Output Duty Cycle/Pulse Width/Period LVPECL Output Duty Cycle/Pulse Width/Period Application Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 12 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform ance, power supply isolation is required. The ICS8430S07I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. The unused LVPECL output can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal Inputs LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 13 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50Ω Receiver LVDS Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 14 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Crystal Input Interface The ICS8430S07I has been characterized with 18pF parallel resonant crystals. The capacitors C1 and C2 are not required, but can be populated for optimal ppm accuracy. The C1 and C2 values can be slightly adjusted to minimize ppm error for different board layouts. XTAL_IN C1 Spare X1 18pF Parallel Crystal XTAL_OUT C2 Spare Figure 4. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 5. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VDD the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 15 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential output pair is low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω + + _ LVPECL Input Zo = 50Ω _ LVPECL R1 50Ω R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 Input Zo = 50Ω R2 84Ω RTT Figure 6A. 3.3V LVPECL Output Termination ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 Figure 6B. 3.3V LVPECL Output Termination 16 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 7. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 17 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Application Schematic Figure 8 shows a schematic example of using an ICS8430S07I. The crystal inputs are parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are optional. The tuning capacitor value can be slightly adjusted to optimize the frequency accuracy. This schematic example shows hardwired logic control input handling. The logic inputs can also be driven by 3.3V LVCMOS drivers. It is recommended to have one bypass capacitor per power pin. In general, the bypass capacitor values are ranged from 0.01uF to 0.1uF. Each bypass capacitor should be located as close as possible to the power pin. The low pass filter R6, C3 and C4 for clean analog supply should also be located as close to the VDDA pin as possible. Only two examples of LVPECL termination and one example of LVCMOS termination are shown in this schematic. Additional examples of LVPECL terminations and LVCMOS terminations can be found in the LVPECL Termination and LVCMOS Termination Application Notes. Figure 8. ICS8430S07I Schematic Example ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 18 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Power Considerations This section provides information on power dissipation and junction temperature for the ICS8430S07I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430S07I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation • Power (core)_MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (170mA + 20mA + 25mA) = 744.98mW • Power (output)_MAX = 30mW/Loaded Output Pair LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.7mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.7mA)2 = 10.7mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 10.7mW * 6 = 64.2mW • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.5mW per output Total Power (25MHz) = 1.5mW * 3 = 4.5mW • Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 4pF * 133MHz * (3.465V)2 = 8mW per output Total Power (133MHz) = 8mW * 3 = 24mW Total Power Dissipation • Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (25MHz) + Total Power (125MHz) = 745mW + 30mW + 64.2mW + 4.5mW + 24mW = 867.7mW ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 19 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.868W * 39.5°C/W = 119.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 0 1 2.5 39.5°C/W 34.5°C/W 31.0°C/W 20 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 9. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 9. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VDD – 2V. • For logic high, VOUT = VOH_MAX = VDD_MAX – 0.9V (VDD_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VDD_MAX – 1.7V (VDD_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 21 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Reliability Information Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 39.5°C/W 34.5°C/W 31.0°C/W Transistor Count The transistor count for ICS8430S07I is: 10,871 ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 22 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 Th er mal Ba se D2 2 C D2 C Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID BB 4 CHAMFER 4 N N-1 There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) 2 1 2 1 CC 2 1 4 N N-1 DD 4 RADIUS 4 N N-1 AA 4 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. Table 9. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 23 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Ordering Information Table 10. Ordering Information Part/Order Number 8430S07AKILF 8430S07AKILFT Marking ICS30S07AIL ICS30S07AIL Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 24 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Revision History Sheet Rev A Table Page 23 Description of Change Date Package Outline & Dimensions - added pin 1 indicator in package drawing. ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 25 9/3/09 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 CLOCK GENERATOR FOR CAVIUM PROCESSORS Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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