FemtoClock™ SAS/SATA Clock Generator ICS843442I DATA SHEET General Description Features The ICS843442I is a low jitter, high performance clock generator and a member of the FemtoClock™family of HiPerClockS™ silicon timing products. The ICS843442I is designed for use in applications using the SAS and SATA interconnect. The ICS843442I uses an external, 25MHz, parallel resonant crystal to generate two selectable output frequencies: 75MHz and 150MHz. This silicon based approach provides excellent frequency stability and reliability. The ICS843442I features down and center spread spectrum (SSC) clocking techniques. • • • • • Designed for use in SAS, SAS-2, and SATA systems • External fundamental crystal frequency ensures high reliability and low aging • • • Selectable output frequencies: 75MHz, 150MHz • • • 3.3V operating supply ICS Applications • • • • • • • SAS/SATA Host Bus Adapters SATA Port Multipliers SAS I/O Controllers TapeDrive and HDD Array Controllers SAS Edge and Fanout Expanders Center (±0.25%) Spread Spectrum Clocking (SSC) Down (-0.23% or -0.5%) SSC Two differential 3.3V LVPECL output pairs Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency Output frequency is tunable with external capacitors RMS phase jitter at 150MHz (integrated from 12kHz to 20MHz): 1.07ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package HDDs and TapeDrives Disk Storage Enterprise Pin Assignment Block Diagram nPLL_SEL Pulldown XTAL_IN 25MHz OSC XTAL_OUT FemtoClock™ PLL 0 1 F_SEL Pullup SSC_SEL[1:0] Pulldown 2 Q0 nQ0 0 = 75MHz 1 = 150MHz Q1 nQ1 (default) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL VEE nPLL_SEL nQ0 Q0 nQ1 Q1 VCC ICS843442I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View Clock Output Control Logic ICS843442AGI REVISION A JUNE 24, 2009 VEE XTAL_OUT XTAL_IN SSC_SEL0 nc nc nc SSC_SEL1 1 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Table 1. Pin Descriptions Number Name 1, 15 VEE Power Type Negative supply pins. Description 2, 3 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4, 8 SSC_SEL0, SSC_SEL1 Input 5, 6, 7 nc Unused 9 VCC Power Power supply pin. 10, 11 Q1, nQ1 Output Differential clock outputs. LVPECL interface levels. 12, 13 Q0, nQ0 Output Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. No connect. Differential clock outputs. LVPECL interface levels. 14 nPLL_SEL Input Pulldown 16 F_SEL Input Pullup PLL Bypass pin. When LOW, selects PLL. When HIGH, bypasses PLL. LVCMOS/LVTTL interface levels. Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ Function Tables Table 3A. SSC_SEL[1:0] Function Table Table 3B. F_SEL Function Table Inputs Input SSC_SEL1 SSC_SEL0 Mode F_SEL Output Frequency (MHz) 0 (default) 0 (default) SSC Off 0 75 0 1 0.5% Down-spread 1 (default) 150 1 0 0.23% Down-spread 1 1 0.5% Center-spread ICS843442AGI REVISION A JUNE 24, 2009 2 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 92.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 80 mA Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V F_SEL VCC = VIN = 3.465V 5 µA nPLL_SEL, SSC_SEL[0:1] VCC = VIN = 3.465V 150 µA F_SEL VCC = 3.465V, VIN = 0V -150 µA nPLL_SEL, SSC_SEL[0:1] VCC = 3.465V, VIN = 0V -5 µA Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 V VCC – 2.0 VCC – 1.7 V 0.6 0.9 V NOTE 1: Output termination with 50Ω to VCC – 2V. ICS843442AGI REVISION A JUNE 24, 2009 3 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units F_SEL = 0 75 MHz F_SEL = 1 150 MHz 75MHz, Integration Range: 12kHz – 20MHz 1.10896 ps 150MHz, Integration Range: 12kHz – 20MHz 1.07375 ps 20% to 80% 325 650 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: See phase noise plot section. ICS843442AGI REVISION A JUNE 24, 2009 4 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Noise Power dBc Hz Typical Phase Noise at 75MHz Offset Frequency (Hz) Noise Power dBc Hz Typical Phase Noise at 150MHz Offset Frequency (Hz) ICS843442AGI REVISION A JUNE 24, 2009 5 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Parameter Measurement Information 2V VCC Qx Noise Power Phase Noise Plot SCOPE Phase Noise Mask LVPECL nQx f1 VEE Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.3V± 0.165V 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter nQ[0:1] nQ[0:1] 80% 80% Q[0:1] VSW I N G Q[0:1] t PW 20% 20% tR t PERIOD tF odc = t PW x 100% t PERIOD Output Rise/Fall Time ICS843442AGI REVISION A JUNE 24, 2009 Output Duty Cycle/Pulse Width/Period 6 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Application Information Crystal Input Interface The ICS843442I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 1. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VCC the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface ICS843442AGI REVISION A JUNE 24, 2009 7 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω Zo = 50Ω + + _ LVPECL Input Zo = 50Ω _ LVPECL R1 50Ω R2 50Ω R1 84Ω VCC - 2V 1 RTT = * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 3A. 3.3V LVPECL Output Termination ICS843442AGI REVISION A JUNE 24, 2009 Input Zo = 50Ω Figure 3B. 3.3V LVPECL Output Termination 8 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Power Considerations This section provides information on power dissipation and junction temperature for the ICS843442I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843442I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 277.2mW + 60mW = 337.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.337W * 92.4°C/W = 116.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS843442AGI REVISION A JUNE 24, 2009 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W 9 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS843442AGI REVISION A JUNE 24, 2009 10 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Reliability Information Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W Transistor Count The transistor count for ICS843442I is: 3037 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 8. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS843442AGI REVISION A JUNE 24, 2009 11 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SATA Clock Generator Ordering Information Table 9. Ordering Information Part/Order Number 843442AGILF 843442AGILFT Marking 43442AIL 43442AIL Package 16 Lead TSSOP 16 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843442AGI REVISION A JUNE 24, 2009 12 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCK™ SAS/SATA Clock Generator Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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