1:2 Differential-to-LVPECL Buffer/Divider ICS8S89874I DATA SHEET General Description Features The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/ Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider, which allows the device to be used as either a 1:2 fanout buffer or frequency divider. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. • • Two LVPECL/ECL output pairs • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML • • • • • • • • Output frequency: 2GHz (maximum) Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8, ÷16 Output skew: 15ps (maximum) Part-to-part skew: 250ps (maximum) Additive phase jitter, RMS: 0.20ps (typical) LVPECL supply voltage range: 2.375V to 3.63V ECL supply voltage range: -3.63V to -2.375V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package 2 11 VT Q1 3 00 01 10 11 50Ω VT 50Ω nIN 10 VREF_AC nQ1 4 Q1 ÷2 ÷4 ÷8 ÷16 nQ1 S2 nQ0 6 7 8 VCC 9 nIN 5 0 nRESET Q0 1 IN VCC 16 15 14 13 12 IN nQ0 Enable FF Enable MUX ICS8S89874I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View S0 Pullup S1 Pullup Q0 1 nc nRESET Pullup VEE S0 S2 Pullup S1 Pin Assignment Block Diagram Decoder VREF_AC ICS8S89874BKI REVISION A OCTOBER 22, 2010 1 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Table 1. Pin Descriptions Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL/ECL interface levels. Description 3, 4 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels. 5, 15, 16 S2, S1, S0 Input 6 nc Unused 7, 14 Vcc Power 8 nRESET Input Pullup Select pins. LVCMOS/LVTTL interface levels. No connect. Positive supply pins. Pullup When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold is VCC/2. Includes a 37kΩ pullup resistor. LVTTL/LVCMOS interface levels. Inverting differential LVPECL clock input. RT = 50Ω termination to VT. 9 nIN Input 10 VREF_AC Output 11 VT Input Termination input. 12 IN Input Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT. 13 VEE Power Negative supply pin. Reference voltage for AC-coupled applications. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLUP Input Pullup Resistor ICS8S89874BKI REVISION A OCTOBER 22, 2010 Test Conditions Minimum Typical 37 2 Maximum Units kΩ ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Function Tables Table 3A. Control Input Function Table Inputs Outputs nRESET Selected Source Q0, Q1 nQ0, nQ1 0 IN/nIN Disabled; LOW Disabled; HIGH 1 IN/nIN Enabled Enabled VCC/2 nRESET tRR IN nIN VIN VIN Swing tPD nQx VOUT Swing Qx Figure 1. nRESET Timing Diagram Table 3B. Truth Table Inputs nRESET S2 S1 S0 Outputs 1 0 X X Reference Clock ÷1 (pass through) 1 1 0 0 Reference Clock ÷2 1 1 0 1 Reference Clock ÷4 1 1 1 0 Reference Clock ÷8 1 1 1 1 Reference Clock ÷16 0 1 X X Q = LOW, nQ = HIGH; Clock Disabled 0 0 X X Q = LOW, nQ = HIGH; Clock Disabled ICS8S89874BKI REVISION A OCTOBER 22, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC -0.5V to + 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA VREF_AC Input Sink/Source, IREF_AC ±2mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA, (Junction-to-Ambient) 74.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.63 V 45 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.63V or 2.625V IIL Input Low Current VCC = 3.63V or 2.625V, VIN = 0V ICS8S89874BKI REVISION A OCTOBER 22, 2010 Test Conditions Minimum 4 Maximum Units 2.2 VCC + 0.3 V 0 0.8 V 10 µA -150 Typical µA ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Table 4C. Differential DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter RIN Differential Input Resistance VIH Test Conditions Minimum Typical Maximum Units (IN, nIN) 40 50 60 Ω Input High Voltage (IN, nIN) 1.2 VCC V VIL Input Low Voltage (IN, nIN) 0 VIH – 0.15 V VIN Input Voltage Swing 0.15 1.2 V VDIFF_IN Differential Input Voltage Swing 0.3 IIN Input Current; NOTE 1 VREF_AC Bias Voltage V (IN, nIN) VCC – 1.45 VCC – 1.37 35 mA VCC – 1.32 V NOTE 1: Guaranteed by design. Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VOUT VDIFF_OUT Test Conditions Minimum Typical Maximum Units VCC – 1.175 VCC – 0.82 V VCC – 2.0 VCC – 1.575 V Output Voltage Swing 0.6 1.0 V Differential Output Voltage Swing 1.2 2.0 V NOTE: Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. ICS8S89874BKI REVISION A OCTOBER 22, 2010 5 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency fIN Input Frequency tPD Propagation Delay; (Differential); NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; NOTE 3, 4 tjit Buffer Additive Jitter; RMS; refer to Additive Phase Jitter Section; NOTE 5 tRR Reset Recovery time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units Output Swing ≥ 450mV 2 GHz ÷2, ÷4, ÷8, ÷16 2.5 GHz Input Swing: <400mV 460 640 840 ps Input Swing: ≥ 400mV 430 615 810 ps 15 ps 250 ps 155.52MHz, Integration Range: 12kHz – 20MHz 0.20 ps 600 20% to 80% 70 ps 250 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters characterized at ≤ 1GHz, 800mV input signal, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Pass through, ÷1 mode. ICS8S89874BKI REVISION A OCTOBER 22, 2010 6 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.20ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS8S89874BKI REVISION A OCTOBER 22, 2010 The source generator IFR2042 and Agilent 8133 were the external input to drive the input clock, IN, nIN. 7 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Parameter Measurement Information 2V VCC VCC Qx SCOPE nIN V Cross Points IN V IH IN LVPECL nQx V VEE IL VEE -0.375V to -1.63V Output Load AC Test Circuit Differential Input Level nQx Par t 1 nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nIN VDIFF_IN VIN IN nQ0, nQ1 Q0, Q1 Differential Voltage Swing = 2 x Single-ended VIN tPD Single-ended & Differential Input Voltage Swing Propagation Delay nQ0, nQ1 80% 80% VSW I N G 20% 20% Q0, Q1 tR tF Output Rise/Fall Time ICS8S89874BKI REVISION A OCTOBER 22, 2010 8 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Applications Information 3.3V Differential Input with Built-In 50Ω Termination Interface the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. Both signals must meet the VIN and VIH input requirements. Figures 2A to 2D show interface examples for the IN/nIN input with built-in 50Ω terminations driven by 3.3V 3.3V 3.3V 3.3V Zo = 50Ω Zo = 50Ω IN IN VT Zo = 50Ω VT Zo = 50Ω nIN nIN Receiver LVDS Receiver LVPECL With With R1 50Ω Built-In Built-In 50Ω 50Ω Figure 2B. IN/nIN Input with Built-In 50Ω Driven by an LVPECL Driver Figure 2A. N/nIN Input with Built-In 50Ω Driven by an LVDS Driver 3.3V 3.3V 3.3V 3.3V Zo = 50Ω Zo = 50Ω IN IN Zo = 50Ω Zo = 50Ω VT nIN nIN Receiver CML – Open Collector VT CML – Built-in 50Ω Pull-up With Receiver With Built-In Built-In 50Ω 50Ω Figure 2D. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Built-In 50Ω Pullup Figure 2C. IN/nIN Input with Built-In 50Ω Driven by a CML Driver ICS8S89874BKI REVISION A OCTOBER 22, 2010 9 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER 2.5V LVPECL Input with Built-In 50Ω Termination Interface the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. Both signals must meet the VIN and VIH input requirements. Figures 3A to 3D show interface examples for the IN/nIN with built-in 50Ω termination input driven by 2.5V 2.5V 2.5V 3.3V or 2.5V Zo = 50Ω Zo = 50Ω IN IN VT Zo = 50Ω VT Zo = 50Ω nIN nIN Receiver LVDS Receiver LVPECL With With R1 18Ω Built-In Built-In 50Ω 50Ω Figure 3B. IN/nIN Input with Built-In 50Ω Driven by an LVPECL Driver Figure 3A. IN/nIN Input with Built-In 50Ω Driven by an LVDS Driver 2.5V 2.5V 2.5V Zo = 50Ω 2.5V Zo = 50Ω IN Zo = 50Ω IN VT Zo = 50Ω nIN nIN Receiver CML CML - Built-in 50Ω Pull-up With Receiver With Built-In Built-In 50Ω 50Ω Figure 3C. IN/nIN Input with Built-In 50Ω Driven by a CML Driver ICS8S89874BKI REVISION A OCTOBER 22, 2010 VT Figure 3D. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Built-In 50Ω Pullup 10 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins has internal pullups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω + + _ LVPECL Input Zo = 50Ω _ LVPECL R1 50Ω R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 4A. 3.3V LVPECL Output Termination ICS8S89874BKI REVISION A OCTOBER 22, 2010 Input Zo = 50Ω Figure 4B. 3.3V LVPECL Output Termination 11 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω 50Ω R3 250Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50Ω 2.5V LVPECL Driver R2 62.5Ω R2 50Ω R4 62.5Ω R3 18Ω Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω Figure 5C. 2.5V LVPECL Driver Termination Example ICS8S89874BKI REVISION A OCTOBER 22, 2010 12 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8S89874BKI REVISION A OCTOBER 22, 2010 13 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8S89874I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8S89874I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 45mA = 163.35mW • Power (outputs)MAX = 32.62mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 32.62mW = 65.24mW • Power Dissipation for internal termination RT Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80Ω = 18mW Total Power_MAX = (3.63V, with all outputs switching) = 163.35mW + 65.24mW + 18mW = 246.59mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.247W * 74.7°C/W = 103.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8S89874BKI REVISION A OCTOBER 22, 2010 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W 14 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.82V (VCC_MAX – VOH_MAX) = 0.82V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.58V (VCC_MAX – VOL_MAX) = 1.58V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.82V)/50Ω] * 0.82V = 19.35mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCO_MAX – VOL_MAX) = [(2V – 1.58V)/50Ω] * 1.58V = 13.27mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.62mW ICS8S89874BKI REVISION A OCTOBER 22, 2010 15 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Reliability Information Table 7. θJA vs. Air Flow Table for a 16 Lead VFQFN θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Transistor Count The transistor count for ICS8S89874I is: 489 Pin compatible with ICS889874 ICS8S89874BKI REVISION A OCTOBER 22, 2010 16 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN (Ref.) Seating Plane ND & NE Even (ND-1)x e (R ef.) A1 Index Area A3 N Top View L N e (Typ.) 2 If ND & NE 1 Anvil Singulation or Sawn Singulation are Even 2 E2 (NE -1)x e (Re f.) E2 2 b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e ND & NE Odd 0. 08 C D2 2 Thermal Base D2 C Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID BB 4 CHAMFER 4 N N-1 There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) 2 1 2 1 CC 2 1 4 N N-1 DD 4 RADIUS 4 N N-1 AA 4 Table 8. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8S89874BKI REVISION A OCTOBER 22, 2010 17 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Ordering Information Table 9. Ordering Information Part/Order Number 8S89874BKILF 8S89874BKILFT Marking 874B 874B Package “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8S89874BKI REVISION A OCTOBER 22, 2010 18 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.