ISL55110_11EVAL1Z, ISL55110_11EVAL2Z Evaluation Board User’s Manual ® Application Note February 13, 2007 AN1283.0 Before Getting Started SCOPE PROBE CONNECTIONS This document supplements the ISL55110, ISL55111 Specification FN6228. Evaluation board users should review that document to obtain information on the parts’ basic functionality and power requirements. A most important note is before powering up the board, review the Power Up Sequence in that specification. There are two DC sources utilized, so a user may inadvertently mis-apply the power sources causing damage to the part. DIF+ DIF- R1 50Ω GND R3 0Ω DIF+ DIFDRIVER OUT R5 0Ω OB - BNC C6 C8 NOT NOT POPULATED POPULATED TP-OB GND FIGURE 1. DUAL.1” SPACED PINS ARE PLACED ON THE EVALUATIONS BOARDS FOR LEADLESS ACTIVE PROBE CONNECTIONS BNC Connections Scope Probe Connections Another topic to cover before getting started is the evaluation board physical connections for waveform observations. On each schematic version you will see a component with pins designated as DIF+ and DIF-. This is not an active component but a dual pin header physically designed to accommodate leadless connection of active differential or FET Probes. This will minimize ground lead inductance and capacitive loading while making waveform observations. However, the user must also be mindful of max voltage limitations when using these types of probes. The ISL55110, ISL55111 drivers cover a large voltage range, so double check the probe’s specifications. Scope Probe Test Points (TP) are provisioned across all inputs, outputs and VDD/VH to ground. 1 DIF+ DIF- Take time to review the ISL55110, ISL55111 Data Sheet (FN6228) and become familiar with the part’s basic functions and power options. Note also that FN6228 supersedes this document with respect to updates and modifications. Always refer to that document if discrepancies occur. All ISL55110, ISL55111 QFN and TSSOP boards are designed essentially in the same fashion. This document provides the user with the information regarding the evaluation board design, circuitry layout and driver load options. DRIVER INPUT TP-IN_B IN_B - BNC This series of evaluation boards also provides BNC connections for Input and Output signals. A key point to remember is the ISL55110, ISL55111 Driver Outputs (OA/OB) operate with the VH voltage as a High and Ground as a Low. These connectors are laid out to accommodate SMD connectors as well as BNC’s. Also note that the Driver Inputs have 50Ω terminations that you may need to remove for your application. Power Down Feature All boards provide the same capability for testing the Power Down Feature. A SPDT- Center OFF switch is provided for manual testing of the feature. In one position the PD input is connected to VDD (Power Down Enabled). In the other position the PD Input is connected to Ground. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1283 S1 - POWER DOWN CONTROL SPDT - CENTER OFF VDD PD - BNC GND R7 10k Once static observations check out, you can then increase power current limits for VCC/VH and apply higher frequency inputs to the IN_A/IN_B pins. Layout Information GND VDD 1 2 3 4 OB GND VH OA VDD PD IN-B IN-A All evaluation boards have complete silk-screen information regarding Test points, Jumpers and Component placements. 8 7 6 5 Schematic Information ISL55110, ISL55111_TSSOP FIGURE 2. TSSOP AND QFN EVALUATION BOARDS HAVE THE SAME POWER DOWN CIRCUITRY Finally the center off position provides a means of connecting a repetitive signal source to the PD input. This is so that the user can observe Power Down Enable/Disable timing. An important note to remember when using the PD BNC: 1) Place the switch in Center-Off position. 2) The PD input is referenced to VDD and ground. S2 - POWER DOWN CONTROL SPDT - CENTER OFF VDD EN - BNC PD - BNC R7 GND 10k GND OB GND VH OA Driver Loads DRIVER OUT OB R5 0Ω R3 0Ω OB - BNC DIF+ C6 NOT POPULATED DIF- DRIVER OUT OA C8 NOT POPULATED GND GND R8 10k VDD /ENABLE PD IN-B 5 IN-A VDD 1 2 3 4 Included below are two schematics. ISL55110, ISL55111: TSSOP dual driver device and ISL55110, ISL55111 QFN dual driver. Both packages have the Power Down Control, while the QFN has both Power Down and Enable inputs. TP-OB S1- ENABLE CONTROL SPDT- CENTER OFF GND Schematics are drawn with physical location in mind. Any changes in electrical circuitry will be updated in this document as needed. R6 0Ω R4 0Ω OA - BNC DIF+ 12 11 10 9 C7 NOT POPULATED DIFTP-OA C9 NOT POPULATED GND FIGURE 4. CUSTOM LOAD COMPONENTS ISL55110, ISL55111_QFN FIGURE 3. QFN PACKAGES HAVE BOTH POWER DOWN AND OUTPUT ENABLE DIGITAL INPUTS Component locations C6 to C7 and R3 to R6 are surface mount locations provided so the user can experiment with various load configurations. Initial Power Up Please refer to the device specification for power up sequencing and current requirements. Also note that the frequency of operation of each driver will determine the current needed. There are graphs in the specification regarding current characteristics. When first powering up the device, set all power bus inputs to minimum current levels needed for quiescent operation. Check the device out statically with DC inputs on the IN_A/ IN_B pins and observe that the OA/OB outputs toggle when the Input pins rise above and below the logic thresholds. Please note that these inputs are intended for use by high speed logic. Avoid slow DC ramps. VDD current should be ~3.6mA and VH should be less then 100µAmps with no DC loads on the outputs. 2 AN1283.0 February 13, 2007 Application Note 1283 S1 - POWER DOWN CONTROL SPDT - CENTER OFF VDD PD - BNC GND R7 10k GND TP-IN_B IN_B - BNC DIF+ DIF- DIFVDD 1 2 3 4 GND IN_A - BNC TP-IN_A VDD PD IN-B IN-A OB GND VH OA 8 7 6 5 ISL55110, ISL55111_TSSOP C6 C8 NOT NOT POPULATED POPULATED TP-OB GND R4 R6 0Ω 0Ω GND DIF+ C7 NOT POPULATED DIF- DIF+ R2 50Ω OB - BNC OA - BNC C9 NOT POPULATED TP-OA GND DIFTP-VH TP_VDD DIF+ DIF+ DIF- DIF- VH GND VH - BANANA JACK R5 0Ω R3 0Ω DIF+ R1 50Ω GND C2 C1 +4.7µF 0.1µF VDD C4 C3 0.1µF 0.1µF C5 +4.7µF VDD - BANANA JACK GND - BANANA JACK GND FIGURE 5. TSSOP EVALUATION BOARD SCHEMATIC . FIGURE 6. TSSOP LAYOUT 3 AN1283.0 February 13, 2007 Application Note 1283 S2 - POWER DOWN CONTROL SPDT - CENTER OFF VDD PD - BNC EN - BNC GND R7 10k S1- ENABLE CONTROL SPDT- CENTER OFF TP-IN_B R1 50Ω DIF+ DIF- 1 2 3 4 . VDD /ENABLE PD IN-B DIF+ VH GND VH - BANANA JACK OB 12 GND GND 11 VH 10 VH OA 9 GND C1 C2 +4.7µF 0.1µF OB - BNC C8 C6 NOT NOT POPULATED POPULATED TP-OB GND R4 0Ω GND DIF+ R6 0Ω OA - BNC C7 C9 NOT NOT POPULATED POPULATED DIF- ISL55110, ISL55111_QFN DIF- R5 0Ω R3 0Ω DIF- 5 TP-IN_A R2 50Ω GND DIF+ VDD GND IN_A - BNC GND R8 10k GND IN-A IN_B - BNC TP-OA TP-VH TP_VDD DIF+ DIF+ DIF- DIF- GND VDD C3 C4 0.1µF 0.1µF C5 + 4.7µF VDD - BANANA JACK GND GND - BANANA JACK GND FIGURE 7. QFN EVALUATION BOARD SCHEMATIC FIGURE 8. QFN LAYOUT Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 4 AN1283.0 February 13, 2007