318A

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−143
CASE 318A−06
ISSUE U
DATE 07 SEP 2011
SCALE 4:1
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE.
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
e
D
A
GAUGE
PLANE
E
SEATING
PLANE
L
L2
DETAIL A
E1
b1
e1
B
3X
b
0.20
TOP VIEW
H
c
A
A1
c
0.10 C
C
SIDE VIEW
C A-B D
M
DETAIL A
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
0.80
1.12
0.01
0.15
0.30
0.51
0.76
0.94
0.08
0.20
2.80
3.05
2.10
2.64
1.20
1.40
1.92 BSC
0.20 BSC
0.35
0.70
0.25 BSC
DIM
A
A1
b
b1
c
D
E
E1
e
e1
L
L2
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT
1.92
XXX MG
G
1
4X
0.75
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
2.70
0.20
3X
0.96
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.54
DIMENSIONS: MILLIMETERS
STYLE 1:
PIN 1.
2.
3.
4.
COLLECTOR
EMITTER
EMITTER
BASE
STYLE 2:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE 1
GATE 2
STYLE 3:
PIN 1.
2.
3.
4.
GROUND
SOURCE
INPUT
OUTPUT
STYLE 4:
PIN 1.
2.
3.
4.
STYLE 7:
PIN 1.
2.
3.
4.
SOURCE
GATE
DRAIN
SOURCE
STYLE 8:
PIN 1.
2.
3.
4.
SOURCE
GATE
DRAIN
N/C
STYLE 9:
PIN 1.
2.
3.
4.
GND
IOUT
VCC
VREF
STYLE 10:
PIN 1. DRAIN
2. N/C
3. SOURCE
4. GATE
DOCUMENT NUMBER:
STATUS:
98ASB42227B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
OUTPUT
GROUND
GROUND
INPUT
SOT−143
http://onsemi.com
1
STYLE 5:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE 1
SOURCE
STYLE 6:
PIN 1.
2.
3.
4.
GND
RF IN
VREG
RF OUT
STYLE 11:
PIN 1. SOURCE
2. GATE 1
3. GATE 2
4. DRAIN
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98ASB42227B
PAGE 2 OF 2
ISSUE
U
REVISION
REDREW TO JEDEC STANDARDS. ADDED SOLDER FOOTPRINT. REQ. BY D.
TRUHITTE.
DATE
07 SEP 2011
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 06U
Case Outline Number:
318A