HA-5340 ® Data Sheet June 2003 700ns, Low Distortion, Precision Sample and Hold Amplifier The HA-5340 combines the advantages of two sample/ hold architectures to create a new generation of monolithic sample/hold. High amplitude, high frequency signals can be sampled with very low distortion being introduced. The combination of exceptionally fast acquisition time and specified/characterized hold mode distortion is an industry first. Additionally, the AC performance is only minimally affected by additional hold capacitance. To achieve this level of performance, the benefits of an integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates to a front-end stage that has high bandwidth due to charging only a small capacitive load and an output stage with constant pedestal error which can be nulled out using the offset adjust pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error and droop rate without sacrificing speed. Low distortion, fast acquisition, and low droop rate are the result, making the HA-5340 the obvious choice for high speed, high accuracy sampling systems. Ordering Information PART NUMBER TEMP. RANGE (oC) HA9P5340-5 0 to 75 PKG. DWG. # PACKAGE 16 Ld SOIC Features • Fast Acquisition Time (0.01%) . . . . . . . . . . . . . . . . . 700ns • Fast Hold Mode Settling Time (0.01%) . . . . . . . . . . 200ns • Low Distortion (Hold Mode) . . . . . . . . . . . . . . . . . . -72dBc (VIN = 200kHz, fS = 450kHz, 5VP-P) • Bandwidth Minimally Affected By External CH • Fully Differential Analog Inputs • Built-In 135pF Hold Capacitor Applications • High Bandwidth Precision Data Acquisition Systems • Inertial Navigation and Guidance Systems • Ultrasonics • SONAR • RADAR Pinout HA-5340 (SOIC) TOP VIEW -IN 1 16 S/H CONTROL +IN 2 15 SUPPLY GND OFFSET ADJ. 3 14 NC OFFSET ADJ. 4 13 NC NC 5 M16.3 V- 6 Functional Diagram CHOLD EXTERNAL (OPTIONAL) ADJUST OFFSET 3 12 4 FN2859.5 EXTERNAL 12 HOLD CAP. 11 NC SIG. GND 7 10 NC OUTPUT 8 9 V+ 8 CHOLD 120pF -IN +IN S/H CONTROL 1 CCOMP 15pF 2 8 OUT 16 9 V+ 6 V- 15 7 SUPPLY SIGNAL GND GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HA-5340 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -6V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Resistance (Typical, Note 2) Temperature Range HA-5340-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . ±12V to ±18V θJA (oC/W) θJC (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package, Note 1) . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation must be designed to maintain the junction temperature below 150oC for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). NonInverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified TEMP. (oC) MIN TYP MAX UNITS Input Voltage Range Full -10 - +10 V Input Resistance (Note 3) 25 - 1 - MΩ Input Capacitance 25 - - 3 pF Input Offset Voltage 25 - - 1.5 mV Full - - 3.0 mV Offset Voltage Temperature Coefficient Full - - 30 µV/oC Bias Current 25 - ±70 - nA Full - - ±350 nA 25 - ±50 - nA Full - - ±350 nA Full -10 - +10 V 25 - 83 - dB Full 72 - - dB PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS Offset Current Common Mode Range ±10V, Note 4 CMRR TRANSFER CHARACTERISTICS Gain DC 25 110 140 - dB Gain Bandwidth Product CH External = 0pF Full - 10 - MHz CH External = 100pF Full - 9.6 - MHz CH External = 1000pF Full - 6.7 - MHz Rise Time 200mV Step 25 - 20 30 ns Overshoot 200mV Step 25 - 35 50 % Slew Rate 10V Step 25 40 60 - V/µs VIH Full 2.0 - - V VIL Full - - 0.8 V VIL = 0V Full - 7 40 µA VIH = 5V Full - 4 40 µA TRANSIENT RESPONSE DIGITAL INPUT CHARACTERISTICS Input Voltage Input Current 2 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). NonInverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified TEMP. (oC) MIN TYP MAX UNITS Output Voltage Full -10 - +10 V Output Current Full -10 - +10 mA Full Power Bandwidth (Note 5) Full 0.6 0.9 - MHz 25 - 0.05 0.1 Ω Full - 0.07 0.15 Ω Sample Mode 25 - 325 400 µVRMS Hold Mode 25 - 325 400 µVRMS Signal to Noise Ratio (RMS Signal to RMS Noise) VIN = 200kHz, 20VP-P Full - 115 - dB Total Harmonic Distortion VIN = 200kHz, 5VP-P Full -90 -100 - dBc VIN = 200kHz, 10VP-P Full -76 -82 - dBc VIN = 200kHz, 20VP-P Full -70 -74 - dBc VIN = 500kHz, 5VP-P Full -66 -75 - dBc VIN = 10VP-P, f1 = 20kHz, f2 = 21kHz Full -78 -83 - dBc VIN = 200kHz, 5VP-P 25 - 76 - dB VIN = 200kHz, 10VP-P 25 - 76 - dB VIN = 200kHz, 5VP-P 25 - -72 - dBc VIN = 200kHz, 10VP-P 25 - -66 - dBc VIN = 200kHz, 20VP-P 25 - -56 - dBc VIN = 100kHz, 5VP-P 25 - -84 - dBc VIN = 100kHz, 10VP-P 25 - -71 - dBc VIN = 100kHz, 20VP-P 25 - -61 - dBc VIN = 20kHz, 5VP-P 25 - -95 - dBc VIN = 50kHz, 5VP-P 25 - -91 - dBc VIN = 100kHz, 5VP-P 25 - -82 - dBc VIN = 10VP-P (f1 = 20kHz, f2 = 21kHz) 25 - -79 - dBc 10V Step to 0.01% 25 - 700 - ns Full - - 900 ns 10V Step to 0.1% 25 - 430 600 ns CH = Internal 25 - 0.1 - µV/µs Full - - 95 µV/µs 25 - 15 - mV PARAMETER TEST CONDITIONS OUTPUT CHARACTERISTICS Output Resistance Hold Mode Total Output Noise DC to 10MHz DISTORTION CHARACTERISTICS SAMPLE MODE Intermodulation Distortion HOLD MODE (50% Duty Cycle S/H) Signal to Noise Ratio (RMS Signal to RMS Noise) fS = 450kHz Total Harmonic Distortion fS = 450kHz fS = 450kHz fS = 2fIN(Nyquist) Intermodulation Distortion fS = 450kHz SAMPLE AND HOLD CHARACTERISTICS Acquisition Time Droop Rate Hold Step Error VIL = 0V, VIH = 4.0V, tR = 5ns 3 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). NonInverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS Hold Mode Settling Time To ±1mV Full - 200 300 ns Hold Mode Feedthrough 20VP-P, 200kHz, Sine Full - -76 - dB EADT (Effective Aperture Delay Time) 25 - -15 - ns Aperture Uncertainty 25 - 0.2 - ns Positive Supply Current Full - 19 25 mA Negative Supply Current Full - 19 25 mA Full 75 82 - dB POWER SUPPLY CHARACTERISTICS PSRR 10% Delta NOTES: 3. Derived from Computer Simulation only, not tested. 4. +CMRR is measured from 0V to +10V, -CMRR is measured from 0V to -10V. 5. Based on the calculation FPBW = Slew Rate/2πVPEAK (VPEAK = 10V). 4 HA-5340 Test Circuits and Waveforms 1 2 S/H CONTROL INPUT 16 -INPUT OUTPUT 8 VO +INPUT 12 S/H CONTROL NC HA-5340 (CH = 135pF = INTERNAL) FIGURE 1. HOLD STEP ERROR AND DROOP RATE HOLD (+4.0V) SAMPLE (0V) S/H CONTROL HOLD (+4.0V) SAMPLE (0V) S/H CONTROL VO ∆VO VO ∆t VP NOTES: NOTE: 7. Observe the voltage “droop”, ∆VO/∆t. 6. Observe the “hold step” voltage VP. 8. Measure the slope of the output during hold, ∆VO/∆t. 9. Droop can be positive or negative - usually to one rail or the other not to GND. FIGURE 2. HOLD STEP ERROR FIGURE 3. DROOP RATE TEST V+ V IN 20VP-P 200kHz SINE WAVE AIN S/H CONTROL INPUT VHA-5340 ANALOG MUX OR SWITCH NOTE: 9 1 -IN 2 +IN 16 S/H CONTROL 6 10. Feedthrough in VOUT OUT SUPPLY GND 15 TO SUPPLY COMMON 8 V OUT - where: dB = 20 log -------------V IN VOUT = VP-P , Hold Mode, VIN = VP-P REF COM 7 TO SIGNAL GND FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION 5 ®Teflon is a registered Trademark of Dupont Corporation. HA-5340 Application Information errors. Teflon® , polystyrene and polypropylene dielectric capacitor types offer good performance over the specified operating temperature range. The HA-5340 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN517 for a collection of circuit ideas. The hold capacitor terminal (pin 12) remains at virtual ground potential. Any PC connection to this terminal should be kept short and “guarded” by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01µF to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 15. Typical Application Figure 5 shows the HA-5340 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the HA-5340’s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The ideal ground connections are pin 7 (SIG. GND) directly to the system Signal Ground, and pin 15 (Supply Ground) directly to the system Supply Common. Hold Capacitor The HA-5340 includes a 135pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 8 and 12. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. The HA-5340 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. The hold capacitor CH should have high insulation resistance and low dielectric absorption, to minimize droop -15V +15V OFFSET ADJUST ≈ ±15mV CH 50kΩ 3 4 6 12 9 HI - 774 120pF 1 2 VIN 8 13 15pF INPUT 16 S/H CONTROL H S 15 7 5 9 SYSTEM POWER GROUND DIGITAL OUTPUT CONVERT HA - 5340 SYSTEM SIGNAL GROUND R/C ANALOG COMMON NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE 6 HA-5340 Typical Performance Curves TA = 25oC, VS = ±15V, Unless Otherwise Specified 4V S/H CONTROL S/H CONTROL 0V 4V 0V 10V 0pF 470pF 0V 1000pF VOUT FIGURE 7. TACQ vs ADDITIONAL CH 2300 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 ACQUISITION TIME TO ±1mV (ns) DROOP RATE (µV/µs) FIGURE 6. TACQ POS 0 TO +10 STEP 125oC 100oC 75oC 2100 1900 1700 1500 1300 1100 900 700 1 10 100 0 1000 400 800 1200 1600 2000 2400 EXTERNAL HOLD CAPACITANCE (pF) EXTERNAL HOLD CAPACITANCE (pF) FIGURE 8. DROOP RATE vs HOLD CAPACITANCE FIGURE 9. ACQUISITION TIME (0.01%) vs HOLD CAPACITANCE 20 13 11 VIH = 4V CH = 470pF HOLD STEP ERROR (mV) CH = INTERNAL TEMPERATURE = 25oC 12 HOLD STEP ERROR (mV) 2200pF VOUT 10 9 8 7 VIH = 3V 6 5 4 3 2 10 0 VIH = 4V 1 0 5 10 15 TRISE (ns) FIGURE 10. HOLD STEP ERROR vs TRISE 7 20 -10 -55 -35 -15 0 25 50 75 100 TEMPERATURE (oC) FIGURE 11. HOLD STEP ERROR vs TEMPERATURE 125 HA-5340 Typical Performance Curves TA = 25oC, VS = ±15V, Unless Otherwise Specified 20 VIH = 4V, CH = INTERNAL tR = 5ns, 10ns, 20ns TRISE = 5ns TA = 25oC 12 HOLD STEP ERROR (mV) HOLD STEP ERROR (mV) 14 10 8 6 4 (Continued) 10 5ns 10ns 20ns 0 VIH = 4V 2 200 400 600 800 -10 -55 1000 -35 -15 0 25 90 0 0 PHASE -90 AV = +100, ±15V AND ±12V SUPPLIES (NOTE) 1K 10K MAGNITUDE (dB) 180 MAGNITUDE 20 1M 100 125 180 40 MAGNITUDE CH = 1000pF 20 90 CH = 470pF CH = 0pF 0 0 PHASE -90 CH = 1000pF CH = 470pF CH = 0pF -180 100K 75 FIGURE 13. HOLD STEP ERROR vs TEMPERATURE PHASE ANGLE (DEGREES) MAGNITUDE (dB) FIGURE 12. HOLD STEP ERROR vs HOLD CAPACITANCE 40 50 TEMPERATURE (oC) EXTERNAL HOLD CAPACITANCE (pF) PHASE ANGLE (DEGREES) 0 1K 10M 10K 100K -180 AV = +100 1M 10M NOTE: ±15V and ±12V supplies trace the same line within the width of the line, therefore only one line is shown. FIGURE 14. CLOSED LOOP PHASE/GAIN FIGURE 15. CLOSED LOOP PHASE/GAIN -20 -20 fSAMPLE ≅ 450kHz VOUT = 5VP-P HA-5320 SAMPLE AND HOLD MODES THD (dBc) THD (dBc) -60 HA-5320 SAMPLE AND HOLD MODES -40 -40 HA-5340 HOLD MODE -60 HA-5340 HOLD MODE -80 -80 HA-5340 SAMPLE MODE HA-5340 SAMPLE MODE -100 -100 0 100K 200K 300K 400K FREQUENCY (Hz) FIGURE 16. THD vs FREQUENCY 8 500K 5 VOUT P-P 10 at 200kHz, fSAMPLE @ 450kHz FIGURE 17. THD vs VOUT 20 HA-5340 Die Characteristics PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kÅ ± 2.0kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ DIE DIMENSIONS: 84mils x 139mils x 19mils METALLIZATION: SUBSTRATE POTENTIAL (POWERED UP): Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ VTRANSISTOR COUNT: 196 Metallization Mask Layout (12) EXTERNAL HOLD CAP HA-5340 SUPPLY (15) GND S/H (16) CONTROL (9) +VSUPPLY -IN (1) (8) OUTPUT (8) OUTPUT +IN (2) 9 -VSUPPLY (6) OFFSET ADJ (4) OFFSET ADJ (3) (7) SIG GND HA-5340 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 16 0o 16 8o 0o 7 8o 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 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