Lattice USB3 Video Bridge Development Kit User’s Guide August 2014 EB88_1.0 Lattice USB3 Video Bridge Development Kit Introduction The Lattice USB3 Video Bridge board allows designers to investigate and experiment with the features of the LatticeECP3™ Field-Programmable Gate Array device in applications of transporting video and audio data through the Universal Serial Bus (USB) 3.0 link. The Lattice USB3 Video Bridge board is the hardware platform of the Lattice USB3 Video Bridge Development Kit. Combined with the control and configuration application software and drivers, the features of the Lattice USB3 Video Bridge board can assist design engineers with rapid prototype and validation of their specific USB3 Video Bridge designs. This guide is intended to be referenced in conjunction with the RD1203, Lattice USB3 Video Bridge Reference Design User's Guide to demonstrate the capability and performance of LatticeECP3 FPGA. Features Key features of the Lattice USB 3.0 Video Bridge Development Kit include: • SuperSpeed USB 3.0 Interface over Cypress EZ-USB FX3 (CYUSB3014) IC • HDMI interface over Analog Devices ADV7611 IC • Embedded SDI Receiver interface with TI LMH0394 Cable Equalizer • Si5338 programmable clock generator • LatticeECP3-17 FPGA programmed with USB3 Video and Audio bridge function • Expansion connector for Image sensors using SubLVDS or MIPI CSI-2 • Selectable expansion VCCIO • Selectable power supply (USB or Auxiliary 5V) • Fly-wire ispDownload cable connection for JTAG fast program and Reveal Analyzer • SPI serial flash controlled by the FX3 USB controller • FPGA configuration at startup by the FX3 via the ispCONFIG SPI interface • I2C and SPI bus for onboard device controls from the FX3 • FX3 JTAG Connector • 2-pin GPIO debug connector (LVTTL) useful for I2C or UART General Description The Lattice USB3 Video Bridge Development Kit is built around the LatticeECP3-17EA 328-ball csBGA FPGA device. The board with the FPGA, peripheral devices and connectors provide a seamless USB3 bridge function for video streaming and capturing applications utilizing the USB 3.0 USB Video Class (UVC) standard. It also supports multi-channel I2S PCM audio streaming through the same USB3 link. The parallel video and audio interface from the ADV7611 HDMI Receiver, the embedded CML SERDES Receiver interface, and differential I/Os on the sensor expansion header are useful for evaluating various Lattice IP cores for video interfacing, as well as the USB 3.0 UVC bridge design. A number of test points are provided to validate various power and configuration status. Figure 1 shows the conceptual connections between LatticeECP3 FPGA device and other peripheral components of the USB3 Bridge board. The contents of this user's guide include top-level functional descriptions of the various portions of the board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics. 2 Lattice USB3 Video Bridge Development Kit Figure 1. Lattice USB3 Video Bridge Board Block Diagram EZ USB FX3 Bank 0 Bank 1 Bank 8 Bank 2 LatticeECP3-17EA Expansion connector cs328BGA Bank 7 Bank 3 Quad A Bank 6 Ch0 Ch1 Ch2 Ch3 Ref clk 100 MHz ADV7611 SDI Initial Setup and Handling The following is recommended reading prior to removing the evaluation board from the static shielding bag and may or may not apply to your particular use of the board. CAUTION: The devices on the board can be damaged by improper handling. The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance or larger capacitance than the respective ESD specifications can potentially damage or degrade the devices on the evaluation board. As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a while, it is best to put it back in the static shielding bag. Please save the static shielding bag and packing box for future storage of the board when it is not in use. When reaching for the board, it is recommended that you first touch the outside shield portion of the SDI connector. This will neutralize any static voltage difference between your body and the board prior to any contact with signal I/O. CAUTION: To minimize the possibility of ESD damage, the first and last electrical connections to the board should always be from test equipment chassis ground to the pin 1 of the J3 header. 3 Lattice USB3 Video Bridge Development Kit Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment to the to the pin 1 of the J3 header. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged, should be the chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board. If you are holding or carrying the board when it is not in a static shielding bag, please keep one finger on the outside shield portion of the SDI connector. This will keep the board at the same voltage potential as your body until you can pick up the Dstatic shielding bag and put the board back in it. Electrical, Mechanical and Environmental Specifications The nominal board dimensions are 99 mm x 69 mm. On the physical board itself, connectors include pin 1 indicators as a dot, or a number “1” beside the pin 1 on the outer layer silk screen. The environmental specifications are as follows: • Operating temperature: 0 °C to 55 °C • Storage temperature: -40 °C to 75 °C • Humidity: <95% without condensation • 5 V DC Functional Description Figure 2. Lattice USB3 Video Bridge Board, Top View Analog Devices ADV7611 HDMI 1.4a Receiver Lattice ECP3-17EA cs328BGA Package (10 mm X 10 mm) HDMI 1.4a Input Cypress EZ-USB FX3 CYUSB3014 (10 mm X 10 mm csBGA) Micro-USB 3.0 Super Speed Connector Board Power Select SDI Equalizer (TI) Auxillary 5 V Power SDI Input SD-, HD-, 3G-SDI Expansion Connection SubLVDS, MIPI Expansion VCCIO Select 4 Lattice USB3 Video Bridge Development Kit LatticeECP3 Device This board features a LatticeECP3-17 FPGA with a 1.2 V DC core in a 328-ball csBGA 10 mm x10 mm package. A complete description of this device can be found on the Lattice web site at www.latticesemi.com/products/fpga/ecp3. USB3 Connector (J8) The board is powered and communicates with the USB 3.0 Host through an USB 3.0 Micro b connector/receptacle. It is connected to the host with the provided USB 3.0 A-to-Micro b cable. Auxiliary Power Connector (J9) The board can be alternately supplied by a single 5 V DC power supply at J9. On-board step-down switching regulators then provide the necessary supply voltages: 3.3 V, 2.5 V, 1.8 V, 1.2 V. For proper operation, the 5 V DC power applied at J9 should be within the range of +4,75 V min. to +5,25 V max. The requirements for the J10 power jack itself are listed in Table 1. Table 1. Auxiliary Power Jack J9 Specifications Polarity Positive Center Inside diameter 0.1'' (2.5 mm) Outside diameter 0.218'' (5.5 mm) Current Capacity Up to 2.5 A Power Supplies The on-board switching and linear regulator output voltages can be measured at test points located around the board as shown in Table 2. Table 2. Test Points for On-Board Regulator Voltages Supply Regulator Test Point Resistor Ratio 5.0 V - TP2 NA 3.3 V U8 TP5 R73/R76 2.5 V U9 TP6 R77/R80 1.8 V U10 TP7 R82/R83 1.2 V U7 TP3 R70/R72 1.2 V (SERDES) U11 TP8 NA Comment Input voltage Each of the step-down switching regulators, U7, U8 and U9, incorporate typical resistor divider voltage feedback to divide down the regulator output voltage and compare it against an internal reference voltage. The regulator then adjusts the output voltage higher or lower such that the resistor divided voltage matches the internal reference. By doing this, the regulator output voltage remains at a constant voltage value independent of the load driven. Each regulator output voltage follows this equation: Vout= (1 + resistor ratio) x (regulator internal reference voltage) See the LT3685 and LTC3621 device data sheets for additional details about these devices. The 1.8 V regulator (U10) is a low dropout linear type regulator with an adjustable output voltage which is set using the external resistive divider. The output voltage is given by the formula: Vout= (1 + resistor ratio) x (Vadj) where Vadj is feedback voltage. 5 Lattice USB3 Video Bridge Development Kit See the LP38511 device data sheet for additional details about this device. The SERDES 1.2 V regulators (U11) are low dropout linear types that deliver a constant 1.2 V output voltage when powered by the 2.5 V input voltage. In contrast to the switching regulators discussed above, the U11 linear regulators do not generate switching noise, so they are a good choice for powering the LatticeECP3 SERDES to give the lowest jitter generation. Also, U11 does not use resistor divider networks to set the output voltage, instead it is set up to directly copy its own internal 1.215 V reference voltage to its outputs. The U11 regulator outputs are available for testing at test points TP8 and TP9. See the LT3029 device data sheets for additional details about this device. When using the various I/O test points located around the board, be sure to not exceed the LatticeECP3 Family Data Sheet specified absolute maximum rating for Output Supply Voltage VCCIO range of -0.5 V to +3.75 V, or damage to the device may occur. Also, for I/O input capability of the various I/O standards supported by the LatticeECP3 sysIO structures, see the LatticeECP3 sysIO Usage Guide. Cypress EZ-USB FX3 (U5) Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 integrates a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. It provides simple connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA. FX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables 375-MBps data transfer from GPIF II to the USB interface. For more information on the EZ-USB http://www.cypress.com/?docID=44322. FX3, please refer to the EZ-USB FX3 Datasheet GPIF II Interface The GPIF II interface implements the Slave FIFO signaling to receive the UVC and UAC packeted streaming data from the LatticeECP3. For more information about the Slave FIFO interface, please consult the EZ-USB FX3 Datasheet technical reference manual http://www.cypress.com/?docID=44322. The signal connections between the EZUSB FX3 and the Lattice ECP3 Device are shown in Table 3. Table 3. LatticeECP3(U1) connections to EZ-USB FX3 (U5) GPIF II interface Signal sysIO Bank LatticeECP3 BGA Ball EZ-USB FX3 Interface Signal sf_data[0] 8 D18 dq[0] sf_data[1] 1 A12 dq[1] sf_data[2] 0 B10 dq[2] sf_data[3] 8 L17 dq[3] sf_data[4] 8 A16 dq[4] sf_data[5] 1 A11 dq[5] sf_data[6] 8 H18 dq[6] sf_data[7] 8 D17 dq[7] sf_data[8] 8 J18 dq[8] sf_data[9] 8 F17 dq[9] sf_data[10] 8 J17 dq[10] sf_data[11] 8 F19 dq[11] sf_data[12] 8 J19 dq[12] 6 Lattice USB3 Video Bridge Development Kit LatticeECP3 BGA Ball EZ-USB FX3 Interface Signal 1 B13 dq[13] 8 G18 dq[14] sf_data[15] 1 A14 dq[15] sf_data[16] 0 C7 dq[16] sf_data[17] 0 B8 dq[17] sf_data[18] 0 C6 dq[18] sf_data[19] 0 B4 dq[19] sf_data[20] 0 B7 dq[20] sf_data[21] 0 A7 dq[21] sf_data[22] 0 A6 dq[22] sf_data[23] 0 B5 dq[23] sf_data[24] 0 A9 dq[24] sf_data[25] 0 B3 dq[25] sf_data[26] 0 A5 dq[26] sf_data[27] 0 A4 dq[27] sf_data[28] 0 C10 dq[28] sf_data[29] 0 A3 dq[29] sf_data[30] 0 B6 dq[30] sf_data[31] 0 A8 dq[31] sf_addr[0] 1 B11 ctl[12] Signal sysIO Bank sf_data[13] sf_data[14] sf_addr[1] 0 C9 ctl[11] sf_csn 1 C12 ctl[0] sf_wen 1 A13 ctl[1] sf_oen 1 B12 ctl[2] sf_rdn 8 A15 ctl[3] sf_pktend 8 B16 ctl[7] sf_clko 0 B9 pclk sf_flaga 1 C11 ctl[4] sf_flagb 1 C13 ctl[5] SPI Serial Flash (U12) The U12 SPI Flash device used on this board is a 16-pin, 16-Mbit device, operated by the EZ-USB FX3. It is sufficient to store both the EZ-USB FX3 Firmware and the LatticeECP3 Bitstream. The EZ-USB FX3 will boot from the SPI flash, then read out and download the LatticeECP3 Bitstream over the Slave SPI sysCONFIG interface. The SPI Flash device is an STMicro SPI-M25P16 in an 8-pin package. LatticeECP3 IO Bank Voltages Most of the bank voltages on the LatticeECP3-17 device (U1) have been hard-wired to specific power supply values, except for the bank 2 which can be set to different voltage levels to support various sensor and camera interfaces through the expansion connector J1. The voltage assignment is shown in Table 4. 7 Lattice USB3 Video Bridge Development Kit Table 4. LatticeECP3 (U1) Bank Voltage Settings LatticeECP3 Bank VCCIO Voltage Comment 0 and 1 2.5 V 2 Adjustable 3 3.3 V Expansion connector SubLVDS, MIPI 6 3.3 V ADV7611, I2C and UART bus 7 3.3 V ADV7611 8 2.5 V LatticeECP3 programming, EZ-USB FX3 Quad A 1.2 V SERDES EZ-USB FX3 Expansion connector SubLVDS, MIPI 3.3 V: Jumper on J2 pins 1-2 2.5 V: Jumper on J2 pins 3-4 1.2 V: Jumper on J2 pins 5-6 Clock Sources There are two crystals, two oscillators, and a programmable clock generator on the Lattice USB 3.0 Video Bridge Development Kit. The two crystals are used as clocks for the ADV7611 and the EZ-USB FX3. One oscillator is used to provide the 32.768 kHz RTC clock to the EZ-USB FX3, While the 27 MHz oscillator is used as the reference clock for the Si5338 clock generator, which is used to drive the (by default 100 MHz) system and GPIF interface frequency to the LatticeECP3 (U1), as well as the reference differential clock to the LatticeECP3 SERDES used for the SDI interface. Table 5 shows the oscillator usage. Locations Y2 and Y3 are the oscillators. Table 5. LatticeECP3 (U1) LatticeECP3 Input and IO Setting Source Frequency Comment Y1 28.63636 MHz ADV7611 pins 58 and 59 - Y2 27 MHz SI5338 pin 3 - Y3 32.768 kHz CYUSB3014 pin D6 - Y4 19.2 MHz CYUSB3014 pins C6 and C7 Si5338 CLK0 (A/B) Adjustable QuadA pins U10 and T10 Si5338 CLK2 (A) Adjustable (100 MHz Typ.) LatticeECP3 pin R2 HDMI Video Input The HDMI Video input is connected to the Analog Devices ADV7611 (U3). The ADV7611 is an HDMI receiver that supports all mandatory 2D and 3D video formats defined in HDMI 1.4a. It supports HDMI audio extraction and has an audio output port for the audio data extracted from the HDMI stream. Accessible audio formats are: a stream from the I2S serializer (two audio channels), a stream from the S/PDIF serializer (two uncompressed channels or N compressed channels, for example, AC3) and DST stream. The LatticeECP3 interfaces to the ADV7611 as shown in Table 6. Table 6. LatticeECP3(U1) connections to ADV7611 (U3) Signal sysIO Bank LatticeECP3 BGA Ball ADV7611 Signal vp[2] 7 F3 p[0] vp[3] 7 F1 p[1] vp[4] 7 G1 p[2] vp[5] 7 H1 p[3] vp[6] 7 J1 p[4] 8 Lattice USB3 Video Bridge Development Kit Signal sysIO Bank LatticeECP3 BGA Ball ADV7611 Signal vp[7] 7 H3 p[5] vp[8] 7 G2 p[6] vp[9] 7 L1 p[7] vp[12] 7 G3 p[8] vp[13] 7 J2 p[9] vp[14] 7 K2 p[10] vp[15] 7 J3 p[11] vp[16] 7 H2 p[12] vp[17] 7 L2 p[13] vp[18] 7 N2 p[14] vp[19] 7 N3 p[15] vp[22] 7 M2 p[16] vp[23] 6 R3 p[17] vp[24] 7 N1 p[18] vp[25] 6 T2 p[19] vp[26] 6 V1 p[20] vp[27] 6 T3 p[21] vp[28] 7 L3 p[22] vp[29] 7 M1 p[23] hs 7 E3 hs vs 7 D2 vs/field/alsb de 7 E2 de pclk 7 M3 llc lrclk_a 7 D3 lrclk sclk_a 7 D1 sclk/int2 i2s0_a 7 E1 ap adv_t_rst_n 6 V2 resetn SDI Video Input The SDI Video input is connected to the Texas Instruments LMH0394 (U2) SDI cable equalizer. The equalizer operates over a wide range of data rates, from 125 Mbps to 2.97 Gbps and supports SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M standards. The signal connections between the LatticeECP3 device and the LMH0394 are shown in Table 7. Table 7. LatticeECP3(U1) connections to LMH0384 (U2) Signal sysIO Bank Polarity LatticeECP3 BGA Ball LMH0394 signal sdi_inp_ch0 Quad A P W14 SDO sdi_inn_ch0 Quad A N W15 SDOn 9 Lattice USB3 Video Bridge Development Kit Expansion Connector (J1) Expansion connector Molex 52559-3652 is provided to connect the LatticeECP3 to a camera or a sensor. Various camera or sensor module interfaces are supported: parallel, SubLVDS or MIPI-CSI-2. Adapter boards are available for various camera/sensor options: HDR-60 NanoVesta connector with SubLVDS lines (MN34041), Sony FCBMA130 Block camera with MIPI CSI-2 interface. The signal connections between the LatticeECP3 device and the Molex expansion connector are shown in Table 8. Table 8. LatticeECP3(U1) Connections to Molex Expansion Connector (J1) Signal sysIO Bank Polarity LatticeECP3 BGA Ball Molex pin number mipi_dck_p 3 P P17 11 mipi_dck_n 3 N P19 12 mipi_d0_p 3 P R18 13 mipi_d0_n 3 N R17 14 mipi_d1_p 3 P T17 15 mipi_d1_n 3 N T18 16 mipi_d2_p 3 P R19 17 mipi_d2_n 3 N T19 18 mipi_d3_p 3 P U18 19 mipi_d3_n 3 N U19 20 mipi_gpio0 2 - L18 31 mipi_gpio1 2 - K18 32 mipi_gpio2 3 - V18 33 mipi_gpio3 3 - V19 34 mipi_lp0_0 2 - M18 24 mipi_lp0_1 2 - M19 23 mipi_lpclk_0 2 - L19 28 mipi_lpclk_1 2 - N17 27 Configuration/Programming Header (J4) The J4 JTAG 1x10 header is provided on the board for accessing the LatticeECP3 JTAG port. It can be used for downloading the LatticeECP3 FPGA bitstream and reveal troubleshooting. It cannot be used for SPI Flash programming. Pin # Description LatticeECP3 BGA Ball Pin 1 VCC - Pin 2 TDO B1 Pin 3 TDI C1 Pin 4 PROGRAMN C19 Pin 5 NC - Pin 6 TMS A2 Pin 7 GND - Pin 8 TCK B2 Pin 9 DONE E19 Pin 10 INITN C18 10 Lattice USB3 Video Bridge Development Kit Debug Header (J3) For general testing and debugging purposes I/Os on the LatticeECP3 are brought to dedicated connector header J3. The signal connections between the LatticeECP3 device and the J3 header are shown in Table 9. Table 9. LatticeECP3(U1) connections to debug header (J3) Signal sysIO Bank LatticeECP3 BGA Ball J3 header pin number dbg_0 6 T1 1 dbg_1 6 U1 2 Default Jumper Settings Figure 3. Default Jumper Settings - J10 J10 On: 5 V On: 5 V USB VCC Figure 3 shows the Lattice USB3 Video Bridge Board default jumper settings of J10 header. J10 selects the power supply source for the board. By installing a jumper between pins 1-2 of the J10 header, the board is supplied by a single 5 V DC power supply at J9. The board is powered through an USB 3.0 Micro b connector/receptacle. Figure 4. Default Jumper Settings - J2 J2 3.5 V VCC_Bank2 2.5 V 1.2 V J2 selects the IO bank power supply for the LatticeECP3 bank 2. Placing a jumper on J2 pins 1-2 selects 3.3 V, jumper on J2 pins 3-4 selects 2.5 V and jumper on J2 pins 5-6 selects 1.2 V. LEDs There is one LED (D7) on the Lattice USB3 Video Bridge Board which indicates the power-on status of the board. 11 Lattice USB3 Video Bridge Development Kit Board Programming/Configuration After initial board setup, use the following procedure to program the board. There is an onboard SPI flash memory (U12) which stores the image file of both FX3 firmware and FPGA bitstream. The SPI flash memory can be programmed through the USB3 link by the USB3 Configurator application installed on the Windows PC. The image file then will be automatically loaded to program and configure the FX3 and FPGA devices during power-up. The USB3 Bridge is equipped with two separated JTAG connectors which allow the user to configure the SRAM of the FPGA and FX3 devices respectively. The J4 connector is connected to the JTAG port of ECP3-17 device and is useful for on-chip debug using Reveal Analyzer tool; the J7 connector is connected to the JTAG port of FX3 device for SRAM configuration and debugging using Cypress USB Suite Control Center tool. For more details of Lattice ECP3 FPGA configuration, please refer to TN1169, LatticeECP3 sysCONFIG Usage Guide. Install the Configurator and Drivers Lattice USB3 Video Bridge Development Kit provides a versatile USB3 Configurator tool to allow the user to program and configure the FX3 and FPGA devices within a unified Windows GUI. The configurator application is also used to control the video input and format for the USB Video Bridge demonstration. Follow the procedure below to install the USB3 Video Bridge Configurator application. 1. Go to Lattice USB3 Video Bridge Development Kit website (www.latticesemi.com/usb3) to download the development kit. DK-ECP3-USB3-xxx.zip. [xxx] represents the revision of the development kit 2. Unzip the kit and copy all the files to the default \Lattice_DevKits directory or any user-specified directory 3. Go to the sub-directory <install_dir>\DK-ECP3-USB3-xxx\Software and run the setup.exe installer. 4. Accept the license agreement and continue to install the Configurator application to the \Program Files\Lattice USB 3.0 Video Bridge Configurator folder. The Cypress USB Bootloader and Lattice USB3 Video Converter driver will be installed as part of the USB3 Video Bridge Configurator installation. Download USB3 Firmware 1. Connect the Lattice USB3 Video Bridge board to the PC’s USB 3.0 port colored in blue, or marked with the USB SuperSpeed logo. It is also suggested to use the USB 3.0 ports which can provide extra power (additionally marked with a lightning icon). 2. The board will enumerate after approximately 15 seconds and appear in the Devices and Printers folder as a Lattice USB3 Video Bridge device. You can also check the same device name under the Imaging devices and Sound, video and game controller categories of the Device Manager. Note: The on-board SPI flash memory is pre-loaded with the firmware and bitstream for the USB3 Video Bridge demo. If the board is not pre-loaded with the USB3 Video Bridge firmware, the default driver invoked is Cypress USB Bootloader. 3. After opening the USB3 Video Bridge Configurator application, the USB3 device should appear in the Device dialog box. 12 Lattice USB3 Video Bridge Development Kit Figure 5. Device Dialog Box USB3 Device 4. Click the USB3 Firmware Download button and choose the appropriate USB3 firmware file (Disc image file) from <install_dir>\DK-ECP3-USB3-xxx\Demonstration\FX3_firmware folder in the pop-up window. 5. Restart the board by recycling the board power supply if pins 1-2 of J10 are shunted; or unplug and re-plug in the USB 3.0 cable if pin 2 and pin 3 of J10 are shunted. 13 Lattice USB3 Video Bridge Development Kit Figure 6. USB3 Firmware Download Button Download USB3 Firmware Download FPGA Bitstream Repeat steps 1 and 2 in the Download USB3 Firmware section above if the board is not powered on and plugged into the USB 3.0 port of the PC. Download the FPGA bitstream by clicking the FPGA Bitfile Download button in the USB3 Video Bridge Configurator application and choosing the bitstream from the <install_dir>\DK-ECP3USB3-xxx\Demonstration\ECP3_bitstream folder in the pop-up window. 14 Lattice USB3 Video Bridge Development Kit Figure 7. FPGA Bitfile Download Button Download ECP3 Bitstream After the download has completed, the following message should appear in the communication status box. 15 Lattice USB3 Video Bridge Development Kit Figure 8. Communication Status Box Communication Status Configure Audio Device The Lattice USB3 Video Bridge can transfer audio data through a USB isochronous mode endpoint. The demo design supports two-channel 16-bit PCM audio data of 48 KHz sampling rate. It preserves the resources to support more audio channels of different sampling rate and audio data width (e.g. eight-channel 24-bit 96 KHz sampling rate) for future development. After the success of the board enumeration, the Lattice USB 3.0 Video Bridge device should appear in the Device Manager under both the Imaging devices and the Sound, video and game controllers device categories. Depending on the Windows operating system, the Lattice USB 3.0 Video Bridge may not be chosen as the default audio device. Follow the procedure described below to configure and enable the audio device in Windows Control Panel. 1. Go to Control Panel > Hardware and Sound folder and open the Sound link. This opens a new Sound configuration window. 2. Select the Recording tab, click on Lattice USB 3.0 Video Bridge and set it as the default Microphone device. See Figure 9. 3. Click the Properties button to open the Microphone Properties window. 4. Select the Listen tab, select the Listen to this device check box and click the Apply button to accept the change. See Figure 10. After enabling Lattice USB 3.0 Video Bridge as the default Microphone device, the Lattice USB3 Video Bridge board is ready to stream both video and audio to the Windows PC equipped with the USB 3.0 port. 16 Lattice USB3 Video Bridge Development Kit Figure 9. Sound-Recording Tab Configuration 17 Lattice USB3 Video Bridge Development Kit Figure 10. Microphone Properties – Listen Tab Configuration Ordering Information Description Ordering Part Number Lattice USB3 Video Bridge Development Kit LFE3-17EA-USB3-EVN Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com 18 China RoHS Environmental Friendly Use Period (EFUP) Lattice USB3 Video Bridge Development Kit Revision History Date Version August 2014 1.0 Change Summary Initial release. © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 19 20 D C B A CY_DQ20 CY_DQ21 CY_DQ16 CY_DQ22 CY_DQ30 CY_DQ18 CY_DQ23 CY_DQ26 CY_DQ19 CY_DQ27 CY_DQ25 CY_DQ29 CY_DQ2 CY_DQ28 CY_IFCLK CY_ADR1 CY_DQ24 CY_DQ17 CY_DQ31 1 2 LFE3-17EA-328 GND 1uF GND 1uF C5 10nF C6 100nF Bank 1 PT46B/TDQ43/VREF2_1/C PT46A/TDQ43/VREF1_1/T PT43B/TDQS43_N/C PT43A/TDQS43_P/T PT38B/TDQ43/C PT38A/TDQ43T PT35B/TDQ34/C PT35A/TDQ34/T PT31B/TDQ34/PCLKC1_0/C PT31A/TDQ34/PCLKT1_0/T U1B C2 E7 E9 F8 A14 A13 C13 B13 C12 B12 A12 A11 C11 B11 C1 C4 10nF Bank 0 VCCIO0 VCCIO0 VCCIO0 VCC_2V5 CY_DQ15 CY_SLWR CY_FLAGB CY_DQ13 CY_SLCS_N CY_SLOE CY_DQ1 CY_DQ5 CY_FLAGA CY_ADR0 VCC_2V5 C3 100nF LFE3-17EA-328 PT28B/TDQ25/PCLKC0_0/C PT26B/TDQ25/C PT28A/TDQ25/PCLKT0_0/T PT26A/TDQ25/T PT25B/TDQS25_N/C PT23B/TDQ25/C PT25A/TDQS25_P/T PT23A/TDQ25/T PT22B/TDQ25/C PT20B/TDQ25/C PT22A/TDQ25/T PT20A/TDQ25/T PT13B/TDQ16/C PT13A/TDQ16/T PT10B/TDQ7/C PT10A/TDQ7/T PT7B/TDQS7_N/C PT7A/TDQS7_P/T PT4B/TDQ7/VREF2_0/C PT4A/TDQ7/VREF1_0/T U1A 2 VCC_2V5 B10 C10 B9 C9 A9 B8 A8 C8 B7 A7 C7 A6 B6 C6 B5 A5 B4 A4 B3 A3 1 E11 E13 F12 VCC_2V5 Revision:0.9 3 Date: 3.6.2014. Sheet 1 of 17 Time: 16:38:46 File: H:\work\Lattice_prj0_revB\ecp3_bank0_bank1.SchDoc Number: 1 Lattice_prj0 Siz e: A4 Title VCCIO1 VCCIO1 VCCIO1 3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * 4 CY_DQ0 CY_DQ1 CY_DQ2 CY_DQ3 CY_DQ4 CY_DQ5 CY_DQ6 CY_DQ7 CY_DQ8 CY_DQ9 CY_DQ10 CY_DQ11 CY_DQ12 CY_DQ13 CY_DQ14 CY_DQ15 CY_DQ16 CY_DQ17 CY_DQ18 CY_DQ19 CY_DQ20 CY_DQ21 CY_DQ22 CY_DQ23 CY_DQ24 CY_DQ25 CY_DQ26 CY_DQ27 CY_DQ28 CY_DQ29 CY_DQ30 CY_DQ31 4 CY_DQ[0..31] D C B A Lattice USB3 Video Bridge Development Kit Appendix A. Schematics Figure 11. Sheet 1 of 17 21 D C B A VCC_2V5 VCC_3V3 GND 1uF C7 2 4 6 1 R6 R7 R8 R9 MIPI_LP0_1 MIPI_LP0_0 MIPI_LPCLK_1 MIPI_LPCLK_0 Place R6-R9 close to the ECP3 J2 1 3 5 C9 10nF 0R 0R 0R 0R R5 51R 51R 51R MIPI_GPIO6 MIPI_GPIO7 CY_SCL CY_SDA MIPI_GPIO0 MIPI_GPIO1 MIPI_GPIO2 MIPI_GPIO3 MIPI_GPIO4 MIPI_GPIO5 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 37 40 39 38 37 40 39 Molex 52559-3652 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 J1 MIPI_D0_N MIPI_D0_P MIPI_DCK_N MIPI_DCK_P MIPI_DCK_N MIPI_D0_P MIPI_D0_N MIPI_D1_P MIPI_D1_N MIPI_D2_P MIPI_D2_N MIPI_D3_P MIPI_D3_N MIPI_GPIO2 MIPI_GPIO3 Place R2-R5 close to the ECP3 Lengths between lines should bematched MIPI_DCK_P VCC_BANK2 51R J13 K14 MIPI_DCK_P MIPI_DCK_N MIPI_D0_P MIPI_D0_N MIPI_D1_P MIPI_D1_N MIPI_D2_P MIPI_D2_N MIPI_D3_P MIPI_D3_N VCC_5V VCC_3V3 MIPI_LP0_0 R4 R3 MIPI_LPCLK_0 MIPI_LP0_1 R2 VCCIO2 VCCIO2 MIPI_LPCLK_1 GND Bank 2 VCC_BANK2 C8 100nF LFE3-17EA-328 PR26E_D/RUM0_GPLLT_IN_B/C PR26E_C/RUM0_GPLLT_IN_A/T PR26B/RDQ23/PCLKC2_0/C(LVDS)* PR24B/RDQ23/C PR26A/RDQ23/PCLKT2_0/T(LVDS)* PR20B/RDQ23/RUM0_GDLLT_IN_B/C(LVDS)* PR18B/RDQ23/VREF2_2/C PR20A/RDQ23/RUM0_GDLLT_IN_A/T(LVDS)* PR18A/RDQ23/VREF1_2/T U1C VCC_BANK2 VCC_1V2_CORE MIPI_LPCLK_0 MIPI_GPIO0 MIPI_GPIO1 MIPI_LPCLK_1 MIPI_LP0_1 MIPI_LP0_0 N19 N18 N17 M19 M18 M17 L19 L18 K18 1 3 C11 10nF Number: 2 C12 100nF Revision:0.9 XRES VCCIO3 VCCIO3 VCCIO3 3 Sheet 2 of 17 Time: 16:38:46 Date: 3.6.2014. File: H:\work\Lattice_prj0_revB\ecp3_bank2_bank3.SchDoc Siz e: A4 Lattice_prj0 GND 1uF C10 VCC_3V3 LFE3-17EA-328 Bank 3 PR29A/RDQ32/PCLKT3_0/T(LVDS)* PR29B/RDQ32/PCLKC3_0/C(LVDS)* PR32A/RDQS32_P/T PR32B/RDQS32_N/C PR35A/RDQ32/VREF1_3/T(LVDS)* PR35B/RDQ32/VREF2_3/C(LVDS)* PR41A/RDQS41_P/T PR41B/RDQS41_N/C PR44A/RDQ41/T(LVDS)* PR44B/RDQ41/C(LVDS)* PR53A/RDQ50/T(LVDS)* PR53B/RDQ50/C(LVDS)* Title P17 P19 R18 R17 T17 T18 R19 T19 U18 U19 V18 V19 U1D R1 1% 10k Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * W18 M14 N13 P14 VCC_3V3 4 4 GND D C B A Lattice USB3 Video Bridge Development Kit Figure 12. Sheet 2 of 17 22 1 V6 V9 V12 V15 V7 V8 V13 V14 2 PCSA_VCCOB PCSA_VCCIB Title Lattice_prj0 VCC_PCS_IO FB1 Revision:0.9 FB2 C17 22uF C15 GND C20 1uF C14 C22 4 100nF 1uF C21 100nF 1uF C13 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * C23 22uF C19 C16 1uF BLM21AG601SN1D GND BLM21AG601SN1D C18 10nF 100nF C24 10nF PCSA_VCCIB 100nF PCSA_VCCOB B A Number: 3 3 Sheet 3 of 17 Date: 3.6.2014. Time: 16:38:46 File: H:\work\Lattice_prj0_revB\ecp3_pcs.SchDoc Siz e: A4 D PCS PCSA_VCCIB3 PCSA_VCCIB2 PCSA_VCCIB1 PCSA_VCCIB0 PCSA_VCCOB3 PCSA_VCCOB2 PCSA_VCCOB1 PCSA_VCCOB0 4 D LFE3-17EA-328 PCSA_HDINP3 PCSA_HDINN3 PCSA_HDOUTP3 PCSA_HDOUTN3 PCSA_REFCLKP PCSA_REFCLKN PCSA_HDOUTN0 PCSA_HDOUTP0 PCSA_HDINN0 PCSA_HDINP0 U1E 3 C SDI_IN_AC_P SDI_IN_AC_N SDI_CLK_P SDI_CLK_N W5 W6 W8 W9 U10 T10 W11 W12 W14 W15 2 C B A 1 Lattice USB3 Video Bridge Development Kit Figure 13. Sheet 3 of 17 23 D C B A Route DBG_UART lines to apad, for alternative debug OSC_100_CLK ADV_OUT_D17 ADV_OUT_D21 ADV_OUT_D19 CY_SCL CY_SDA DBG_UART_RX DBG_UART_TX ADV_T_RSTn ADV_OUT_D20 VCC_3V3 1 GND 2 Revision:0.9 Bank 7 3 Sheet 4 of 17 Date: 3.6.2014. Time: 16:38:46 File: H:\work\Lattice_prj0_revB\ecp3_bank6_bank7.SchDoc Number: 4 Lattice_prj0 Siz e: A4 Title C28 100nF LFE3-17EA-328 GND 1uF 3 PL6A/T PL6B/C PL9A/LDQ14/T PL11A/LDQ14/T(LVDS)* PL9B/LDQ14/C PL11B/LDQ14/C(LVDS)* PL12A/LDQ14/T(LVDS)* PL14A/LDQS14_P/T PL12B/LDQ14/C(LVDS)* PL14B/LDQS14_N/C PL15A/LDQ14/T PL17A/LDQ14/VREF1_7/T(LVDS)* PL15B/LDQ14/C PL17B/LDQ14/VREF2_7/C(LVDS)* PL18A/LDQ23/T PL20A/LDQ23/LUM0_GDLLT_IN_A/T(LVDS)* PL18B/LDQ23/C PL20B/LDQ23/LUM0_GDLLT_IN_B/C(LVDS)* PL21A/LDQ23/LUM0_GDLLT_FB_A/T(LVDS)* PL23A/LDQS23_P/T PL21B/LDQ23/LUM0_GDLLT_FB_B/C(LVDS)* PL23B/LDQS23_N/C PL24A/LDQ23/T PL26A/LDQ23/PCLKT7_0/T(LVDS)* PL24B/LDQ23/C PL26B/LDQ23/PCLKC7_0/C(LVDS)* PL26E_A/LUM0_GPLLT_FB_A/T PL26E_C/LUM0_GPLLT_IN_A/T PL26E_B/LUM0_GPLLT_FB_B/C PL26E_D/LUM0_GPLLT_IN_B/C U1G C26 1uF C27 10nF K6 L7 N6 C2 D1 E1 D3 D2 E3 E2 F1 F3 G1 G2 H1 G3 H2 H3 J3 J2 J1 K2 L3 L2 L1 M2 M3 M1 N3 N1 N2 P1 P3 C25 J3 1 2 3 VCCIO6 VCCIO6 VCCIO6 ADV_I2S_MCLK ADV_I2S_SCLK ADV_I2S_AP ADV_I2S_LRCLK ADV_OUT_VS ADV_OUT_HS ADV_OUT_DE ADV_OUT_D1 ADV_OUT_D0 ADV_OUT_D2 ADV_OUT_D6 ADV_OUT_D3 ADV_OUT_D8 ADV_OUT_D12 ADV_OUT_D5 ADV_OUT_D11 ADV_OUT_D9 ADV_OUT_D4 ADV_OUT_D10 ADV_OUT_D22 ADV_OUT_D13 ADV_OUT_D7 ADV_OUT_D16 ADV_OUT_CLK ADV_OUT_D23 ADV_OUT_D15 ADV_OUT_D18 ADV_OUT_D14 VCC_3V3 GND Bank 6 DBG_UART_RX DBG_UART_TX I2C address is 0x10 LFE3-17EA-328 PL29A/LDQ32/PCLKT6_0/T(LVDS)* PL29B/LDQ32/PCLKC6_0/C(LVDS)* PL32A/LDQS32_P/T PL32B/LDQS32_N/C PL35A/LDQ32/VREF1_6/T(LVDS)* PL33B/LDQ32/C PL35B/LDQ32/VREF2_6/C(LVDS)* PL47A/LDQ50/T(LVDS)* PL47B/LDQ50/C(LVDS)* PL53A/LDQ50/T(LVDS)* PL53B/LDQ50/C(LVDS)* U1F 2 VCC_3V3 R2 R3 T3 T2 R1 U2 T1 U1 V2 V1 W2 1 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * VCCIO7 VCCIO7 VCCIO7 E6 G7 J6 4 VCC_3V3 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 14. Sheet 4 of 17 24 D C B A FPGA_TCK FPGA_CFG2 FPGA_CFG1 GND 1uF C30 VCC_2V5 R29 10k 1 C31 100nF R30 10k CY_DQ9 CY_DQ11 FPGA_SPI_S_CS_N CY_DQ7 SPI_S_HOLD_N CY_DQ0 CY_DQ14 CY_DQ3 CY_DQ8 CY_DQ12 CY_DQ10 SPI_S_MISO CY_DQ6 SPI_S_MOSI GND 1 R31 10k L17 J18 J19 J17 H17 H18 G17 H19 G18 G19 F17 F19 E18 D17 E17 D18 LFE3-17EA-328 2 SPI_S_HOLD_N FPGA_SPI_S_CS_N FPGA_CFG0 FPGA_PRG_N FPGA_INIT_N FPGA_DONE FPGA_TMS FPGA_TDI FPGA_TDO R20 10k VCC_2V5 2 FPGA_TMS FPGA_TDO FPGA_TCK FPGA_TDI Bank 8 PR17B/BUSY_SISPI/C PR15B/D6_SPID1/C PR17A/D7_SPID0/T PR15A/D5/T PR14B/D4_SO/C PR12B/D2/C PR14A/D3_SI/T PR12A/D1/T PR11B/D0_SPIFASTN/C PR9B/MCLK/C PR11A/WRITEN/T PR9A/DOUT_CSON_CSSPI1N/T PR8B/CSN/SN/CONT1N/C PR6B/DI_CSSPI0N_CSSPIN/C PR8A/CS1N_HOLDN_CONT2N/T PR6A/T U1H R21 10k A2 B1 B2 C1 VCCJ R22 10k R23 10k R24 10k LFE3-17EA-328 JTAG TMS TDO TCK TDI U1I VCCIO8 VCCIO8 R26 10k VCC_2V5 F14 G13 E19 D19 C18 C19 B18 B19 A18 A17 B17 A16 B16 A15 B15 B14 C14 D4 R25 10k DONE CCLK INITN PROGRAMN CFG0 CFG1 CFG2 PT55B/C PT53B/C PT55A/T PT53A/T PT52B/C PT50B/C PT52A/T PT50A/T R27 10k R28 10k VCC_2V5 ADV_2V5_RSTn CY_DQ4 CY_PKTEND CY_SLRD FPGA_DONE SPI_S_CLK FPGA_INIT_N FPGA_PRG_N FPGA_CFG0 FPGA_CFG1 FPGA_CFG2 CONN_TCK CONN_DONE CONN_INIT_N CONN_TMS CONN_TDO CONN_TDI CONN_PRG_N Revision:0.9 J4 1 2 3 4 5 6 7 8 9 10 3 Date: 3.6.2014. Time: 16:38:46 Sheet 5 of 17 File: H:\work\Lattice_prj0_revB\ecp3_bank8.SchDoc Number: 5 Lattice_prj0 Siz e: A4 Title GND 100nF C29 VCC_2V5 3 10R 10R 10R 10R 10R 10R 10R 10R 10R 10R Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * CY_DQ0 CY_DQ1 CY_DQ2 CY_DQ3 CY_DQ4 CY_DQ5 CY_DQ6 CY_DQ7 CY_DQ8 CY_DQ9 CY_DQ10 CY_DQ11 CY_DQ12 CY_DQ13 CY_DQ14 CY_DQ15 CY_DQ16 CY_DQ17 CY_DQ18 CY_DQ19 CY_DQ20 CY_DQ21 CY_DQ22 CY_DQ23 CY_DQ24 CY_DQ25 CY_DQ26 CY_DQ27 CY_DQ28 CY_DQ29 CY_DQ30 CY_DQ31 R19 R18 CY_INIT_N CY_DONE R17 R16 R15 R14 CY_PRG_N CONN_TDO CONN_INIT_N CONN_DONE R13 R12 CONN_TMS CONN_TCK R11 R10 CONN_PRG_N CONN_TDI 4 4 CY_DQ[0..31] FPGA_DONE FPGA_INIT_N FPGA_PRG_N FPGA_TDO FPGA_INIT_N FPGA_DONE FPGA_TCK FPGA_TMS FPGA_PRG_N FPGA_TDI D C B A Lattice USB3 Video Bridge Development Kit Figure 15. Sheet 5 of 17 25 D C B A 1 1 GND A1 A10 A19 C16 C17 C3 C4 D16 E10 E12 E16 E4 F11 F13 F16 F18 F2 F4 F6 F9 G11 G12 G16 G4 G8 G9 H10 H12 H13 H16 H4 GND #0 LFE3-17EA-328 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U1J GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 H6 H8 J11 J16 J4 J7 J9 K1 K10 K12 K13 K16 K19 K4 K8 L11 L12 L13 L16 L4 L8 L9 M10 M11 M12 M16 M4 M8 M9 N12 N16 N4 2 GND GND N7 N8 P12 P13 P16 P18 P2 P4 P7 P8 R10 R11 R12 R13 R14 R16 R4 R6 R7 R8 R9 T11 T12 T13 T14 T15 T16 T4 T5 T6 T7 T8 T9 U11 U12 U13 U14 U15 U16 U17 U3 U4 U5 U6 U7 U8 U9 V10 V11 V16 V17 V3 V4 V5 W1 W10 W13 W16 W17 W19 W3 W4 W7 GND Revision:0.9 3 Time: 16:38:47 Date: 3.6.2014. Sheet 6 of 17 File: H:\work\Lattice_prj0_revB\ecp3_gnd.SchDoc Number: 6 Lattice_prj0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Siz e: A4 Title GND #1 LFE3-17EA-328 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U1K 3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 16. Sheet 6 of 17 26 D C B A VCC_PLL K3 K17 E14 E8 F7 G10 G14 G6 H11 H9 J10 J12 J8 K11 K9 L10 M6 N14 VCC_1V2_CORE 1 LFE3-17EA-328 Vxx LUM0_VCCPLL RUM0_VCCPLL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U1L 1 VTT2 VTT3 VTT3 VTT6 VTT6 VTT6 VTT7 VCCA VCCA VCCA VCCA VCCA VCCA VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC_3V3 H14 L14 M13 L6 M7 P6 H7 VCC_1V2_SER N10 N11 N9 P10 P11 P9 C15 C5 F10 J14 K7 GND GND FB3 2 GND C58 1uF C52 100nF C43 100nF BLM21AG601SN1D VCC_3V3 C51 1uF VCC_3V3 C42 1uF VCC_1V2_CORE 2 C59 100nF C53 100nF C44 100nF C60 100nF C54 100nF C45 100nF C56 10nF C47 10nF C49 1nF C35 100nF C50 1nF C38 100nF 3 Sheet 7 of 17 Time: 16:38:47 Date: 3.6.2014. File: H:\work\Lattice_prj0_revB\ecp3_pwr.SchDoc Revision:0.9 C37 100nF GND C33 1nF VCC_1V2_SER C36 100nF Number: 7 Lattice_prj0 Siz e: A4 Title C48 10nF C34 1uF C57 10nF GND C62 10nF VCC_PLL C61 100nF C55 100nF C46 10nF GND VCC_1V2_SER C32 10uF VCC_1V2_SER 3 C39 10nF 4 C41 10nF Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * C40 10nF 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 17. Sheet 7 of 17 27 D C B A J5 R32 1M GND 1k R36 HDMI_IN_HPD R37 47k C63 100nF HDMI_IN_HPD R34 2k R35 2k 1 GND 2 OUT1 OUT2 GND OUT3 OUT4 IN1 IN2 GND IN3 IN4 D2 OUT1 OUT2 GND OUT3 OUT4 RCla mp0524 IN1 IN2 GND IN3 IN4 D1 HDMI_IN_5V VCC_3V3 R33 HDMI_IN_DDC_DAT HDMI_IN_HPD OUT1 OUT2 GND OUT3 OUT4 27k CEC_D RCla mp0524 IN1 IN2 GND IN3 IN4 D3 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 RCla mp0524 HDMI_IN_CEC HDMI_IN_DDC_CLK IN_TMDS_CLK_P IN_TMDS_CLK_N IN_TMDS_D0_P IN_TMDS_D0_N IN_TMDS_D1_P IN_TMDS_D1_N IN_TMDS_D2_P IN_TMDS_D2_N HDMI_IN_DDC_CLK HDMI_IN_DDC_DAT HDMI_IN_5V GND GND 2 HDMI_IN_CEC IN_TMDS_CLK_N IN_TMDS_CLK_P IN_TMDS_D0_N IN_TMDS_D0_P IN_TMDS_D1_N IN_TMDS_D1_P IN_TMDS_D2_N IN_TMDS_D2_P GND EGND 13 14 15 16 17 18 19 20 10 11 12 7 8 9 4 5 6 1 2 3 HDMI_IN_DDC_CLK HDMI_IN_DDC_DAT CEC NC DDC_CLK DDC_DAT GND +5V HOT PLUG SHELL TMDS CLK+ TMDS CLK GND TMDS CLK- TMDS DAT0+ TMDS DAT0 GND TMDS DAT0- TMDS DAT1+ TMDS DAT1 GND TMDS DAT1- TMDS DAT2+ TMDS DAT2 GND TMDS DAT2- 1 GND GND GND Revision:0.9 3 Time: 16:38:47 Date: 3.6.2014. Sheet 8 of 17 File: H:\work\Lattice_prj0_revB\hdmi_conn_esd.SchDoc Number: 8 Lattice_prj0 Siz e: A4 Title HDMI_IN_CEC HDMI_IN_DDC_DAT HDMI_IN_HPD HDMI_IN_CEC HDMI_IN_DDC_CLK IN_TMDS_CLK_P IN_TMDS_CLK_N IN_TMDS_D0_P IN_TMDS_D0_N IN_TMDS_D1_P IN_TMDS_D1_N IN_TMDS_D2_P IN_TMDS_D2_N PMEG4005 D4 10 9 8 7 6 10 9 8 7 6 10 9 8 7 6 3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 18. Sheet 8 of 17 28 D C B A J6 1 1 BNC conn GND 2 1 i Net Class VCC_SDI 5.6nH 75R L1 1% R38 2 2 10k R88 GND R40 SDI_SPI_EN 37R4 1% R39 75R 1% 1uF C67 1uF C64 VCC_2V5 FB4 EQ_SPI_S_CS_N SPI_S_CLK SPI_S_MOSI SPI_S_MISO SDI_SPI_EN SDI_IN_EQ_P SDI_IN_EQ_N LMH0394 SS MUTE_SCK CD_MOSI ASLEEP_MISO SPI_EN MUTEREF BYPASS_CD SDI SDI U2 VCC VCC AEC+ AEC- SDO SDO Number: 9 C68 1uF VCC_SDI Revision:0.9 C72 10nF VCC_SDI GND C71 100nF 1 17 13 16 5 6 11 SDI_IN_P 10 SDI_IN_N 3 Time: 16:38:47 Date: 3.6.2014. Sheet 9 of 17 File: H:\work\Lattice_prj0_revB\SDI_c onn_esd.SchDoc C70 100nF VEE_GND VEE_DAP Lattice_prj0 Siz e: A4 Title GND C69 10uF BLM21AG601SN1D Drive this with 2.5V!!! 9 14 15 12 4 8 7 2 3 3 4 SDI_IN_AC_N SDI_IN_AC_P Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * 4.7uF 4.7uF C66 C65 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 19. Sheet 9 of 17 29 D C B A GND C88 10uF 1 C89 100nF C90 100nF C91 10nF C92 10nF GND BLM21AG601SN1D FB7 BLM21AG601SN1D VCC_1V8 C79 10nF VCC_1V8 C78 100nF ADV7611 C87 10uF C75 10uF RXA_5V DDCA_SDA DDCA_SCL CEC XTALN XTALP RESEST GND PVDD DVDD DVDD DVDD DVDD DVDDIO DVDDIO DVDDIO CVDD CVDD HPA_A/INT2 RXA_CRXA_C+ RXA_0RXA_0+ RXA_1RXA_1+ RXA_2RXA_2+ TVDD TVDD TVDD U3 FB5 64 63 62 61 VCC_3V3 HDMI_IN_DDC_DAT HDMI_IN_DDC_CLK HDMI_IN_CEC 59 58 56 65 57 24 40 52 60 23 34 44 2 14 1 3 4 6 7 9 10 12 13 5 8 11 GND C77 100nF 0R R41 XTALN_DVI0 XTALP_DVI0 ADV_T_RSTn GND VCC_1V8_PLL_D0 VCC_1V8 VCC_3V3 VCC_1V8_A_D0 VCC_3V3_TERM_D0 HDMI_IN_HPD IN_TMDS_CLK_N IN_TMDS_CLK_P IN_TMDS_D0_N IN_TMDS_D0_P IN_TMDS_D1_N IN_TMDS_D1_P IN_TMDS_D2_N IN_TMDS_D2_P GND C76 10uF VCC_3V3 VCC_5V 1 2 2 C81 100nF C93 100nF C94 100nF VCC_1V8_A_D0 C80 100nF 54 53 55 51 49 50 48 43 42 41 39 38 37 36 35 33 32 31 30 29 28 27 26 22 21 20 19 18 17 16 15 45 46 47 25 C82 10nF VCC_3V3_TERM_D0 SDA SCL INT1 MCLK/INT2 SCLK/INT2 LRCLK AP P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 DE HS VS/FIELD/ALSB LCC FB6 GND BLM21AG601SN1D VCC_1V8 CY_SDA CY_SCL ADV_I2S_MCLK ADV_I2S_SCLK ADV_I2S_LRCLK ADV_I2S_AP HDMI_A_D0 HDMI_A_D1 HDMI_A_D2 HDMI_A_D3 HDMI_A_D4 HDMI_A_D5 HDMI_A_D6 HDMI_A_D7 HDMI_A_D8 HDMI_A_D9 HDMI_A_D10 HDMI_A_D11 HDMI_A_D12 HDMI_A_D13 HDMI_A_D14 HDMI_A_D15 HDMI_A_D16 HDMI_A_D17 HDMI_A_D18 HDMI_A_D19 HDMI_A_D20 HDMI_A_D21 HDMI_A_D22 HDMI_A_D23 HDMI_A_DE HDMI_A_HS HDMI_A_VS HDMI_A_CLK 10uF C85 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 2 4 6 8 RA1 2 4 6 8RA2 2 4 6 8RA3 2 4 6 8RA4 2 4 6 8RA5 2 4 6 8RA6 2 4 6 8 RA7 2 GND 3 R42 10k ADV_OUT_VS 4 4 GND Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * C84 33pF XTALN_DVI0 i Net Class 28.63636 MHz Y1 Revision:0.9 1 Date: 3.6.2014. Time: 16:38:48 Sheet 10 of 17 File: H:\work\Lattice_prj0_revB\adv7611.SchDoc C83 33pF XTALP_DVI0 GND C74 10uF ADV_OUT_D1 ADV_OUT_D2 ADV_OUT_D3 ADV_OUT_D4 ADV_OUT_D5 ADV_OUT_D6 ADV_OUT_D7 ADV_OUT_D8 ADV_OUT_D9 ADV_OUT_D1 T 0 ADV_OUT_D10 ADV_OUT_D1 T 1 ADV_OUT_D11 ADV_OUT_D12 ADV_OUT_D1 T 2 ADV_OUT_D13 ADV_OUT_D1 T 3 ADV_OUT_D14 ADV_OUT_D1 T 4 ADV_OUT_D15 ADV_OUT_D1 T 5 ADV_OUT_CLK ADV_OUT_D16 ADV_OUT_D1 T 6 ADV_OUT_D17 ADV_OUT_D1 T 7 ADV_OUT_D18 ADV_OUT_D1 T 8 ADV_OUT_D19 ADV_OUT_D1 T 9 ADV_OUT_D20 ADV_OUT_D2 T 0 ADV_OUT_D21 ADV_OUT_D2 T 1 ADV_OUT_D22 ADV_OUT_D2 T 2 ADV_OUT_D23 ADV_OUT_D2 T 3 ADV_OUT_VS ADV_OUT_HS ADV_OUT_DE ADV_OUT_D0 C73 10uF VCC_1V8 Number: 10 Lattice_prj0 Siz e: A4 Title C86 100nF VCC_1V8_PLL_D0 HDMI_A_D1 HDMI_A_D2 HDMI_A_D3 HDMI_A_D4 HDMI_A_D5 HDMI_A_D6 HDMI_A_D7 HDMI_A_D8 HDMI_A_D9 HDMI_A_D10 HDMI_A_D11 HDMI_A_D12 HDMI_A_D13 HDMI_A_D14 HDMI_A_D15 HDMI_A_CLK HDMI_A_D16 HDMI_A_D17 HDMI_A_D18 HDMI_A_D19 HDMI_A_D20 HDMI_A_D21 HDMI_A_D22 HDMI_A_D23 HDMI_A_VS HDMI_A_HS HDMI_A_DE HDMI_A_D0 3 D C B A Lattice USB3 Video Bridge Development Kit Figure 20. Sheet 10 of 17 30 D C B A 1 1 GND C101 100nF VCC_3V3 I2C address is 0x70 GND GND 2 1 27 MHz GND EN Y2 CY_SCL CY_SDA OUT VCC GND 23 25 12 19 8 3 4 VCC_3V3 GND SI5338 OSC_27_CLK 2 VDDO3 VDDO2 VDDO1 VDDO0 VDD VDD CLK3B CLK3A CLK2B CLK2A CLK1B CLK1A CLK0B CLK0A C96 100nF GND EPAD/GND SCL SDA INTR IN1/CLK_P IN2/CLK_N IN3/CLK_IN IN4/I2C_LSB IN5/FDBK_P IN6/FDBK_N U4 C95 100nF VCC_3V3 OSC_27_CLK 1 2 3 4 5 6 2 C97 100nF 11 15 16 20 7 24 C98 100nF VCC_3V3 VCC_3V3 9 10 13 14 OSC_100_CLK 17 18 21 SDI_CLK_N 22 SDI_CLK_P C99 100nF Revision:0.9 3 Time: 16:38:48 Date: 3.6.2014. Sheet 11 of 17 File: H:\work\Lattice_prj0_revB\clock.Sc hDoc Number: 11 Lattice_prj0 100R 1% Siz e: A4 Title C100 10nF R43 3 FD4 M4 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * FD6 FD5 FD3 M3 M5 FD2 FD1 M2 M1 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 21. Sheet 11 of 17 31 D C B A 1 GND R56 10k C103 100nF CY_RST_N CYUSB3014_BGA121 I2C_SCL I2C_SDA GPIO_I2SCLK GPIO_I2SSD GPIO_I2SWS SPISCK_UARTRTS_GPIO SPISSN_UARTCTS_GPIO SPIMISO_UARTTX_GPIO SPIMOSI_UARTRX_GPIO GPIO_I2SMCLK GPIO CTL0_SLCS CTL1_SLWR CTL2_SLOE CTL3_SLRD CTL4_FLAGA CTL5_FLAGB CTL6_EPSWITCH CTL7_PKTEND CTL8_A4 CTL9_A3 CTL10_A2 CTL11_A1 CTL12_A0 INT_CTL15 PCLK_CLK RESET U5A VCC_2V5 D9 D10 D1 D2 D3 D4 C1 C2 D5 C4 F2 FPGA_SPI_S_CS_N SPI_S_CLK SPI_S_MOSI SPI_M_CLK SPI_M_CS_N SPI_M_MISO SPI_M_MOSI SPI_S_MISO EQ_SPI_S_CS_N CY_SCL CY_SDA K8 K7 J7 H7 G7 G6 K6 H8 G5 H6 K5 J5 H5 L8 J6 C5 CY_SLCS_N CY_SLWR CY_SLOE CY_SLRD CY_FLAGA CY_FLAGB ADV_2V5_RSTn CY_PKTEND CY_INIT_N CY_DONE CY_PRG_N CY_ADR1 CY_ADR0 CY_IFCLK CY_RST_N 1 CY_SCL CY_SDA VCC_3V3 4k7 4k7 R57 R58 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 F10 F9 F7 G10 G9 F8 H10 H9 J10 J9 K11 L10 K10 K9 J8 G8 K2 J4 K1 J2 J3 J1 H2 H3 F4 G2 G3 F3 F5 E1 E5 E4 2 2 CY_DQ0 CY_DQ1 CY_DQ2 CY_DQ3 CY_DQ4 CY_DQ5 CY_DQ6 CY_DQ7 CY_DQ8 CY_DQ9 CY_DQ10 CY_DQ11 CY_DQ12 CY_DQ13 CY_DQ14 CY_DQ15 CY_DQ16 CY_DQ17 CY_DQ18 CY_DQ19 CY_DQ20 CY_DQ21 CY_DQ22 CY_DQ23 CY_DQ24 CY_DQ25 CY_DQ26 CY_DQ27 CY_DQ28 CY_DQ29 CY_DQ30 CY_DQ31 CY_DQ[0..31] 1 2 3 4 9 GND SPI_M_CS_N SPI_M_MISO SPI_M_VPP CY_IFCLK J7 M25P16 R55 10k Revision:0.9 R53 10k R48 CONN2_TDO CY_TDI CY_TMS CY_TRST_N CY_TDO R47 CONN2_RST_N 3 10R 10R 10R 10R 10R 4 CY_TDO CY_TRST_N CY_TCK CY_TMS CY_TDI 4 R51 10k R52 10k VCC_3V3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * R50 10k R46 R49 10k R45 CONN2_TCK R44 CONN2_TMS CONN2_TDI Time: 16:38:48 Date: 3.6.2014. Sheet 12 of 17 File: H:\work\Lattice_prj0_revB\usb_fx3_part1.SchDoc Number: 12 Lattice_prj0 Siz e: A4 Title R54 10k VCC_2V5 GND C102 100nF VCC_3V3 CONN2_RST_N 8 7 SPI_M_HOLD_N 6 SPI_M_CLK 5 SPI_M_MOSI VCC_2V5 SPI_M_CS_N SPI_M_VPP SPI_M_HOLD_N S VCC Q HOLD W/VPP C VSS D PAD U12 TP1 CONN2_TDO CONN2_TDI CONN2_TCK CONN2_TMS 1 2 3 4 5 6 7 8 9 10 3 D C B A Lattice USB3 Video Bridge Development Kit Figure 22. Sheet 12 of 17 32 D C B A GND 100nF 10nF 100nF GND 100nF 10nF C129 1 GND 22uF C130 VCC_1V2_CORE VCC_3V3 C128 C120 100nF C131 100nF C132 100nF 10nF C119 Digital power bypass 10nF C118 CYUSB3014_BGA121 NC R_usb2 R_usb3 PMODE0 PMODE1 PMODE2 O60_CHGDET TDI TDO TRST TMS TCK FSLC0 FSLC1 FSLC2 CLKIN CLKIN_32 XTALIN XTALOUT OTG_ID SSRXM SSRXP SSTXM SSTXP DP DM U5B CVDDQ power bypass GND C117 C116 A11 C8 B3 G4 H4 L4 D11 E7 C10 B11 E8 F6 C115 VCC_3V3 R60 200R 1% CY_PMODE0 CY_PMODE1 CY_PMODE2 CY_TDI CY_TDO CY_TRST_N CY_TMS CY_TCK B2 B4 E6 D7 OSC_32K_CLK D6 C6 C7 XTALP_CY XTALN_CY IO power bypass R59 6k04 1% GND C9 A3 A4 A6 A5 A9 A10 CY_OTG_ID CN_SSRX_N CN_SSRX_P CY_SSTX_N CY_SSTX_P CY_D_P CY_D_N 1 C122 100nF C133 10nF C134 100nF 10nF C121 C124 10nF C135 10nF VCC_3V3 I2C and JTAG have to be3V3! VCC_2V5 2 10nF C137 3 2 1 NCP361 EN GND IN U6 GND FLAG OUT BLM21AG601SN1D FB11 VCC_1V2_CORE GND C104 C109 22uF C113 22uF 4 100nF C111 100nF 100k R65 10k 10k C108 2.2uF OUT1 OUT2 GND OUT3 OUT4 GND 3 Sheet 13 of 17 Date: 3.6.2014. Time: 16:38:48 File: H:\work\Lattice_prj0_revB\usb_fx3_part2.SchDoc Revision:0.9 GND C127 4.7uF 1 OUT VCC 3 XTALN_CY GND 4 19.2 MHz Y4 CONN_USB30_B_mic ro SSTXSSTX+ GND2 SSRXSSRX+ +5V DD+ OTG GND SHLD J8 C126 12pF 3 OSC_32K_CLK 4 VCC_3V3 FB10 C107 BLM21AG601SN1D 100nF 32.768 kHz GND EN Y3 GND Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * VBUS power bypass C125 12pF XTALP_CY GND 2 GND 1 2 3 4 5 0 6 7 8 9 10 USB_SHLD CN_SSRX_P CN_SSRX_N CN_SSTX_N CN_SSTX_P CY_D_N CY_D_P CY_OTG_ID 1 4 VDD_5V_USB USB_SHLD 100nF C112 100nF C106 GND DO NOT MOUNT THIS RESISTORS! VCC_2V5 C110 100nF GND 10 9 8 7 6 VDD_5V_USB SP3010-04UTG IN1 IN2 GND IN3 IN4 D5 VDD_5V_VBUS R63 10k R64 10k R62 R61 Number: 13 Lattice_prj0 GND 1 2 3 4 5 VCC_1V2_ANALOG VDD_5V_VBUS CY_PMODE2 CY_PMODE1 CY_PMODE0 GND BLM21AG601SN1D Siz e: A4 Title C114 100nF CN_SSTX_N CN_SSTX_P Route SS lines with 90 ohm diff impe dance. CN_SSRX_P CN_SSRX_N FB8 VCC_1V2_CORE C105 100nF VCC_1V2_SSRX 5 3 Place close to theFX3, with cutout unde r C. VCC_1V2_SSTX CY_SSTX_N CY_SSTX_P BLM21AG601SN1D FB9 VCC_1V2_CORE GND VCC_1V2_CORE VCC_3V3 VDD_5V_VBUS VCC_1V2_ANALOG VCC_3V3 VCC_1V2_SSTX VCC_1V2_SSRX VDD_5V_USB GND D8 E2 G1 G11 L1 L6 L11 B8 B9 K4 L3 K3 L2 A8 B7 A1 H11 L9 F1 E3 B1 C11 B10 C3 E9 F11 H1 L7 J11 L5 E10 E11 A7 B6 B5 A2 C136 100nF 10nF C123 VCC_2V5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVSS U3VSSQ VIO1 VIO1 VIO2 VIO3 VIO4 VIO5 VDD VDD VDD VDD VDD VDD VDD VDD VBATT VBUS AVDD CVDDQ U3TXVDDQ U3RXVDDQ 2 D C B A Lattice USB3 Video Bridge Development Kit Figure 23. Sheet 13 of 17 33 D C B A GND TP2 1 3 2 C140 10uF VCC_5V C139 10uF VCC_5V J9 1 18k2 R68 GND GND C144 100nF R67 100k GND C148 10pF C149 330pF R69 16k2 GND GND GND R71 68k1 C142 4.7uF VDD_5V_USB C141 4.7uF VCC_5V VCC_3V3 22uF +C138 SS8P3L VCC_5V 100k R89 TP4 6 7 10 9 5 2 PWR_GOOD PWR_GOOD J10 1 2 3 LT3685 SYNC PG RT VC RUN/SS 4 V IN D6 2 PA D GND 11 1 BD 1 FB SW BOOST U7 8 3 2 FB12 3.3uH L2 Number: 14 GND Revision:0.9 GND C145 100uF BLUE D7 3 Sheet 14 of 17 Date: 3.6.2014. Time: 16:38:49 File: H:\work\Lattice_prj0_revB\power_part1.SchDoc Siz e: A4 Title 52k3 R70 0.47uF D8 EGND 470R R66 Lattice_prj0 BLM21PG300SN1D C143 R72 100k GND GND VCC_5V 3 C146 100uF Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia C147 10uF TP3 VCC_1V2_CORE GND 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 24. Sheet 14 of 17 D C B A GND C159 10uF VCC_5V GND C154 10uF VCC_5V GND C150 10uF 1 3 2 LTC3621 RUN VIN LTC3621 RUN VIN U8 U9 3 2 GND GND FB SW MODE INTVCC PGOOD FB SW MODE INTVCC PGOOD GND SGND 9 8 GND SGND 34 9 8 VCC_5V 1 7 6 4 5 1 7 6 4 5 1 GND PWR_GOOD R78 0R 0R R79 L4 GND PWR_GOOD R74 0R 0R R75 L3 GND C160 10uF GND 4.7uH GND 2 C155 10uF GND 4.7uH 2 R80 10k R77 31k6 TP6 R76 22k1 R73 100k TP5 C156 22pF C151 22pF GND C157 47uF GND C153 47uF C158 47uF VCC_2V5 C152 47uF VCC_3V3 Revision:0.9 3 Sheet 15 of 17 Date: 3.6.2014. Time: 16:38:49 File: H:\work\Lattice_prj0_revB\power_part2.SchDoc Number: 15 Lattice_prj0 Siz e: A4 Title 3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 25. Sheet 15 of 17 D C B GND 1 GND C173 22uF VCC_2V5 C166 22uF VCC_2V5 VCC_2V5 22uF C162 VCC_2V5 GND 10 12 11 15 14 13 C165 1nF R81 10k IN IN EN GND LP38511MR-ADJ SHDN2 IN2 IN2 SHDN1 IN1 IN1 8 7 6 5 U10 GND PA D BYP2 ADJ 2 OUT2 OUT2 BYP1 ADJ 1 OUT1 OUT1 GND 9 A 2 NC 5 17 35 GND GND 1 8 9 6 7 1 16 3 4 1 2 3 4 2 U11 LT3029EMSE OUT OUT ADJ N/C 2 C170 10nF C167 10nF GND R83 1k13 R82 2.94k GND 0R Do not mount! R87 C164 10uF TP7 GND GND GND C172 10uF Number: 16 Revision:0.9 3 Time: 16:38:49 Date: 3.6.2014. Sheet 16 of 17 File: H:\work\Lattice_prj0_revB\power_part3.SchDoc TP10 VCC_PCS_IO TP9 C169 10uF Lattice_prj0 C171 10uF C168 10uF TP8 VCC_1V2_SER Siz e: A4 Title GND C163 10uF VCC_1V8 GND 0R Do not mount! R85 R86 0R R84 0R 1500pF C161 VCC_1V8 3 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia 4 4 D C B A Lattice USB3 Video Bridge Development Kit Figure 26. Sheet 16 of 17 36 2 clock clock.Sc hDoc ecp3_bank6_bank7 ecp3_bank6_bank7.SchDoc Title ecp3_bank8 ecp3_bank8.SchDoc ecp3_gnd ecp3_gnd.SchDoc Lattice_prj0 3 Revision:0.9 Mikroprojekt d.o.o. Slavonska avenija 50 Zagreb Cr oatia * ecp3_pwr ecp3_pwr.SchDoc 4 4 B A Number: 17 3 Time: 16:38:49 Date: 3.6.2014. Sheet 17 of 17 File: H:\work\Lattice_prj0_revB\main.SchDoc Siz e: A4 D 1 2 D power_part3 power_part3.SchDoc adv7611 adv7611.SchDoc ecp3_pcs ecp3_pcs.SchDoc C power_part2 power_part2.SchDoc usb_fx3_part2 usb_fx3_part2.SchDoc usb_fx3_part1 usb_fx3_part1.SchDoc power_part1 power_part1.SchDoc SDI_c onn_esd SDI_c onn_esd.SchDoc hdmi_conn_esd hdmi_conn_esd.SchDoc ecp3_bank2_bank3 ecp3_bank2_bank3.SchDoc C B A 1 ecp3_bank0_bank1 ecp3_bank0_bank1.SchDoc Lattice USB3 Video Bridge Development Kit Figure 27. Sheet 17 of 17 Lattice USB3 Video Bridge Development Kit Appendix B. Bill of Materials Table 10. Bill of Materials Quantity Part Number Manufacturer Description U3 1 DV7611BSWZ-P Analog Low Power 165 MHz HDMI Receiver J6 1 0731713356 Molex BNC connector C1, C2, C7, C10, C13, C15, C19, C21, C25, C26, C30, C34, C42, C51, C58 15 LMK107B7105KA-T Taiyo Yuden Capacitor 1uF C108 1 LMK212BJ225KD-T Taiyo Yuden Capacitor 2.2uF C125, C126 2 CC0402JRNPO9BN120 Yageo Capacitor 12pF C127, C141, C142 3 LMK212BJ475KD-T Taiyo Yuden Capacitor 4.7uF C139, C140, C150, C154, C155, C159, C160 7 TMK316B7106KL-TD Taiyo Yuden Capacitor 10uF C143 1 UMK107B7474KA-TR Taiyo Yuden Capacitor 0.47uF C145, C146 2 JMK325BJ107MM-T Taiyo Yuden Capacitor 100uF C148 1 CC0402JRNPO9BN100 Yageo Capacitor 10pF Reference Value C149 1 C1005X7R1H331K TDK Corporation Capacitor 330pF C151, C156 2 CC0402JRNPO9BN220 Yageo Capacitor 22pF C152, C153, C157, C158 4 LMK316BJ476ML-T Taiyo Yuden Capacitor 47uF C161 1 CC0402KRX7R9BB152 Yageo Capacitor 1500pF C167, C170 2 GRM155R71C103KA01D Murata Electronics Capacitor 10nF C17, C23, C109, C113, C130, C162, C166, C173 8 C2012X5R1A226M/1.25 TDK Corporation Capacitor 22uF C3, C6, C8, C12, C14, C16, C20, C22, C28, C29, C31, C35, C36, C37, C38, C43, C44, C45, C52, C53, C54, C55, C59, C60, C61, C63, C70, C71, C77, C78, C80, C81, C86, C89, C90, C93, C94, C95, C96, C97, C98, C99, C101, C102, C103, C104, C105, C106, C107, C110, C111, C112, C114, C115, C117, C119, C121, C123, C128, C131, C132, C133, C144 63 GRM155R71C104KA88D Murata Electronics Capacitor 100nF 37 Quantity Part Number Manufacturer Description Value C32, C69, C73, C74, C75, C76, C85, C87, C88, C147, C163, C164, C168, C169, C171, C172 16 LMK212BJ106KG-T Taiyo Yuden Capacitor 10uF C33, C49, C50, C165 4 0402YC102KAT2A AVX Corporation Capacitor 1nF C4, C5, C9, C11, C18, C24, C27, C39, C40, C41, C46, C47, C48, C56, C57, C62, C72, C79, C82, C91, C92, C100, C116, C118, C120, C122, C124, C129, C134, C135, C136, C137 32 GRM155R71C103KA01D Murata Electronics Capacitor 10nF C64, C67, C68 3 04026D105KAT2A Avex Capacitor 1uF C65, C66 2 C1005X5R0J475M050BC TDK Capacitor 4.7uF C83, C84 2 CC0402JRNPO9BN330 Yageo Capacitor 33pF C138 1 EEEFK1V220R Panasonic Electronic Components Capacitor Polarized 22uF J9 1 PJ-002A CUI Inc Barrel Connector Low Voltage Power Supply Connector Reference J3, J10 2 825433-3 TE Connectivity J2 1 67996-206HLF FCI J4 1 1-87224-0 TE Connectivity J7 1 826925-5 TE Connectivity Header 2x5 WAYs J8 1 USB3110-30-A Global Connector Technology USB 3.0, B micro U5 1 CYUSB3014-BZXC Cypress Cypress USB 3.0 Device, 121-ball BGA D8 1 DFLS240L-7 Diodes Inc Schottky Rectifier FB1, FB2, FB3, FB4, FB5, FB6, FB7, FB8, FB9, FB10, FB11 11 BLM21AG601SN1D Murata Electronics FB12 1 BLM21PG300SN1D Murata Electronics J5 1 0471511001 Molex HDMI Connector L1 1 LQP15MN5N6B02D Murata Inductor L2 1 NRS8030T3R3MJGJ Taiyo Yuden Inductor 3.3uH L3, L4 2 NRS6028T4R7MMGK Taiyo Yuden Inductor 4.7uH D7 1 KP-3216PBC Kingbright LED U1 1 LFE3-17EA-6MG328C Lattice LFE3-17EA-328 U2 1 LMH0394SQ Texas Instruments SDI equalizer 5.6nH Quantity Part Number Manufacturer Description U10 1 LP38511MR-ADJ National Semiconductor LP38511MR-ADJ 3A Fast-Transient Response Adjustable Low-Dropout Linear U11 1 LT3029EMSE#PBF Linear Technology Dual 500 mA/500 mA Low Dropout, Low Noise, Micropower Linear Regulator U7 1 LT3685EMSE#PBF Linear Technology 36V, 2A 2.4 MHz Step-Down Switching Regulator U8, U9 2 LTC3621EMS8E-2#PBF Linear Technology 17V, 1A Synchronous Step-Down Regulator U12 1 M25PX16-VMP6TG Micron Technology Inc Numonyx SPI FLASH, 16 MBit J1 1 52559-3652 Molex FFC/FPC Connector, Vertical, SMT, ZIF, 36 Circuits U6 1 NCP361SNT1G ON Semi USB Positive Overvoltage Protection Controller with Internal PMOS FET and Overcurrent Protection Y2 1 7C-27.000BB-T TXC Corporation Oscillator Y3 1 7XZ-32.768KBE-T TXC Oscillator D4 1 PMEG4005EJ,115 NXP Semiconductors Schottky Rectifier D1, D2, D3 3 RCLAMP0524PATCT Semtech Ultra Low Capacitance TVS Arrays R1, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R42, R49, R50, R51, R52, R53, R54, R55, R56, R61, R64, R80, R81, R88 27 CRCW040210K0FKED Vishay Dale RESISTOR 10k R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R44, R45, R46, R47, R48 15 RC0402JR-0710RL Yageo RESISTOR 10R R32 1 ERJ-2GEJ105X Panasonic Electronic Components RESISTOR 1M R33 1 CRCW040227K0FKED Vishay Dale RESISTOR 27k Reference Value R34, R35 2 CRCW04022K00JNED Vishay Dale RESISTOR 2k R36 1 CRCW04021K00FKED Vishay Dale RESISTOR 1k R37 1 CRCW040247K0FKED Vishay Dale RESISTOR 47k R38, R39 2 CRCW040275R0FKED Vishay RESISTOR 75R R40 1 CRCW040237R4FKED Vishay RESISTOR 37R4 R43 1 ERJ-2RKF1000X Panasonic Electronic Components RESISTOR 100R Reference Quantity Part Number R57, R58 2 CRCW04024K70FKEAHP R59 1 CRCW04026K04FKED R6, R7, R8, R9, R41, R74, R78, R84, R86 9 CRCW04020000Z0ED R60 1 CRCW0402200RFKED R65, R72 2 ERA-2AED104X R66 1 CRCW0603470RFKEA R67, R89 2 ERJ-3GEYJ104V R68 1 ERJ-2RKF1822X R69 1 R70 Manufacturer Description Value RESISTOR 4k7 Vishay RESISTOR 6k04 Vishay Dale RESISTOR 0R Vishay RESISTOR 200R Panasonic Electronic Components RESISTOR 100k Vishay RESISTOR 470R Panasonic Electronic Components RESISTOR 100k Panasonic Electronic Components RESISTOR 18k2 ERJ-2RKF1622X Panasonic Electronic Components RESISTOR 16k2 1 ERJ-2RKF5232X Panasonic Electronic Components RESISTOR 52k3 R71 1 ERJ-2RKF6812X Panasonic Electronic Components RESISTOR 68k1 R73 1 CRCW0402100KFKED Vishay Dale RESISTOR 100k R76 1 CRCW040222K1FKED Vishay Dale RESISTOR 22k1 R77 1 CRCW040231K6FKED Vishay Dale RESISTOR 31k6 R82 1 ERJ-2RKF2941X Panasonic Electronic Components RESISTOR 2.94k R83 1 ERJ-2RKF1131X Panasonic Electronic Components RESISTOR 1k13 RA1, RA2, RA3, RA4, RA5, RA6, RA7 7 EXBN8V220JX Panasonic Electronic Components Resistor array (4 resistors) U4 1 SI5338C-A-GM Silicon Laboratories Inc SI5338A/B/C clock synthesizer D5 1 SP3010-04UTG Littelfuse Low Capacitance TVS Arrays D6 1 SS8P3L-M3/86A Vishay General Semiconductor High Current Density Schottky Rectifier Y1 1 7A-28.63636MAAJ-T TXC Corporation Y4 1 7B-19.200MAAJ-T Crystal Crystal