HRFZ44N Data Sheet June 1999 49A, 55V, 0.022 Ohm, N-Channel UltraFET Power MOSFET This N-Channel power MOSFET is manufactured using the innovative UltraFET™ process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. File Number 4752 Features • 49A, 55V • Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and Saber Thermal Impedance Models - www.semi.Intersil.com/families/models.htm • Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Formerly developmental type TA75329. D Ordering Information PART NUMBER HRFZ44N PACKAGE TO-220AB BRAND G HRFZ44N NOTE: When ordering, use the entire part number. S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation. SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HRFZ44N Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 55 55 ±20 UNITS V V V 49 160 0.227 120 0.8 -55 to 175 A A A2s W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. 2. Repetitive rating: pulse width limited by maximum junction temperature. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 55 - - V VDS = 50V, VGS = 0V - - 1 µA VDS = 45V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±20V - - ±100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS Gate to Source Leakage Current IGSS ID = 250µA, VGS = 0V (Figure 11) ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 25A, VGS = 10V (Figure 9) - 0.019 0.022 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.25 oC/W Thermal Resistance Junction to Ambient RθJA TO-220 - - 62 oC/W tON VDD = 30V, ID ≅ 25A, RL = 1.2Ω, VGS = 10V, RGS = 9.1Ω (Figures 18, 19) - - 105 ns - 12 - ns - 58 - ns td(OFF) - 33 - ns tf - 33 - ns tOFF - - 100 ns - 60 75 nC - 35 43 nC - 2.0 2.5 nC - 4 - nC - 14 - nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Gate to Source Gate Charge Qgs Reverse Transfer Capacitance Qgd 2 VDD = 30V, ID ≅ 25A, RL = 1.2Ω Ig(REF) = 1.0mA (Figures 13, 16, 17) HRFZ44N TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 1060 - pF - 405 - pF - 95 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage TEST CONDITIONS VSD TYP MAX UNITS ISD = 25A - - 1.25 V trr ISD = 25A, dISD/dt = 100A/µs - - 72 ns QRR ISD = 25A, dISD/dt = 100A/µs - - 120 nC Reverse Recovery Time Reverse Recovered Charge MIN 1.2 60 1.0 50 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 40 30 20 10 0.2 0 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 25 175 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 THERMAL IMPEDANCE ZθJC, NORMALIZED 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 -5 10 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 100 101 HRFZ44N Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 VGS = 10V 150 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 500 TJ = MAX RATED TC = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 500 100 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms BVDS MAX = 55V If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC STARTING TJ = 150oC 1 1 10 100 10 0.001 200 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.01 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 100 VGS = 20V VGS = 10V VGS = 8V VGS = 7V 80 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY VGS = 6V 60 40 VGS = 5V 20 0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS 4 -55oC 80 175oC 60 40 20 25oC 5 0 0 VDD = 15V 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS 7.5 HRFZ44N Typical Performance Curves 1.2 VGS = 10V, ID = 49A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 (Continued) 2.0 1.5 1.0 0.5 -80 -40 0 40 80 120 160 1.0 0.8 0.6 0.4 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 40 80 120 160 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1800 ID = 250µA VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 1500 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 0 TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 0.9 1200 CISS 900 600 COSS 300 CRSS 0.8 -80 -40 0 40 80 120 160 0 200 0 10 TJ , JUNCTION TEMPERATURE (oC) 20 FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS , GATE TO SOURCE VOLTAGE (V) 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 49A ID = 36.75A ID = 24.5A ID = 12.25A 2 VDD = 30V 0 5 10 15 20 25 30 35 Qg, GATE CHARGE (nC) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 5 40 50 60 FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 0 30 VDS , DRAIN TO SOURCE VOLTAGE (V) HRFZ44N Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT 6 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS HRFZ44N PSPICE Electrical Model .SUBCKT HRFZ44N 2 1 3 ; rev 6/19/97 CA 12 8 1.72e-9 CB 15 14 1.52e-9 CIN 6 8 9.61e-10 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 RLDRAIN RSLC1 51 DBREAK + RSLC2 EBREAK 11 7 17 18 58.13 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 5 51 ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.86e-9 LSOURCE 3 7 2.69e-9 + 17 EBREAK 18 50 - IT 8 17 1 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD 8 SOURCE 3 7 RSOURCE RLSOURCE S1A RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 1.52 RLDRAIN 2 5 10 RLGATE 1 9 26.9 RLSOURCE 3 7 28.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 13.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DRAIN 2 5 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 - - IT 14 + + EGS 19 VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))} .MODEL DBODYMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5) .MODEL DBREAKMOD D (RS = 2.14e-1 TRS1 = 9.62e-4 TRS2 = 1.23e-6) .MODEL DPLCAPMOD D (CJO = 13.5e-10 IS = 1e-30 N = 10 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52) .MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = 1.94e-7) .MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4) .MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5) .MODEL RVTEMPMOD RES (TC1 = -1.35e-3 TC2 = 1.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.90 VOFF= -4.90) VON = -4.90 VOFF= -7.90) VON = -0.50 VOFF= 2.50) VON = 2.50 VOFF= -0.50) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 7 HRFZ44N SABER Electrical Model REV June 1997 template hrfz44n n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 7.50e-13, cjo = 1.51e-9, tt = 4.05e-8, m = 0.5) d..model dbreakmod = () d..model dplcapmod = (cjo = 13.5e-10, is = 1e-30, n = 10, m = 0.85) m..model mmedmod = (type=_n, vto = 3.25, kp = 2.50, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.80, kp = 70, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.91, kp = 0.06, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.90, voff = -4.90) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.90, voff = -7.90) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 2.50) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.50, voff = -0.50) LDRAIN DPLCAP DRAIN 2 5 10 RLDRAIN RSLC1 51 RDBREAK RSLC2 c.ca n12 n8 = 1.72e-9 c.cb n15 n14 = 1.52e-9 c.cin n6 n8 = 9.61e-10 72 ISCL d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod GATE 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.86e-9 l.lsource n3 n7 = 2.69e-9 EVTHRES + 19 8 + LGATE i.it n8 n17 = 1 RDRAIN 6 8 ESG EVTEMP RGATE + 18 22 9 20 21 MSTRO S2A 13 8 LSOURCE 7 RBREAK 15 14 13 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/135))** 3.5)) } } VBAT 5 8 EDS - IT 14 + + spe.ebreak n11 n7 n17 n18 = 58.13 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 8 8 DBODY RLSOURCE S1A S1B CA EBREAK + 17 18 RSOURCE 12 res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.94e-7 res.rdbody n71 n5 = 5.05e-3, tc1 = 2.21e-3, tc2 = 1.02e-6 res.rdbreak n72 n5 = 2.14e-1, tc1 = 9.62e-4, tc2 = 1.23e-6 res.rdrain n50 n16 = 1e-3, tc1 = 8.04e-2, tc2 = 1.37e-4 res.rgate n9 n20 = 1.52 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26.9 res.rlsource n3 n7 = 28.6 res.rslc1 n5 n51 = 1e-6, tc1 = 4.83e-3, tc2 = 1.16e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 13.85e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.35e-3, tc2 = 1.16e-6 res.rvthres n22 n8 = 1, tc1 = -3.43e-3, tc2 = -1.63e-5 MWEAK MMED CIN 71 11 16 6 RLGATE m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u DBREAK 50 - RDBODY - + 8 22 RVTHRES SOURCE 3 HRFZ44N SPICE Thermal Model REV 23 February 1999 th JUNCTION HRFZ44N CTHERM1 th 6 2.80e-3 CTHERM2 6 5 1.00e-2 CTHERM3 5 4 6.80e-3 CTHERM4 4 3 7.00e-3 CTHERM5 3 2 1.60e-2 CTHERM6 2 tl 15.55 RTHERM1 CTHERM1 6 RTHERM1 th 6 7.94e-3 RTHERM2 6 5 1.98e-2 RTHERM3 5 4 5.57e-2 RTHERM4 4 3 3.13e-1 RTHERM5 3 2 4.71e-1 RTHERM6 2 tl 6.26e-2 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model HRFZ44N template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.80e-3 ctherm.ctherm2 6 5 = 1.00e-2 ctherm.ctherm3 5 4 = 6.80e-3 ctherm.ctherm4 4 3 = 7.00e-3 ctherm.ctherm5 3 2 = 1.60e-2 ctherm.ctherm6 2 tl = 15.55 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 rtherm.rtherm1 th 6 = 7.94e-3 rtherm.rtherm2 6 5 = 1.98e-2 rtherm.rtherm3 5 4 = 5.57e-2 rtherm.rtherm4 4 3 = 3.13e-1 rtherm.rtherm5 3 2 = 4.71e-1 rtherm.rtherm6 2 tl = 6.26e-2 } RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9