ETC HUF76145S3ST

HUF76145P3, HUF76145S3S
TM
Data Sheet
August 2000
75A, 30V, 0.0045 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
Features
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers,
low-voltage bus switches, and power management in
portable and battery-operated products.
• 75A, 30V
File Number
4401.8
• Logic Level Gate Drive
• Ultra Low On-Resistance, rDS(ON) = 0.0045Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76145.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Packaging
PART NUMBER
PACKAGE
JEDEC TO-220AB
BRAND
HUF76145P3
TO-220AB
76145P
HUF76145S3S
TO-263AB
76145S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76145S3ST.
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Symbol
D
JEDEC TO-263AB
G
S
DRAIN
(FLANGE)
GATE
SOURCE
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER™ is a trademark of Analogy, Inc.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HUF76145P3, HUF76145S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
30
30
±16
V
V
V
75
75
75
Figure 4
Figure 6
270
2.17
-40 to 150
A
A
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figures 9, 10)
-
0.0035
0.0045
Ω
ID = 75A, VGS = 5V (Figure 9)
-
0.0043
0.0058
Ω
ID = 75A, VGS = 4.5V (Figure 9)
-
0.0046
0.0065
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
0.46
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-220 and TO-263
-
-
62
oC/W
tON
VDD = 15V, ID ≅ 75A,
RL = 0.20Ω, VGS = 4.5V,
RGS = 2.5Ω
(Figure 15)
-
-
255
ns
-
26
-
ns
-
145
-
ns
td(OFF)
-
35
-
ns
tf
-
39
-
ns
tOFF
-
-
110
ns
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
2
HUF76145P3, HUF76145S3S
TA = 25oC, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
110
ns
-
16
-
ns
-
57
-
ns
td(OFF)
-
53
-
ns
tf
-
38
-
ns
tOFF
-
-
135
ns
-
130
156
nC
-
73
88
nC
-
4.65
5.6
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 75A,
RL = 0.20Ω, VGS = 10V,
RGS = 2.2Ω
(Figure 16)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V,
ID ≅ 75A,
RL = 0.20Ω
Ig(REF) = 1.0mA
(Figure 14)
Gate to Source Gate Charge
Qgs
-
12.30
-
nC
Gate to Drain “Miller” Charge
Qgd
-
40.00
-
nC
-
4900
-
pF
-
2520
-
pF
-
560
-
pF
MIN
TYP
MAX
UNITS
ISD = 75A
-
-
1.25
V
trr
ISD = 75A, dISD/dt = 100A/µs
-
-
115
ns
QRR
ISD = 75A, dISD/dt = 100A/µs
-
-
255
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves
80
1.0
VGS = 10V
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
60
VGS = 4.5V
40
20
0.2
0
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
3
150
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76145P3, HUF76145S3S
Typical Performance Curves
(Continued)
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
5000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
1000
175 - TC
I = I25
150
VGS = 10V
100
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
1000
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
100µs
100
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
SINGLE PULSE
TJ = MAX RATED TC = 25oC
10
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10ms
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
100
10
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76145P3, HUF76145S3S
Typical Performance Curves
150
(Continued)
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
120
90
60
150oC
-40oC
30
25oC
120
VGS = 4.5V
90
VGS = 4V
60
VGS = 3V
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VDD = 15V
0
0
0
1
2
3
4
5
1
0
FIGURE 7. TRANSFER CHARACTERISTICS
4
1.8
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 75A
ON RESISTANCE (mΩ)
3
FIGURE 8. SATURATION CHARACTERISTICS
20
rDS(ON), DRAIN TO SOURCE
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
15
ID = 50A
10
5 ID = 25A
0
2
4
6
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 75A
1.5
1.2
0.9
0.6
-60
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
60
120
180
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.4
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
1.2
1.0
0.8
0.6
0.4
-60
0
TJ, JUNCTION TEMPERATURE (oC)
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = 3.5V
VGS = 10V
VGS = 5V
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5
ID = 250µA
1.1
1.0
0.9
-60
0
60
120
TJ , JUNCTION TEMPERATURE (oC)
180
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76145P3, HUF76145S3S
Typical Performance Curves
(Continued)
10
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
6000
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
8000
CISS
4000
COSS
2000
CRSS
0
0
10
5
20
15
8
6
4
2
VDD = 15V
0
30
25
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 50A
ID = 25A
0
80
40
VDS , DRAIN TO SOURCE VOLTAGE (V)
120
160
Qg , GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
1200
1000
VGS = 4.5V, VDD = 15V, ID = 75A, RL= 0.20Ω
VGS = 10V, VDD = 15V, ID = 75A, RL= 0.20Ω
tr
800
800
td(OFF)
SWITCHING TIME (ns)
SWITCHING TIME (ns)
1000
tf
600
400
td(OFF)
600
tf
400
tr
200
200
td(ON)
td(ON)
0
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
-
VGS
VDS
IAS
VDD
VDD
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
6
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76145P3, HUF76145S3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
IG(REF)
0
Qg(TH)
IG(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
7
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76145P3, HUF76145S3S
PSPICE Electrical Model
SUBCKT HUF76145 2 1 3 ;
rev 6 Apr98
CA 12 8 7.75e-9
CB 15 14 7.45e-9
CIN 6 8 4.47e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
EBREAK 11 7 17 18 33.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
IT 8 17 1
LGATE
GATE
1
LDRAIN 2 5 1.00e-9
LGATE 1 9 2.60e-9
LSOURCE 3 7 1.10e-9
KGATE LSOURCE LGATE 0.0085
+
17
EBREAK 18
50
-
EVTEMP
RGATE +
18 22
9
20
21
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 0.59e-3
RGATE 9 20 0.898
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.20e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBODY
-
S2A
14
13
13
8
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*750),3))}
.MODEL DBODYMOD D (IS = 6.01e-12 IKF = 20 RS = 1. 72e-3 TRS1 = 1.01e-3 TRS2 = 1.21e-6 CJO = 8.41e-9 TT = 4.84e-8 M = 0.45 )
.MODEL DBREAKMOD D (RS = 6.80e-2 TRS1 = 1.12e-3 TRS2 = 1.25e-6 )
.MODEL DPLCAPMOD D (CJO = 4.25e-9 IS = 1e-30 N = 10 M = 0.61)
.MODEL MMEDMOD NMOS (VTO = 1.74 KP = 5.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.898)
.MODEL MSTROMOD NMOS (VTO = 2.10 KP = 245 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.98 RS= 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.01e-3 TC2 = 1.07e-7)
.MODEL RDRAINMOD RES (TC1 = 1.58e-2 TC2 = 3.76e-5)
.MODEL RSLCMOD RES (TC1 = 1.02e-4 TC2 = -1.13e-4)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.73e-3 TC2 = -1.01e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.50e-3 TC2 = 1.25e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.00 VOFF= -1.50)
VON = -1.50 VOFF= -6.00)
VON = 0.00 VOFF= 0.45)
VON = 0.45 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
HUF76145P3, HUF76145S3S
SABER Electrical Model
REV 6 Apr 1998
template huf76145 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 6.01e-12, cjo = 8.41e-9, tt = 4.84e-8, m = 0.45)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.25e-9, is = 1e-30, n = 10, m = 0.61)
m..model mmedmod = (type=_n, vto = 1.74, kp = 5.00, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.10, kp = 245, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = -6.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = 0.45)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.45, voff = 0.0)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
c.ca n12 n8 = 7.75e-9
c.cb n15 n14 = 7.45e-9
c.cin n6 n8 = 4.47e-9
LGATE
l.ldrain n2 n5 = 1.00e-9
RLGATE
l.lgate n1 n9 = 2.60e-9
l.lsource n3 n7 = 1.10e-9
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
EVTEMP
RGATE +
18 22
9
20
DBODY
EBREAK
+
17
18
MSTRO
-
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
13
S2A
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/750))** 3))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 33.50
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
MWEAK
MMED
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.01e-3, tc2 = 1.07e-7
res.rdbody n71 n5 = 1.72e-3, tc1 = 1.01e-3, tc2 = 1.21e-6
res.rdbreak n72 n5 = 6.80e-2, tc1 = 1.12e-3, tc2 = 1.25e-6
res.rdrain n50 n16 = 0.59e-3, tc1 = 1.58e-2, tc2 = 3.76e-5
res.rgate n9 n20 = 0.898
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 1.02e-4, tc2 = -1.13e-4
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.20e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.50e-3, tc2 = 1.25e-6
res.rvthres n22 n8 = 1, tc1 = -2.73e-3, tc2 = -1.01e-5
6
71
11
EVTHRES
16
21
+ 19 8
+
GATE
1
i.it n8 n17 = 1
RDRAIN
6
8
ESG
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
DBREAK
50
-
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
HUF76145P3, HUF76145S3S
SPICE Thermal Model
th
REV Aug 2000
JUNCTION
HUF76145T
CTHERM1 th 6 6.3e-3
CTHERM2 6 5 1.5e-2
CTHERM3 5 4 2.0e-2
CTHERM4 4 3 3.0e-2
CTHERM5 3 2 8.0e-2
CTHERM6 2 tl 1.5e-1
RTHERM1
CTHERM1
6
RTHERM1 th 6 5.0e-3
RTHERM2 6 5 1.8e-2
RTHERM3 5 4 5.0e-2
RTHERM4 4 3 8.5e-2
RTHERM5 3 2 1.0e-1
RTHERM6 2 tl 1.1e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
RTHERM3
CTHERM3
SABER thermal model HUF76145T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.3e-3
ctherm.ctherm2 6 5 = 1.5e-2
ctherm.ctherm3 5 4 = 2.0e-2
ctherm.ctherm4 4 3 = 3.0e-2
ctherm.ctherm5 3 2 = 8.0e-2
ctherm.ctherm6 2 tl = 1.5e-1
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 = 5.0e-3
rtherm.rtherm2 6 5 = 1.8e-2
rtherm.rtherm3 5 4 = 5.0e-2
rtherm.rtherm4 4 3 = 8.5e-2
rtherm.rtherm5 3 2 = 1.0e-1
rtherm.rtherm6 2 tl = 1.1e-1
}
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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