TMS320VC5504/5 to TMS320C5505/04/14/15
Application Migration Guide
ABSTRACT
TMS320VC5504/5 and TMX320VC5504/5 (Silicon Revision 1.4) will here forth in this document
be referred to as VC5505. The TMS320C5504/5 (Device Revision A, Silicon Revision 2.0) will
here forth in this document be referred to as C5505. The TMS320C5514/5 (Device Revision A,
Silicon Revision 2.0) will here forth in this document be referred to as C5515. When referring to
TMS320C5504/5 and TMS320C5514/5 in the document the term C5505/15 will be used to refer
to all four devices.
This document provides the minimum changes required to migrate from the VC5505 to the
C5505/15. Enhancements or new features of the C5505/15 that do not affect migrating from the
VC5505 to the C5505/15 are not covered in this document. For details of the functional
differences between the VC5505 and C5505/15 at the device level, please see the
TMS320VC5504/5 to TMS320C5504/05/14/15 Device Migration Guide.
All efforts have been made to provide a comprehensive list of changes, this will be updated if
additional changes are identified. A CSL (Chip Support Library) migration guide for VC5505 to
C5505/15 migration has also be been published and is available at C55XCSL-LOWPWR 1.0 to
2.x Migration Guide.
March 2010
Version 1.0
1
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
Table of Contents
1
OPERATING VOLTAGES AND CPU SPEEDS............................................................................. 3
2
PIN AND PACKAGE CONSIDERATIONS.................................................................................... 3
2.1
2.2
3
PLL....................................................................................................................................................... 5
3.1
3.2
3.3
3.4
4
MEMORY STANDBY ON THE VC5505 ........................................................................................... 7
MEMORY STANDBY ON THE C5505/15......................................................................................... 8
RTC ...................................................................................................................................................... 9
5.1
6
PLL CHANGES ............................................................................................................................. 5
PLL CONFIGURATION .................................................................................................................. 5
PLL EXAMPLE CODE .................................................................................................................... 6
PLL CALCULATOR ....................................................................................................................... 6
MEMORY RETENTION ENHANCEMENT.................................................................................. 7
4.1
4.2
5
SDRAM AND MSDRAM SUPPORT .............................................................................................. 3
FUNCTIONALITY CHANGES RELATED TO LDOS ........................................................................... 4
BCD VALUES OF DAY AND MONTH CORRECTION ....................................................................... 9
ENDIANNESS CHANGES FROM VC5505 TO C5505/15............................................................10
6.1
6.2
6.3
6.4
SINGLE DATA PATH: EMIF AND ON-CHIP RAM ........................................................................12
SINGLE DATA PATH: MMC/SD AND ON-CHIP RAM ..................................................................12
SINGLE DATA PATH: USB AND ON-CHIP RAM ..........................................................................12
MULTIPLE DATA PATHS: USB , ON-CHIP RAM, AND MMC/SD ................................................12
7
USB REGISTER ADDRESS CHANGES ........................................................................................13
8
REFERENCES...................................................................................................................................14
2
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
1 Operating Voltages and CPU Speeds
Table 1-1 Operating Voltages and CPU speeds for VC5505/4 and C55105/15
VC5505/04 - 100
CVDD Max CPU Speed
1.05V
60 MHz
1.3V
100 MHz
C5505/15 -100
CVDD Max CPU Speed
1.05V 60 MHz
1.3V
100 MHz
C5505/15 -120
CVDD Max CPU Speed
1.05V 75 MHz
1.3V
120 MHz
2 Pin and Package Considerations
The VC5505 and C5505/15 have the same package. The devices are not fully pin to pin
compatible from the PCB (Print Circuit Board) design point of view. Major changes are:
Addition of SDRAM and mSDRAM support on C5505/15 that was not available on
VC5505.
Functionality changes related to LDOs.
2.1 SDRAM and mSDRAM Support
The pin changes for the added SDRAM and mSDRAM support in C5505/15 are provided in Table
1-1. The only corresponding board level changes needed are to connect the SDRAM/mSDRAM
device.
Ball
No
B3
A4
M3
N2
A6
VC5505 pin name and
description
RSV10
Reserved. (Leave
unconnected, do not
connect to power or
ground).
RSV11
Reserved. (Leave
unconnected, do not
connect to power or
ground).
RSV12
Reserved. (Leave
unconnected, do not
connect to power or
ground).
RSV13
Reserved. (Leave
unconnected, do not
connect to power or
ground).
RSV14
Reserved. (Leave
C5505 pin name
and description
____________
EM_CS0
C5515 pin name and
description
Same as C5505
EMIF SDRAM/mSDRAM
chip select 0 output
Same as C5505
____________
EM_CS1
EMIF SDRAM/mSDRAM
chip select 1 output
EM_SDCLK
EMIF SDRAM/mSDRAM
clock
Same as C5505
EM_SDCKE
EMIF SDRAM/mSDRAM
clock enable
Same as C5505
________________
EM_SDRAS
3
Same as C5505
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
B4
P1
B5
unconnected, do not
connect to power or
ground).
RSV15
Reserved. (Leave
unconnected, do not
connect to power or
ground).
EM_DQM1
EMIF asynchronous data
write strobes and byte
enables
EM_DQM0
EMIF asynchronous data
write strobes and byte
enables
EMIF SDRAM/mSDRAM
row address strobe
________________
EM_SDCAS
Same as C5505
EMIF SDRAM/mSDRAM
column strobe
EM_DQM1
EMIF asynchronous data
write strobes and byte
enables or EMIF SDRAM
and mSDRAM data mask
bits.
EM_DQM0
EMIF asynchronous data
write strobes and byte
enables or EMIF SDRAM
and mSDRAM data mask
bits.
Same as C5505
Same as C5505
Table 2-1 Pins with Added Functionality for SDRAM/mSDRAM Support
2.2 Functionality Changes Related to LDOs
The functionality changes related to LDOs between VC5505 and C5505/15 can be summarized in
the table 1-2.
LDO
Functions/Pins
VC5505
C5505
C5515
ANA_LDO
Supported
Supported
Supported
DSP_LDO
Not Supported
Note: DSP_LDO is not
supported but is
required to be enabled
due to the internal POR
performance issue.
Not supported
Note: DSP_LDO must be
disabled
USB_LDO
Not Supported
Note: USB_LDO must
be disabled
Not Supported
Note: USB_LDO must be
disabled
LDO Input Pins
ANA_LDOI
DSP_LDOI
USB_LDOI
Three LDO input pins
are independent each
other. ANA_LDOI and
DSP_LDOI are required
to be powered.
Three LDO input pins are
internally connected. The pin
name of each LDO inputs
pins share the same name,
LDOI. The three LDOI pins
Supported
Note: DSP_LDO can be
enabled or disabled. When
enabled, 5uF - 10uF
decoupling cap are
recommended to the
DSP_LDO output pin
(DSP_LDOO)
Supported
Note: USB_LDO can be
enabled or disabled. When
enabled, 1uF - 2uF
decoupling cap are
recommended to the
USB_LDO output pin
(USB_LDOO)
Same as C5505
4
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
USB_LDOI should be
tied to VSS
____________________
DSP_LDO_EN
pin
DSP_LDO_V pin
(for VC5505),
RSV16 pin (for
C5505/15)
Since DSP_LDO is
required to be turned
on, this pin must be tied
to ground (VSS).
This pin must be
connected to the same
supply as the
ANA_LDOI pin
must be connected to the
same power supply source
with a voltage range of 1.8V
to 3.6V even when LDOs
are not used.
This pin must be tied to
LDOI, via 2-kΩ resistor to
disable the DSP_LDOO pin.
Reserved pin. For proper
device operation, this pin
must be directly tied to either
VSS or LDOI or tied via a
10kΩ resistor to either Vss
or LDOI For proper device
operation this pin must be
left Floating / No Connection
This pin can be tied to VSS
or LDOI but must not be
dynamically switched.
Same as C5505
Table 1-2 LDO functional changes between VC5505 and C5505/15
3 PLL
3.1 PLL Changes
On the VC5505, it was not possible to divide down the PLL output frequency by a factor of 4, so
the PLL was unable to generate frequencies from 16 MHz – 23 MHz.
On the C5505/15, the following divide-by values are supported: 1, 2, 3, 4, … 128. Note that when
odd divisor values other than divide-by-1 are applied, clock high or low period (duty cycle) of the
system clock will not be 50%, this may degrade speed performance of the whole chip.
3.2 PLL Configuration
To migrate from VC5505 to C5505/15, PLL register configuration must be updated to get a
desired output frequency, but the sequence of configuring PLL registers has not been changed.
Table 1-1 lists the most commonly used PLL output frequencies and their PLL register
configurations.
Table 2-1 PLL Register Configurations
PLL Output
Frequency
120MHz
PLL Input
Frequency
(RTC)
32.768KHz
100 MHz
32.768KHz
PLL Registers
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
5
PLL Register
Configuration
for C5505/15
0x8E4A
0x8000
0x0806
0x0000
0x8BE8
0x8000
0x0806
PLL Register
Configuration for
VC5505
Not supported
0x82F4
0x8000
0x0806
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
75MHz
32.768KHz
60MHz
32.768KHz
40MHz
32.768KHz
20MHz
32.768KHz
12.288MHz
32.768KHz
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
CGCR1 (0x1C20)
CGCR2 (0x1C21)
CGCR3 (0x1C22)
CGCR4 (0x1C23)
0x0000
0x88ED
0x8000
0x0806
0x0000
0x8724
0x8000
0x0806
0x0000
0x8986
0x8000
0x0806
0x0201
0x8986
0x8000
0x0806
0x0203
0x8BB4
0x8000
0x0806
0x0207
0x0000
0x823B
0x9000
0x0806
0x0000
0x81C9
0x8000
0x0806
0x0000
0x8262
0xA000
0x0806
0x0300
Not supported
0x82ED
0x8000
0x0806
0x0200
3.3 PLL Example code
PLL frequency can be set either in GEL file (during CCS debug) or in a C program. Here is an
example that sets the C5505/15 PLL to 120MHz
void PLL_120MHz(void)
{
// bypass PLL
CONFIG_MSW = 0x0;
// configure PLL registers for 120MHz
PLL_CNTL1 = 0x8E4A;
PLL_CNTL2 = 0x8000;
PLL_CNTL3 = 0x0806;
PLL_CNTL4 = 0x0000;
// wait for Lock bit
while ( (PLL_CNTL3 & 0x0008) == 0);
// Switch to PLL clock
CONFIG_MSW = 0x1;
}
3.4 PLL Calculator
For frequencies that are not in Table 2-1, the provided “C5505_pll_calculator.xls” file can be used
to generate PLL register configurations for any PLL output frequencies. The file includes some
examples and the steps below explain how to use the file.
1. Do not change the values in the orange color rows in the file, and the values for the TI
Test Registers.
6
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
2. Fclkin: Clock frequency to the CLKIN pin. This is only used when an external clock
source is used (CLK_SEL =1)
3. CLK_SEL: CLK_SEL = 0 when the RTC oscillator is used as the PLL source. CLK_SEL
= 1 when an external clock source is used as the PLL source.
4. RP_BYPASS: Input divider on (0) /off (1). When the RTC oscillator is used as the PLL
source, RP_BYPASS = 1.
5. RP[11:0]: input divider value
6. RefClk (PhaseDet Input) Freq: calculated PLL input frequency (do not change)
7. RefClk Freq Range Check: “OK” = within the VCO input frequency range. “Out Of
Range” = outside of the VCO input frequency range which means the register setting are
not valid (do not change)
8. FP[11:0]: VCO feedback divider
9. VcoOut Freq: calculated VCO output frequency (do not change)
10. VcoOut Freq Range Check: “OK” = within the VCO output frequency range. “Out Of
Range” = outside of the VCO output frequency range which means the register setting
are not valid (do not change)
11. OUTDIVIDE: output divider on (1)/ off (0)
12. PDIV[5:0]: output divider
13. PLL_OUTCK Freq: calculated PLL output frequency after the output divider (do not
change)
14. PLL_OUTCK_O Freq Range Check (C5505/04): “OK” = within the PLL output frequency
range. “Out Of Range” = outside of the PLL output frequency range which means the
register setting are not valid (do not change)
15. PLL_OUTCK_O Freq Range Check (C5515/14): “OK” = within the PLL output frequency
range. “Out Of Range” = outside of the PLL output frequency range which means the
register setting are not valid (do not change)
16. PWDN: Power down bit (0 = normal operation)
17. STANDBY: Standby bit (0= normal operation)
18. PLL_CNTL1: calculated value of the PLL_CNTL1 register (0x1C20)
19. PLL_CNTL2: calculated value of the PLL_CNTL2 register (0x1C21)
20. PLL_CNTL3: calculated value of the PLL_CNTL3 register (0x1C22)
21. PLL_CNTL4: calculated value of the PLL_CNTL4 register (0x1C23)
4 Memory Retention Enhancement
Memory retention feature has been changed from the VC5505 to the C5505/15. If the memory
retention feature is used for the VC5505, the same control won’t work for the C5505/15. The
memory retentions control must be updated to properly migrate from the VC5505 to the C5505/15.
On VC5505, it was only possible to control the retention mode for all DARAMs together and all
SARAMs together. The C5505/15 improves the memory retention features by adding individual
control of memory retention for each bank of memory. The address for each memory bank is
provided in the device datasheet.
4.1 Memory Standby on the VC5505
The RAM Sleep Mode Control Register [0x1C28] controls the retention mode for all DARAMs
together (bit 0 and 1) and all SARAMs together (bit 3 and 2).
7
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
Figure 4-1: RAM Sleep Mode Control Register1 [0x1C28]
15
4
3
2
1
0
Reserved
SARAM
SLPZVDD
SARAM
SLPZVSS
DARAM
SLPZVDD
DARAM
SLPZVSS
R+000000000000
RW+1
RW+1
RW+1
RW+1
4.2 Memory Standby on the C5505/15
C5505/15 improves the memory retention features by adding individual control of memory
retention for each bank of memory. The address for each memory bank is provided in the device
datasheet.
The register additions for C5505/15 are provided below.
Figure 4-2: RAM Sleep Mode Control Register1 [0x1C28]
15
14
13
12
11
10
9
8
DARAM7
SLPZVDD
DARAM7
SLPZVSS
DARAM6
SLPZVDD
DARAM6
SLPZVSS
DARAM5
SLPZVDD
DARAM5
SLPZVSS
DARAM4
SLPZVDD
DARAM4
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
7
6
5
4
3
2
1
0
DARAM3
SLPZVDD
DARAM3
SLPZVSS
DARAM2
SLPZVDD
DARAM2
SLPZVSS
DARAM1
SLPZVDD
DARAM1
SLPZVSS
DARAM0
SLPZVDD
DARAM0
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
Figure 4-3: RAM Sleep Mode Control Register2 [0x1C2A]
15
14
13
12
11
10
9
8
SARAM7
SLPZVDD
SARAM7
SLPZVSS
SARAM6
SLPZVDD
SARAM6
SLPZVSS
SARAM5
SLPZVDD
SARAM5
SLPZVSS
SARAM4
SLPZVDD
SARAM4
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
7
6
5
4
3
2
1
0
SARAM3
SLPZVDD
SARAM3
SLPZVSS
SARAM2
SLPZVDD
SARAM2
SLPZVSS
SARAM1
SLPZVDD
SARAM1
SLPZVSS
SARAM0
SLPZVDD
SARAM0
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
15
14
13
12
11
10
9
8
SARAM15
SLPZVDD
SARAM15
SLPZVSS
SARAM14
SLPZVDD
SARAM14
SLPZVSS
SARAM13
SLPZVDD
SARAM13
SLPZVSS
SARAM12
SLPZVDD
SARAM12
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
Figure 4-4: RAM Sleep Mode Control Register3 [0x1C2B]
7
6
5
4
3
2
1
0
SARAM11
SLPZVDD
SARAM11
SLPZVSS
SARAM10
SLPZVDD
SARAM10
SLPZVSS
SARAM9
SLPZVDD
SARAM9
SLPZVSS
SARAM8
SLPZVDD
SARAM8
SLPZVSS
8
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
Figure 4-5: RAM Sleep Mode Control Register4 [0x1C2C]
15
14
13
12
11
10
9
8
SARAM23
SLPZVDD
SARAM23
SLPZVSS
SARAM22
SLPZVDD
SARAM22
SLPZVSS
SARAM21
SLPZVDD
SARAM21
SLPZVSS
SARAM20
SLPZVDD
SARAM20
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
7
6
5
4
3
2
1
0
SARAM19
SLPZVDD
SARAM19
SLPZVSS
SARAM18
SLPZVDD
SARAM18
SLPZVSS
SARAM17
SLPZVDD
SARAM17
SLPZVSS
SARAM16
SLPZVDD
SARAM16
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
15
14
13
12
11
10
9
8
SARAM31
SLPZVDD
SARAM31
SLPZVSS
SARAM30
SLPZVDD
SARAM30
SLPZVSS
SARAM29
SLPZVDD
SARAM29
SLPZVSS
SARAM28
SLPZVDD
SARAM28
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
7
6
5
4
3
2
1
0
SARAM27
SLPZVDD
SARAM27
SLPZVSS
SARAM26
SLPZVDD
SARAM26
SLPZVSS
SARAM25
SLPZVDD
SARAM25
SLPZVSS
SARAM24
SLPZVDD
SARAM24
SLPZVSS
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
RW+1
Figure 4-6: RAM Sleep Mode Control Register5 [0x1C2D]
Table 4-1: RAM Sleep Mode Control Register Bit Field Definitions
Field
Description
DARAMx
SLPZVSS
Memory Standby Enable for DARAMx
0 =Low power retention mode. No read or write access allowed. Memory contents are retained.
1 = Normal operational mode. Read or write access allowed.
DARAMx
SLPZVDD
Memory Standby Enable for DARAMx
0 = Inactive mode. No read or write access allowed. Memory content is not retained.
1 = Normal operational mode. Read or write access allowed.
SARAMx
SLPZVSS
Memory Standby Enable for SARAMx
0 = Low power retention mode. No read or write access allowed. Memory contents are retained.
1 = Normal operational mode. Read or write access allowed.
SARAMx
SLPZVDD
Memory Standby Enable for SARAMx
0 = Inactive mode. No read or write access allowed. Memory content is not retained.
1 = Normal operational mode. Read or write access allowed.
5 RTC
5.1 BCD Values of Day and Month Correction
The C5505/15 corrects the issue in VC5505 where the binary coded decimal values of RTC Day
and Month register incorrectly increment from 0x09 to 0x1A instead of correctly incrementing from
0x09 to 0x10. Once this occurs on VC5505, the Day and Month registers increase incorrectly. For
example: 09 -> 1A →1B → 1C → 1D → 1E → 1F → 10 → 11…
9
TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
On the VC5505, the program must reload the correct number 0x10 when 0x1A is detected. The
correction is not necessary and can be removed for the C5505/15.
6 Endianness Changes from VC5505 to C5505/15
Table 4-1 shows the differences in endianness between the VC5505 and the C5505/15.
Table 4-1 Summary of endianness in the VC5505 and the C5505/15
C55x CPU
EMIF
USB
VC5505
Big endian
Configured in hardware as little endian
CORE, and CDMA are little endian
MMC/SD
Endianness is software programmable.
Default is little endian
LCD
Endianness is software programmable,
default is little endian
Performs word swap
Performs word swap
DPORT
IPORT
C5505/15
Big endian
Configured in hardware as big endian
CORE is little endian.
CDMA is big endian
Endianness is software programmable.
Default is big endian
Note: If the C550515 bootloader
reaches the MMC/SD during boot-up,
the bootloader will configure MMC/SD
as little endian.
Endianness is software programmable,
default is little endian
Does not perform word swap
Does not perform word swap
Figure 4-1 and Figure 4-2 depict the endianness of the VC5505 and the C5505/15 along with
data paths, which can be used to determine if any software changes are needed to prevent data
swaps when migrating from the VC5505 to the C5505/15.
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TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
Figure 4-1 Block Diagram of VC5505 Endianness
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TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
Figure 4-2 Block Diagram of C5505/15 Endianness
A single data path or multiple data paths can be used in an application. The following sections
provide details of how endianness affects data formats with different data paths. Software
examples in C5505/15 CSL are also provided to help users migrate from the VC5505 to the
C5505/15.
6.1 Single Data Path: EMIF and On-Chip RAM
The C5505/15 has corrected the possible data swaps (word swap or byte swap) that could have
occurred on the VC5505 between the on-chip RAM and External Memory Interface (EMIF). If any
software was used to correct the data swap between the on-chip RAM and EMIF on the VC5505,
the software correction is no longer necessary and should be removed for the C5505/15.
6.2 Single Data Path: MMC/SD and On-Chip RAM
Endianness of MMC/SD controller is software programmable but its default has been changed to
big endian on the C5505/15 from little endian on the VC5505.
When the C5505/15 bootloader reaches MMC/SD during boot-up, the bootloader configures
MMC/SD endianness as little endian. Therefore the programmer should not rely on the default
configuration. Desired MMC/SD endianness should be set after boot-up.
C5505/15 CSL provides MMC/SD examples to help users migrate from the VC5505 to the
C5505/15. There are four MMC/SD examples (example #1 through #4) and endianness change is
properly handled in the examples. Please see the C5505/15 CSL migration guide for details of
the examples.
6.3 Single Data Path: USB and On-Chip RAM
On the VC5505, the USB module is little endian. On the C5505/15, the USB Core is still little
endian but the USB CDMA has been changed to big endian.
Data in the USB module can be read either by the USB module’s CDMA or the CPU XPORT
accesses. On the C5505/15, when the USB CDMA accesses on-chip RAM through the MPORT,
the USB CDMA handles these transfers in big endian fashion (little endian fashion for the
VC5505). On the other hand, when the CPU accesses the USB data buffers in the USB Core
through XPORT, the USB Core handles these transfers in little endian fashion on both VC5505
and C5505/15. Therefore, if any software was used to correct the data format between the onchip RAM and USB on the VC5505, the correction caused by the CPU data accesses is still
needed, but the correction caused by the USB CDMA data accesses is not necessary and can be
removed for the C5505/15.
C5505/15 CSL provides USB examples to help users migrate from the VC5505 to the C5505/15.
The USB examples support multiple data paths. Among the USB examples, examples #1, #2,
and #3 are for the data path between on-chip RAM and USB controller. Data endianness is
properly handled in the examples and is transparent to users. Please see the C5505/15 CSL
migration guide for details of the examples.
6.4 Multiple Data Paths: USB , On-Chip RAM, and MMC/SD
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Application Migration Guide
Multiple data paths can be used in an application. C5505/15 CSL provides a software example of
USB Mass Storage Device application which uses MMC/SD card for data storage (USB example
#4). Data endianness is properly handled in the example and is transparent to Users. Please see
the C5505/15 CSL migration guide for details of the example.
7 USB Register Address Changes
The change in endianness on the C5505/15 resulted in a minor change in the address of the USB
registers in the Core registers (the address is offset by 1) as shown in Table 5-1 below. The same
table is also provided in the Device Migration Guide. The updated register addresses must be
used to control USB module in the C5505/15.
Table 5-1: USB Registers Address Changes
VC5505 Address
0x8400
0x8401
C5505/15 Address
0x8401
0x8402
0x8404
0x8405
0x8408
0x8409
0x8405
0x8406
0x8409
0x840A
0x840C
0x840D
0x840D
0x840E
0x8410
0x8411
0x8411
0x8412
0x8414
0x8415
0x8415
0x8416
0x8418
0x8419
0x841D
0x841E
0x8420
0x8421
0x8424
0x8425
0x8428
0x8429
0x842C
0x842D
0x8430
0x8431
0x8421
0x8422
0x8425
0x8426
0x8429
0x842A
0x842D
0x842E
0x8431
0x8432
Register Name
Function Address Register, Power Management Register
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1
to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts, Interrupt
Enable Register
Frame Number Register
Index Register for Selecting the Endpoint Status and
Control Registers, Register to Enable the USB 2.0 Test
Modes
Maximum Packet Size for Peripheral/Host Transmit
Endpoint. (Index register set to select Endpoints 1-4)
Control Status Register for Peripheral Endpoint 0. (Index
register set to select Endpoint 0) or Control Status Register
for Peripheral Transmit Endpoint. (Index register set to
select Endpoints 1-4)
Maximum Packet Size for Peripheral/Host Receive
Endpoint. (Index register set to select Endpoints 1-4)
Control Status Register for Peripheral Receive Endpoint.
(Index
register set to select Endpoints 1-4)
Number of Received Bytes in Endpoint 0 FIFO. (Index
register set to select Endpoint 0) or Number of Bytes in Host
Receive Endpoint FIFO. (Index register set to select
Endpoints 1- 4)
Returns details of core configuration. (index register set to
select Endpoint 0)
Transmit and Receive FIFO Register 1 for Endpoint 0
Transmit and Receive FIFO Register 2 for Endpoint 0
Transmit and Receive FIFO Register 1 for Endpoint 1
Transmit and Receive FIFO Register 2 for Endpoint 1
Transmit and Receive FIFO Register 1 for Endpoint 2
Transmit and Receive FIFO Register 2 for Endpoint 2
Transmit and Receive FIFO Register 1 for Endpoint 3
Transmit and Receive FIFO Register 2 for Endpoint 3
Transmit and Receive FIFO Register 1 for Endpoint 4
Transmit and Receive FIFO Register 2 for Endpoint 4
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0x8461
0x8462
0x8464
0x8465
0x8465
0x8466
0x846C
0x8501
0x8508
0x850D
0x8510
0x846D
0x8502
0x8509
0x850E
0x8511
0x8511
0x8512
0x8514
0x8515
0x8515
0x8516
0x8518
0x8520
0x8519
0x8521
0x8521
0x8522
0x8524
0x8525
0x8525
0x8526
0x8528
0x8530
0x8529
0x8531
0x8531
0x8532
0x8534
0x8535
0x8535
0x8536
0x8538
0x8540
0x8539
0x8541
0x8541
0x8542
0x8544
0x8545
0x8545
0x8546
0x8548
0x8549
Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size
(Index
register set to select Endpoints 1-4)
Transmit Endpoint FIFO Address (Index register set to
select Endpoints 1-4)
Receive Endpoint FIFO Address (Index register set to select
Endpoints 1-4)
Hardware Version Register
Control Status Register for Peripheral Endpoint 0
Number of Received Bytes in Endpoint 0 FIFO
Returns details of core configuration.
Maximum Packet Size for Peripheral/Host Transmit
Endpoint 1
Control Status Register for Peripheral Transmit Endpoint 1
(peripheral Mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
1
Control Status Register for Peripheral Receive Endpoint 1
(peripheral mode)
Number of Bytes in Host Receive endpoint 1 FIFO
Maximum Packet Size for Peripheral/Host Transmit
Endpoint 2
Control Status Register for Peripheral Transmit Endpoint 2
(peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
2
Control Status Register for Peripheral Receive Endpoint 2
(peripheral mode)
Number of Bytes in Host Receive endpoint 2 FIFO
Maximum Packet Size for Peripheral/Host Transmit
Endpoint 3
Control Status Register for Peripheral Transmit Endpoint 3
(peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
3
Control Status Register for Peripheral Receive Endpoint 3
(peripheral mode)
Number of Bytes in Host Receive endpoint 3 FIFO
Maximum Packet Size for Peripheral/Host Transmit
Endpoint 4
Control Status Register for Peripheral Transmit Endpoint 4
(peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
4
Control Status Register for Peripheral Receive Endpoint 4
(peripheral mode)
Number of Bytes in Host Receive endpoint 4 FIFO
8 References
1. TMS320VC5504/5 to TMS320C5504/05/14/15 Device Migration Guide
2. VC5505 Datasheet
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TMS320VC5504/05 to TMS320C5504/05/14/15
Application Migration Guide
3.
4.
5.
6.
7.
C5505 Datasheet
C5504 Datasheet
C5515 Datasheet
C5514 Datasheet
C55XCSL-LOWPWR 1.0 to 2.x Migration Guide
15