TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide ABSTRACT TMS320VC5504/5 and TMX320VC5504/5 (Silicon Revision 1.4) devices will here forth in this document be referred to as VC5505. The TMS320C5504/5 (Device Revision A, Silicon Revision 2.0) will here forth in this document be referred to as C5505. The TMS320C5514/5 (Device Revision A, Silicon Revision 2.0) will here forth in this document be referred to as C5515. When referring to TMS320C5504/5 and TMS320C5514/5 in the document the term C5505/15 will be used to refer to all four devices. This document provides a summary of the functional differences between the VC5505 and the C5505/15 devices. All efforts have been made to provide a comprehensive list of the functional differences between these devices; this will be updated if additional changes are identified. A separate migration guide for CSL C55XCSL-LOWPWR 1.0 to 2.x Migration Guide is also being published as well as a simplified application migration guide TMS320VC5504/05 to TMS320C5504/05/14/15 Application Migration Guide. As the focus of this document is the differences between the devices, the descriptions of the behavior and functions of the devices are explained only to the extent necessary to illustrate those differences. Chip documentation referenced at the end of this document should be used for details about each chip. This document does not cover the silicon exceptions that may be present on the devices. Please consult the TMS320C5504/5 Digital Signal Processor Silicon Errata (SPRZ310) and the TMS320C5514/5 Digital Signal Processor Silicon Errata (SPRZ308) for the list of silicon exceptions and the suggested workarounds. March 2010 1 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Version 1.0 Table of Contents 1 PIN AND PACKAGE ......................................................................................................................... 3 2 I/O CHANGES .................................................................................................................................... 6 2.1 2.2 ALLOW CORE POWERED DOWN WHILE I/O SUPPLIES ON ............................................................ 6 REMOVES THE POWER SEQUENCE REQUIREMENTS ...................................................................... 7 3 OPERATING VOLTAGES AND CPU SPEEDS............................................................................. 7 4 CPU AND MEMORY......................................................................................................................... 7 4.1 MEMORY RETENTION ENHANCEMENT – CONTROL PER BANK ...................................................... 8 5 WAKEUP FROM MASTER CLOCKS OFF................................................................................... 9 6 RTC ONLY MODE FEATURE ADDED ....................................................................................... 10 7 BOOTLOADER................................................................................................................................ 10 7.1 7.2 SPI SUPPORTS 24-BIT ADDRESSES ............................................................................................. 10 UART BOOT NO LONGER SUPPORTED ........................................................................................ 10 8 DIE ID................................................................................................................................................ 10 9 INTERRUPT AGGREGATION (GPIO, DMA, AND TIMER) CORRECTIONS .................... 11 10 ENDIANNESS CORRECTIONS .................................................................................................... 11 10.1 11 ANALOG CHANGES ...................................................................................................................... 14 11.1 11.2 11.3 12 C5505/15 USB DATA PATH ENDIANNESS EXAMPLE ................................................................. 14 ADDITION OF SAR RESET BIT .................................................................................................... 14 ADDITIONAL ANA_LDO SUPPLY PINS ...................................................................................... 15 LDO, POR COMPARATOR, AND RESET CHANGES ...................................................................... 15 PERIPHERAL CHANGES.............................................................................................................. 17 12.1 PLL DIVIDER CHANGE AND REGISTER CHANGES ...................................................................... 17 12.2 RTC CORRECTIONS .................................................................................................................... 23 12.3 DMA CORRECTIONS AND FEATURES ADDED ............................................................................. 23 12.3.1 Ping Pong Mode Addition and Data Transfer Control Register Changes....................... 24 12.4 EMIF ......................................................................................................................................... 26 12.4.1 Endianness Change.......................................................................................................... 26 12.4.2 SDRAM and mSDRAM Support Added............................................................................ 27 12.5 I2S CORRECTIONS ...................................................................................................................... 27 12.6 MMC/SD DEFAULT ENDIANNESS CHANGE ............................................................................... 28 12.7 USB ENDIAN CHANGES ............................................................................................................. 28 13 REFERENCES.................................................................................................................................. 30 2 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 1 Pin and Package The VC5505 and C5505/15 have the same package. The devices are not pin to pin compatible but so long as the instructions for compatibility with future devices were followed at board layout, the only change at the board level needed is to populate the desired resistors. The pin changes for the added SDRAM and mSDRAM support in C5505/15 are provided in Table 1-1and the pin changes related to the LDOs provided in Table 1-2. Most of the C5505/15 I/Os have bus keepers which are explained in detail in Section 0. Ball No B3 A4 M3 N2 A6 B4 P1 B5 Table 1-1 Pins with Added Functionality for SDRAM/mSDRAM Support VC5505 pin name and C5505 pin name C5515 pin name and description and description description ____________ RSV10 Same as C5505 EM_CS0 Reserved. (Leave unconnected, do not EMIF SDRAM/mSDRAM connect to power or chip select 0 output ground). ____________ RSV11 Same as C5505 EM_CS1 Reserved. (Leave unconnected, do not EMIF SDRAM/mSDRAM connect to power or chip select 1 output ground). RSV12 EM_SDCLK Same as C5505 Reserved. (Leave EMIF SDRAM/mSDRAM unconnected, do not clock connect to power or ground). RSV13 EM_SDCKE Same as C5505 Reserved. (Leave EMIF SDRAM/mSDRAM unconnected, do not clock enable connect to power or ground). ________________ RSV14 Same as C5505 EM_SDRAS Reserved. (Leave unconnected, do not EMIF SDRAM/mSDRAM connect to power or row address strobe ground). ________________ RSV15 Same as C5505 EM_SDCAS Reserved. (Leave unconnected, do not EMIF SDRAM/mSDRAM connect to power or column strobe ground). EM_DQM1 EM_DQM1 Same as C5505 EMIF asynchronous data EMIF asynchronous data write strobes and byte write strobes and byte enables enables or EMIF SDRAM and mSDRAM data mask bits. EM_DQM0 EM_DQM0 Same as C5505 EMIF asynchronous data EMIF asynchronous data 3 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide write strobes and byte enables Ball No F13 write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits. Table 1-2 Pins with functionality changes related to LDOs VC5505 pin name and C5505 pin name C5515 pin name and description and description description USB_LDOI LDOI LDOI [Not supported on this LDO inputs. The three LDOI LDO inputs. The three LDOI input pins (F12, F14, B12) are input pins (F12, F14, B12) device. Reserved for internally connected and must are internally connected and compatibility with future devices]. be connected to the same must be connected to the For proper device power supply source with a same power supply source operation, this pin must voltage range of 1.8V to 3.6V. with a voltage range of 1.8V be connected to the same These pins supply power to to 3.6V. These pins supply supply as the the internal ANA_LDO, the power to the internal ANA_LDOI pin (B12). bandgap reference generator ANA_LDO, the bandgap circuits, and serve as the I/O reference generator circuits, supply for some input pins. and serve as the I/O supply LDOI pins must be powered for some input pins. LDOI even if ANA_LDO is not used. pins must be powered even if none of the LDOs are used. F14 DSP_LDOI [Not supported on this device. Reserved for compatibility with future devices]. For proper device operation, this pin must be connected to the same supply as the ANA_LDOI pin (B12). LDOI LDO inputs. The three LDOI input pins (F12, F14, and B12) are internally connected and must be connected to the same power supply source with a voltage range of 1.8V to 3.6V. These pins supply power to the internal ANA_LDO, the bandgap reference generator circuits, and serve as the I/O supply for some input pins. LDOI pins must be powered even if ANA_LDO is not used. LDOI LDO inputs. The three LDOI input pins (F12, F14, and B12) are internally connected and must be connected to the same power supply source with a voltage range of 1.8V to 3.6V. These pins supply power to the internal ANA_LDO, the bandgap reference generator circuits, and serve as the I/O supply for some input pins. LDOI pins must be powered even if none of the LDOs are used. B12 ANA_LDOI Analog LDO input. This input pin must be connected to a power supply with a voltage range of 1.8 V to 3.6 V. It supplies power for the ANA_LDO, the bandgap reference generator circuits, and is the I/O supply for some input pins. LDOI LDO inputs. The three LDOI input pins (F12, F14, and B12) are internally connected and must be connected to the same power supply source with a voltage range of 1.8V to 3.6V. These pins supply power to the internal ANA_LDO, the bandgap reference generator circuits, and serve as the I/O supply LDOI LDO inputs. The three LDOI input pins (F12, F14, and B12) are internally connected and must be connected to the same power supply source with a voltage range of 1.8V to 3.6V. These pins supply power to the internal ANA_LDO, the bandgap reference generator circuits, 4 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide D13 D12 DSP_LDO_V [Not supported on this device. Reserved for compatibility with future devices]. For proper device operation, this pin must be connected to the same supply as the ANA_LDOI pin (B12). For future device family compatibility, board designs should have this pin layout with a zero-Ω resistor to ANA_LDOI and a zero-Ω resistor to ground. For VC5505, only the zero-Ω resistor to ANA_LDO should be populated. for some input pins. LDOI pins must be powered even if ANA_LDO is not used. and serve as the I/O supply for some input pins. LDOI pins must be powered even if none of the LDOs are used. RSV16 Reserved. For proper device operation, this pin must be directly tied to either VSS or LDOI or tied via a 10kΩ resistor to either Vss or LDOI. Same as C5505 ____________________ ____________________ DSP_LDO_EN DSP_LDO_EN [Not supported on this device. Reserved for compatibility with future devices]. For proper device operation, this pin must be tied to ground (VSS). For future device family pin compatibility, board designs should have this pin layout with a zero Ω resistor to ANA_LDOI and a 0-Ω resistor to ground. For VC5505, only the 0-Ω resistor to ground should be populated DSP_LDO enable input. [Not supported on this device] For proper device operation, this pin must be tied to LDOI, via 2-kΩ resistor to disable the DSP_LDOO pin. DSP_LDO enable input. This signal is not intended to be dynamically switched. 0 = DSP_LDO is enabled. The internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal. 1= DSP_LDO disabled. The internal POR voltage monitoring is also disabled. The internal POWERGOOD signal is forced high and the external reset signal on the __________ RESET pin (D6) is the only source for the device reset. Note, C5515 device’s internal reset signal is generated as the AND of the __________ RESET pin and the internal POWERGOOD signal. E10 DSP_LDOO [Not supported on this device. Reserved for compatibility with future devices] DSP_LDOO [Not supported on this device. Reserved for compatibility with future devices] For proper device operation 5 DSP_LDOO 5uF - 10uF decoupling cap to VSS Supply power to CVDD pins TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide F12 For proper device operation, this pin must have a 0.1uF decoupling cap to VSS USB_LDOO [Not supported on this device. Reserved for compatibility with future devices] For proper device operation this pin must be left floating / No Connection this pin must be left Floating / No Connection USB_LDOO [Not supported on this device. Reserved for compatibility with future devices] For proper device operation this pin must be left Floating / No Connection USB_LDOO 1 uF ~ 2 uF decoupling capacitor to VSS Supplies power to the USB_ VDD1P3, USB_VDDA1P3 pins 2 I/O Changes 2.1 Allow Core Powered Down While I/O Supplies On VC5505's I/O buffers do not allow the core supply to be powered off while maintaining power to the I/O supply. On VC5505, the core and I/O must be powered together and in a specific sequence. The C5505/15 pin I/O buffers were redesigned to allow the core power supply (CVDD) to be turned off while the I/O supplies (DVDDIO, DVDDRTC, and DVDDEMIF) remain powered. Additionally, the C5505/15 has special I/O bus-holder1 structures to ensure pins are not in an unknown state when CVDD power is removed while I/O power is applied. When CVDD supply is powered ON, the bus-holders are disabled and the internal pullups/pulldowns, if applicable, function normally. But when CVDD supply is powered OFF and the I/O supply is powered ON, the output buffer is in the high impedance state, the bus-holders are enabled, and any applicable internal pullups/pulldowns are disabled. The bus-holders are weak drivers on the pin and, for as long as CVDD supply is powered OFF and I/O supply is power ON, they hold the last state on the pin. If an external device is strongly driving the C5505/15 I/O pin to the opposite state then the bus-holder will flip state to match the external driver, and DC current will stop. In this way, the bus-holder feature prevents unnecessary power consumption. If external pullup or pulldown resistors are implemented on the PCB board, then care should be taken that those pullup/pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to flip state to match the state of the external pullup or pulldown. The datasheet parameters IOLBH & IOHBH provide the bus-holder max current specs and should be used to determine the size of the external pullup/pulldown resistor. If the external resistors are too weak, DC current will flow and consume power unnecessarily. When CVDD power is applied, the bus holders are disabled. Note 1: All digital I/O pins on C5505/15 have bus-holders except the following pins: Pins supplied by the CVDD_RTC and/or DVDD_RTC power domains. These power domains are "Always On" and therefore do not need these special features. The pins are: – RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP 6 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide USB Pins: – USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO 2.2 Removes the Power Sequence Requirements The VC5505 device has power up sequencing requirements that can result in a higher cost for customer systems. The C5505/15 device was redesigned with new I/O cells to remove the need __________ of a specific power-up sequence. However, the external reset signal ( RESET ) must still be asserted until all of the I/O supply voltages reach their valid operation ranges. The I/O design allows either the core supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3) or the I/O supplies (LDOI, DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3) to be powered up for an indefinite period of time while the other supply is not powered, if the following constraints are met: 1. All maximum ratings and recommended operating conditions are satisfied. 2. All warnings about exposure to maximum rated and recommended conditions, particularly junction temperature are satisfied. These apply to power transitions as well as normal operation. 3. Bus voltage contention while core supplies are powered must be limited to 100 hours over the projected lifetime of the device. 4. Bus voltage contention while core supplies are powered down does not violate the absolute maximum ratings. If the USB subsystem is not used, the USB Core (USB_VDD1P3, USB_VDDA1P3) and USB PHY and I/O level supplies (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) can be powered off. Note: If the device is powered up with the USB cable connected to an active USB host and the USB PHY (USB_VDDA3P3) is powered up before the USB Core (USB_VDD1P3, USB_VDDA1P3), the USB Core must be powered within 100 ms after the USB host detects the device has been attached. A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when the voltage is below that range, either stable or while in transition. 3 Operating Voltages and CPU Speeds Table 3-1 Operating Voltages and CPU speeds for VC5505/4 and C55105/15 VC5505/04 - 100 CVDD Max CPU Speed 1.05V 60 MHz 1.3V 100 MHz C5505/15 -100 CVDD Max CPU Speed 1.05V 60 MHz 1.3V 100 MHz C5505/15 -120 CVDD Max CPU Speed 1.05V 75 MHz 1.3V 120 MHz 4 CPU and Memory The VC5505 and C5505/15 CPU core are the same however the C5505/15 has a -120 part with increased frequencies described in Table 3-1. The VC5505 and C5505/15 memory size is the same. The memory retention has been enhanced and is described in the section below. 7 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 4.1 Memory Retention Enhancement – control per bank On VC5505, it was only possible to control the retention mode for all DARAMs together and all SARAMs together. C5505/15 improves the memory retention features by adding individual control of memory retention for each bank of memory. To activate memory retention mode, set the SLPZVDD bit and clear the SLPZVSS bit of each bank. The address for each memory bank is provided in the device datasheet. The register additions for C5505/15 are provided below. Figure 4-1: RAM Sleep Mode Control Register1 [0x1C28] 15 14 13 12 11 10 9 8 DARAM7 SLPZVDD DARAM7 SLPZVSS DARAM6 SLPZVDD DARAM6 SLPZVSS DARAM5 SLPZVDD DARAM5 SLPZVSS DARAM4 SLPZVDD DARAM4 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 7 6 5 4 3 2 1 0 DARAM3 SLPZVDD DARAM3 SLPZVSS DARAM2 SLPZVDD DARAM2 SLPZVSS DARAM1 SLPZVDD DARAM1 SLPZVSS DARAM0 SLPZVDD DARAM0 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 Figure 4-2: RAM Sleep Mode Control Register2 [0x1C2A] 15 14 13 12 11 10 9 8 SARAM7 SLPZVDD SARAM7 SLPZVSS SARAM6 SLPZVDD SARAM6 SLPZVSS SARAM5 SLPZVDD SARAM5 SLPZVSS SARAM4 SLPZVDD SARAM4 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 7 6 5 4 3 2 1 0 SARAM3 SLPZVDD SARAM3 SLPZVSS SARAM2 SLPZVDD SARAM2 SLPZVSS SARAM1 SLPZVDD SARAM1 SLPZVSS SARAM0 SLPZVDD SARAM0 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 Figure 4-3: RAM Sleep Mode Control Register3 [0x1C2B] 15 14 13 12 11 10 9 8 SARAM15 SLPZVDD SARAM15 SLPZVSS SARAM14 SLPZVDD SARAM14 SLPZVSS SARAM13 SLPZVDD SARAM13 SLPZVSS SARAM12 SLPZVDD SARAM12 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 7 6 5 4 3 2 1 0 SARAM11 SLPZVDD SARAM11 SLPZVSS SARAM10 SLPZVDD SARAM10 SLPZVSS SARAM9 SLPZVDD SARAM9 SLPZVSS SARAM8 SLPZVDD SARAM8 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 Figure 4-4: RAM Sleep Mode Control Register4 [0x1C2C] 15 14 13 12 11 10 9 8 SARAM23 SLPZVDD SARAM23 SLPZVSS SARAM22 SLPZVDD SARAM22 SLPZVSS SARAM21 SLPZVDD SARAM21 SLPZVSS SARAM20 SLPZVDD SARAM20 SLPZVSS 8 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 7 6 5 4 3 2 1 0 SARAM19 SLPZVDD SARAM19 SLPZVSS SARAM18 SLPZVDD SARAM18 SLPZVSS SARAM17 SLPZVDD SARAM17 SLPZVSS SARAM16 SLPZVDD SARAM16 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 Figure 4-5: RAM Sleep Mode Control Register5 [0x1C2D] 15 14 13 12 11 10 9 8 SARAM31 SLPZVDD SARAM31 SLPZVSS SARAM30 SLPZVDD SARAM30 SLPZVSS SARAM29 SLPZVDD SARAM29 SLPZVSS SARAM28 SLPZVDD SARAM28 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 7 6 5 4 3 2 1 0 SARAM27 SLPZVDD SARAM27 SLPZVSS SARAM26 SLPZVDD SARAM26 SLPZVSS SARAM25 SLPZVDD SARAM25 SLPZVSS SARAM24 SLPZVDD SARAM24 SLPZVSS RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 RW+1 Table 4-1: RAM Sleep Mode Control Register Bit Field Definitions Field Description DARAMx SLPZVSS Memory Standby Enable for DARAMx 0 =Low power retention mode. No read or write access allowed. Memory contents are retained. 1 = Normal operational mode. Read or write access allowed. DARAMx SLPZVDD Memory Standby Enable for DARAMx 0 = Inactive mode. No read or write access allowed. Memory content is not retained. 1 = Normal operational mode. Read or write access allowed. SARAMx SLPZVSS Memory Standby Enable for SARAMx 0 = Low power retention mode. No read or write access allowed. Memory contents are retained. 1 = Normal operational mode. Read or write access allowed. SARAMx SLPZVDD Memory Standby Enable for SARAMx 0 = Inactive mode. No read or write access allowed. Memory content is not retained. 1 = Normal operational mode. Read or write access allowed. 5 Wakeup from Master Clocks OFF On both VC5505 and C5505/15, the DSP can disable the Master Clock by setting bit 15 of the PCGCR (0x1C02) register. Once the master clock is disabled, only the RESET pin, an RTC alarm, or the WAKEUP pin can re-enable it. The WAKEUP pin is a bidirectional signal and therefore it can be configured as an input or an output. As an input, it is level sensitive. On both VC5505 and C5505/15, when the WAKEUP pin is configured as an input, a high level on the WAKEUP pin will asynchronously clear bit 15 of the PCGCR, and thus, enable the Master Clock. Attempts by software to disable the master clock by writing a 1 to bit 15 of the PCGCR will not take effect if WAKEUP is an input and held HIGH, since the high level on the WAKEUP pin has priority over the setting of the PCGCR. For software to disable the Master Clock, the WAKEUP pin must be held low when configured as an input. VC5505 and C5505/15 differ in functionality when the WAKEUP pin is configured as an output. VC5505: When the WAKEUP pin is configured as an output and held high, software attempts to write a 1 to bit 15 of the PCGCR register will not take effect. 9 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide C5505/15: When WAKEUP is configured as an output, software attempts to write a 1 to bit 15 will take effect regardless of the state of the WAKEUP pin. 6 RTC Only Mode Feature Added C5505/15 provides a RTC-only mode that wasn’t available on VC5505. This mode allows all supplies except DVDDRTC and CVDDRTC to be powered-down. In this mode, the RTC counter continues to operate. The RTC has the capability to wakeup the device from idle states via alarms, periodic interrupts, or an external WAKEUP input. Additionally, the RTC is able to output an alarm or periodic interrupt on the WAKEUP pin to cause external power management to reenable power to the DSP Core and I/O. 7 Bootloader 7.1 SPI Supports 24-bit Addresses The VC5505 SPI EEPROM boot only supports 16-bit address mode for SPI. The C5505/15 SPI EEPROM boot supports both 16-bit and 24-bit address modes. 7.2 UART Boot no longer supported VC5505 supported UART boot but C5505/15 does not support UART boot. Another boot method must be used. 8 Die ID VC5505 and C5505/15 have Die ID registers that are programmed and used for manufacturing test to uniquely identify each die. Die ID register 3 indicates the silicon revision (DesignRev). The DesignRev bit field of DieID3 register is set to 4 for VC5505 and is set to 5 for C5505/15. Figure 8-1: C5505/15 Die ID Register 3 (DIEIDR3) [0x1C43] 15 14 13 12 11 0 DesignRev[3:0] DIEID3 R, 0101 R, 0 Table 8-1: C5505/15 Die ID Register 3 Bit Field Description Field DesignRev Description Describes the Silicon Revision of Die CPU 0 = Silicon Revision 1.0. 1 = Silicon Revision 1.1. 2 = Silicon Revision 1.2. 3 = Silicon Revision 1.3. 4 = Silicon Revision 1.4. 5 = Silicon Revision 2.0. 10 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 9 Interrupt Aggregation (GPIO, DMA, and Timer) Corrections The below table lists the VC5505 Silicon Errata Issues that have been corrected in C5505/15. Workarounds for these issues in VC5505 can be removed in C5505/15. Table 9-1 Interrupt Aggregation Changes Issue Extra Aggregated Interrupt (GPIO, DMA, and Timer) possible Aggregation Interrupt (GPIO, DMA, and Timer) can be missed VC5505 Errata info SPRZ281B Advisory 1.4.9 SPRZ281B Advisory 1.4.12 C5505/15 Corrected corrected 10 Endianness Corrections In an effort to address the issues in SPRZ281b Advisory 1.4.1 on the VC5505, the C5505/15 endianness has been changed for EMIF, USB, and MMC/SD. Also the word swaps present in DPORT and IPORT were removed. This means that if software swaps were needed on VC5505 to handle the endianness differences some/all of them should be removed on C5505. The section will detail the device level endianness changes. Depending on the use case these changes may be transparent to users of CSL example code. Table 10-1 lists the endianness changes. Reference the block diagrams in Figure 10-1and Figure 10-2 to understand the data path and determine if any software changes are needed to prevent data swaps when migrating from the VC5505 to the C5505/15. Note: If CSL is used, refer to the C55XCSL-LOWPWR 1.0 to 2.x Migration Guide for details. If data is moving back and forth along the same data path, for example from EMIF to CPU DMA to SARAM and from SARAM to CPU DMA to EMIF, then no changes are required between devices. Care should be taken when data is transferred in and out of the C5505/15 as other devices may differ in endianness, and thus, the proper data swapping should be handled in software. The changes on C5505/15 peripheral endianness to all big endian except part of the USB and removal of the IPORT and DPORT word swap should allow any software swaps to be removed. This includes if swaps were used for instruction execution from external memory through EMIF. The USB module CPU access however are still little endian so byte swaps maybe be required when words are transferred between the C5505/15's on-chip memory and the USB module using CPU transfer because of the endianness mismatch. If any software swaps were used for USB DMA access on VC5505 should be removed on C5505/15. An example for the USB data path endianness is provided in Section 10.1 11 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide C55x CPU EMIF USB MMC/SD LCD DPORT IPORT Table 10-1 Endianness Changes from VC5505 to C5505/15 VC5505 C5505/15 Big endian Big endian Configured in hardware as little endian. Configured in hardware as big endian. Core and CDMA are little endian. CDMA is big endian. Core remains little endian. Note: Core register addresses, accessible via XPORT, are offset by one compared to the VC5505. See Table 12-17 for the new addresses. Endianness is software programmable. Endianness is software programmable. Default is little endian. Default is big endian. TI’s bootloader if it reaches the MMC/SD boot will change the endianness back to little endian. Endianness is software programmable, Endianness is software programmable, but default is little endian. This should and default is still little endian. This be changed in software to big endian should be changed in software to big when the LCD controller is configured endian when the LCD controller is if desired. configured if desired. Performs word swap Does not perform word swap Performs word swap Does not perform word swap 12 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Figure 10-1 Block Diagram of the VC5505 Endianness Figure 10-2 Block Diagram of the C5505/15 Endianness 13 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 10.1 C5505/15 USB Data Path Endianness Example Data in the USB module can be read either by the USB module’s CDMA or the CPU XPORT accesses. The USB CDMA accesses on-chip RAM through the MPORT and only performs 32-bit transfers. The USB CDMA handles these transfers in big endian fashion, so no data swap occurs (see Figure 10-3). On the other hand, when the CPU accesses the USB data buffers in the USB Core through its XPORT (ie: when using ‘port’ operand qualifiers), the data is accessed 16-bits at a time in little endian fashion, which results in swaps based on the original data size (see Figure 10-4). For instance, if the original data size was byte, intra-word byte swap will occur. Figure 10-3 DMA Read from USB Module Figure 10-4 CPU Read from USB Module 11 Analog Changes 11.1 Addition of SAR Reset Bit The function of bit 2 of the Peripheral Reset Control Register (PRCR) has changed from reserved in the VC5505 to controlling reset of the SAR ADC in the C5505/15. Writing 1 to the SAR_RST bit resets the SAR module and writing 0 to the bit releases the module out of reset. 14 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Figure 11-1: Peripheral Reset Control Register (PRCR) [0x1C05] 15 8 Reserved R, 0x00 7 6 5 4 3 2 1 0 PG4_RST Reserved PG3_RST DMA_RST USB_RST SAR_RST PG1_RST I2C_RST RW+0 R+0 RW+0 RW+0 RW+0 RW+0 RW+0 RW+0 Table 11-1 Peripheral Reset Control Register (PRCR) bit field description Field SAR_RST Description SAR software reset bit. 0 Reset deasserted, module out of reset 1 Reset asserted, module in reset 11.2 Additional ANA_LDO Supply Pins The VC5505 has three independent LDO input pins: ANA_LDOI, DSP_LDOI, and USB_LDOI but the data sheet states that DSP_LDOI and USB_LDOI must be connected to the same supply as the ANA_LDOI pin. The VC5505’s DSP_LDOI and the USB_LDOI pins are reserved for compatibility with C5514 and C5515, which offer higher integration with 3 on-chip LDOs. In the C5505/15, the three LDO input pins are named LDOI and are internally connected to reduce IR drop and improve manufacturing testability. Thus, in the C5505/15, the three LDOI pins must be connected to the same power source with a voltage range of 1.8V to 3.6V. 11.3 LDO, POR Comparator, and Reset Changes Both VC5505 and C5505/15 have a Power-On-Reset (POR) Comparator circuit that is involved in the generation of the chip’s hardware reset. VC5505 and C5505/15 all support ANA_LDO while C5515 also support two additional integrated LDOs, DSP_LDO and USB_LDO to reduce system level cost and board space. A summary of the LDOs, POR and Reset of each device follows. VC5505 supports one LDO, ANA_LDO. Due to the POR and DSP_LDO performance problems on VC5505, the DSP_LDO is not supported yet it must be enabled to provide the voltage to the POR comparator so the (active-low) chip reset can be de-asserted. The external reset signal on __________ the RESET pin must be provided. C5505 supports one LDO, ANA_LDO. The C5505 does not support the DSP_LDO and device modification allows the DSP_LDO to be disabled which also disables the internal POR. The internal POWERGOOD signal (generated from the POR) is forced high and the external reset __________ signal on the RESET pin is the only source of the device reset. 15 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide The C5515 supports ANA_LDO plus two additional LDOs: DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD).and the USB_LDO which can provide 1.3 V to USB core digital (USB_VDD1P3) and PHY circuit (USB_VDDA1P3). On the C5515, the on-chip DSP_LDO works in conjunction with the RTC-only mode to power up the C5514/5 with an RTC alarm or external wakeup. With the CORE_LDO enabled on C5515, the POR is also enabled and monitors the DSP_LDOO pin (the DSP LDO output pin) voltage and generates and internal POWERGOOD __________ signal. The POWERGOOD signal is ANDed with the external RESET for the device reset. A summary of the differences in pin connection from VC5505 to C5505 to C5515 due to the LDOs are shown in Table 11-2 and added registers for C5515 are shown in Table 11-3. See the C5515 datasheet for more details on the DSP_LDO and USB_LDO including cases where all the three internal LDOs are not enabled. Table 11-2 VC5505 to C5505 to C5515 pin connection changes C5515 connections when Core_LDO and Pin Name VC5505 connections: C5505 connections: USB_LDO are enabled: 5uF - 10uF decoupling a 0.1uF decoupling cap Floating / No cap to VSS DSP_LDOO Supply power to CVDD to VSS Connection pins ________________________ VSS (DSP_LDO Pulled up to LDOI VSS (DSP_LDO DSP _ LDO _ EN enabled) (DSP_LDO disabled) enabled) Internal POWERGOOD __________ External reset must be External reset must ANDed with the RESET provided be provided external reset resets the chip, external reset must be provided This pin D13 is This pin D13 is reserved. Tie to VSS reserved. Tie to VSS or LDOI. or LDOI., the DSP_LDO voltage selection is in a register see DSP_LDO_V ANA_LDOI supply Table 11-3 Floating / No Connection USB_LDOO Floating / No Connection 16 1 uF ~ 2 uF decoupling capacitor to VSS Supplies power to the USB_ VDD1P3, USB_VDDA1P3 pins TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 11-3 VC5505 to C5505 to C5515 register changes Register bit LDOCNTL (0x7004) DSP_LDO_V VC5505: C5505: reserved reserved LDOCNTL (0x7004) USB_LDO_EN reserved reserved RTCPMGT (0x1930) Bit 1 LDO_PD reserved reserved RTCPMGT (0x1930) Bit 2 BG_PD reserved reserved C5515: DSP_LDO voltage select bit 0 DSP_LDOO is regulated to 1.3V 1 DSP_LDOO is regulated to 1.05V USB_LDO enable bit 0 USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state 1 USB LDO output is enabled and regulated to 1.3V On-chip LDOs and Analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog POR 0 On-chip LDOs and Analog POR are enabled. 1 On-chip LDOs and Analog POR are disabled (shutdown). Bandgap, on-chip LDOs, and the analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR, and Bandgap reference. 0 On-chip LDOs, Analog POR, and Bandgap reference are enabled. 1 On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown). 12 Peripheral Changes 12.1 PLL Divider Change and Register Changes On VC5505, it was not possible to divide down the PLL output frequency by a factor of 4. The capability of the output divider allowed for divide-by factors of 1, 2, 8, 10, 12, 14, …, etc, skipping 4 and 6. This divider skip created a gap in the frequencies attainable. The PLL was unable to generate the frequencies from 16 MHz – 23 MHz. To remove the frequency gap on C5505/15, the dividers on the output of the PLL were redesigned. Effectively, in Figure 12-1, the “divide by two” block was removed and the existing “Output Divider” block was replaced with a new one. The new output divider supports divide-by values of: 1, 2, 3, 4, … 128. However, odd divisor values other than divide-by-1 are not recommended due to their negative effect on duty cycle, which can degrade speed performance of the whole chip. 17 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Figure 12-1 VC5505 PLL Block diagram red highlighted areas are removed for C5505/15 Additionally on C5505/15, improvements were made to the organization of bits in the PLL registers to collect the multiplier bit fields in a single PLL register. In VC5505 the multiplier value was calculated as MH[9:0] x 4 + ML[1:0] + 4. C5505/15 simplifies the calculation as M[11:0] + 4 by having all the M bits in the same register. The below tables highlight the register changes for the multiplier and divider bits. Refer to the datasheet for the full register descriptions of the other bits that were not affected. 18 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 12-1: Clock Generator Control Register 1 [0x1C20] Changes from VC5505 to C5505/15 VC5505 C5505/15 Bit name R/W reset Bit name R/W Reset MH[0] RW 0 M[0] RW 0 MH[1] RW 0 M[1] RW 0 MH[2] RW 0 M[2] RW 0 MH [3] RW 0 M[3] RW 0 MH [4] RW 0 M[4] RW 0 MH [5] RW 0 M[5] RW 0 MH [6] RW 0 M[6] RW 0 MH [7] RW 0 M[7] RW 0 MH [8] RW 0 M[8] RW 0 MH [9] RW 0 M[9] RW 0 reserved R 0 M[10] RW 0 Reserved R 0 M[11] RW 0 PLL_PWRDN RW 1 PLL_PWRDN RW 1 PLL_STANDYBY RW 0 PLL_STANDYBY RW 0 Reserved R 0 Reserved R 0 CLR_CNTL RW 0 CLR_CNTL RW 0 19 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-2: Clock Generator Control Register 1 [0x1C20] M bits in C5505/15 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Field Description 0-11 M PLL Multiplier value bits. Multiplier value = M[11:0] + 4 Table 12-3: Clock Generator Control Register 2 [0x1C21] Changes from VC5505 to C5505/15 VC5505 C5505/15 Bit name R/W Reset Bit name R/W reset RDRATIO [0] RW 0 RDRATIO [0] RW 0 RDRATIO [1] RW 0 RDRATIO [1] RW 0 RDRATIO [2] RW 0 RDRATIO [2] RW 0 RDRATIO [3] RW 0 RDRATIO [3] RW 0 RDRATIO [4] RW 0 RDRATIO [4] RW 0 RDRATIO [5] RW 0 RDRATIO [5] RW 0 RDRATIO [6] RW 0 RDRATIO [6] RW 0 RDRATIO [7] RW 0 RDRATIO [7] RW 0 RDRATIO [8] RW 0 RDRATIO [8] RW 0 RDRATIO [9] RW 0 RDRATIO [9] RW 0 RDRATIO [10] RW 0 RDRATIO [10] RW 0 RDRATIO[11] RW 0 RDRATIO[11] RW 0 ML[0] RW 0 Reserved R 0 ML[1] RW 0 Reserved R 0 Reserved R 0 Reserved R 0 RDBYPASS RW 0 RDBYPASS RW 0 Clock Generator Control Register 3 (CGCR3) [0x1C22h] did not change. C5505/15 removes the divide by two output divider and changes the output divider value calculation from ODRATIO[5:0] + 4 to be ODRATIO[7:0] +1. 20 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-4: Clock Generator Control Register 4 [0x1C23] Changes from VC5505 to C5505/15 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VC5505 Bit name R/W ODRATIO[0] RW ODRATIO [1] RW ODRATIO [2] RW ODRATIO [3] RW ODRATIO [4] RW ODRATIO [5] RW reserved R Reserved R OUTDIV2BYPASS RW OUTDIVEN RW reserved R Reserved R reserved R Reserved R reserved R Reserved R reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 Bit name ODRATIO[0] ODRATIO [1] ODRATIO [2] ODRATIO [3] ODRATIO [4] ODRATIO [5] ODRATIO [6] ODRATIO [7] Reserved OUTDIVEN Reserved Reserved reserved Reserved reserved Reserved C5505/15 R/W RW RW RW RW RW RW RW RW R RW R R R R R R reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-5: Clock Generator Control Register 4 [0x1C23] ODRATIO bits that changed in C5505/15 Bit Field Description 0-7 ODRATIO Output divider value bits. Output divider = ODRATIO[7:0] + 1 Table 12-6 VC5505 System Clock Equation [RDBypass, OUTDIVEN, OUTDIV2BYPS] System clock equation bit values 00X MH 2 ML 4 InputClock * RD 4 MH 2 ML 4 1 1 InputClock * * * RD 4 OD 4 2 MH 2 ML 4 1 InputClock * * RD 4 2 InputClock * MH 2 ML 4 1 1 InputClock * [ MH 2 ML 4] * * OD 4 2 1 InputClock * [ MH 2 ML 4] * 2 010 011 10X 110 111 Table 12-7 C5505/15 System Clock Equation [RDBypass, OUTDIVEN] bit values System clock equation 00 M 4 InputClock * RD 4 M 4 1 InputClock * * RD 4 OD 1 InputClock * [ M 4] 1 InputClock * [ M 4] * OD 1 01 10 11 22 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-8 Examples of Selecting PLL Mode Frequency for C5505/15 RDBYPASS OUTDIVEN M RDRATIO ODRATIO PLL output Frequency 1 0 173h x X 32.768KHz x (173h+4) = 12.288 MHz 1 1 E4Ah X 2 32.768KHz x (E4Ah+4)/3 =40.00 MHz 1 0 723h X X 32.768KHz x (723h+4) = 60.00 MHz 1 0 8EDh X X 32.768KHz x (8EDh+4) = 75.01 MHz 1 0 BE8h X X 32.768KHz x (BE7h+4) = 100.01 MHz 1 0 E4Ah X X 32.768KHz x (E4Ah+4) = 120.00 MHz 12.2 RTC Corrections The below table lists the VC5505 Silicon Errata Issues that have been corrected in C5505/15. User can now program the RTC OSCILLATOR DRIFT COMPENSATION REGISTER with any value in the range of 0 to 1024 and remove the workaround for the BCD. Table 12-9 Interrupt Aggregation Changes Issue VC5505 Errata info C5505/15 SPRZ281B Advisory Corrected and maximum RTC Positive Compensation – 1.4.2 allowed compensation value is Multiples of Ten Values Do Not now 1024. Work SPRZ281B Advisory Corrected, 09 updates to 10 RTC BCD Value Error 1.4.10 09 updates to 1A instead of 10 12.3 DMA Corrections and Features Added The below table lists the VC5505 Silicon Errata Issues that have been corrected in C5505/15 as well as two added features for C5505/15 Ping pong mode and auto reload with sync mode support. Details of the DMA Ping Pong Mode are provided in Section 12.3.1 23 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-10 Interrupt Aggregation Changes Issue VC5505 Errata info C5505/15 NA Ping Pong Mode available Ping Pong Mode feature added NA Auto reload with software sync mode (SYNC=0) is supported Auto Reload with SYNC supported added Hardware Event can Trigger DMA Data Transfer in S/W Control Mode SPRZ281B Advisory 1.4.7 In H/W Sync Mode, Auto Reload Bit Overrides Enable Bit SPRZ281B Advisory 1.4.6 Corrected the enable bit now controls the enabling and disabling of the channel in all configurations corrected 12.3.1 Ping Pong Mode Addition and Data Transfer Control Register Changes The DMA Transfer Control Register was changed from VC5505 to C5505/15 to accommodate the addition of Ping-Pong mode. Ping-Pong mode allows the use of two buffers of equal lengths that are rotated through the DMA use. The DMA utilizes the Ping buffer first and when the Ping buffer's transfer length reaches zero, the DMA is automatically reprogrammed to use the Pong buffer. When the Pong buffer's transfer length reaches zero, the DMA is automatically reprogrammed to utilize the Ping buffer. The DMA continues operating between Ping and Pong buffers until the DMA is stopped. The changes are highlighted in red. Bits 0 and 1 of DMACHmTCR2 were previously reserved. Figure 12-2: Transfer Control Register 1 (DMACHmTCR1) 15 0 LENGTH RW, +0 Table 12-11: DMAX Transfer Control Register 1 (DMACHmTCR1) Bit Field Description Field LENGTH Description Size of transfer. For ping-pong mode it is the size of both ping and pong (the entire ping-pong transfer). Valid values are: 0004h - FFFCh These bits specify the number of double 16-bit words (specified in bytes). To be transferred in multiples of (4 x 2BURSTMODE) bytes. Note: These bits are not updated by the channel each time it is serviced by the DMA controller. 24 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Burst Mode These bits specify the number of double word transfers that each channel performs at once before the DMA controller moves on to the active channel. Figure 12-3: Transfer Control Register 2 (DMACHmTCR2) 15 14 13 12 11 10 9 8 7 6 EN Status Interrupt Enable Auto Reload Rsvd DSTA MODE SRCA MODE RW, +0 R+, 0 RW, +0 RW+, 0 R+, 00 RW, +00 RW, +00 5 3 2 1 BURST MODE SYNC MODE Last Transfer Status RW, +000 RW, +0 R+, 0 0 Enable Ping Pong Mode RW, +0 Table 12-12: DMAX Transfer Control Register 2 (DMACHmTCR2) Bit Field Description for bits that changed from VC5505 to C5505/15 Field Last Transfer Status Enable Ping Pong Mode Description Indicates the most recent completed transfer set. This status bit is valid when the Enable Ping Pong Mode bit is set. 0 = Ping set transfer completed. 1 = Pong set transfer completed. Enable ping pong mode – a pong data buffer of length equal to the ping data buffer must be contiguous to the ping buffer. 0 = Ping Pong Mode is disabled. 1 = Ping Pong Mode is enabled. Features associated with the new Ping Pong Mode: 1) The EN bit (enable bit 15 of DMACHmTCR2 register) enables (1) or disables (0) the DMA. When this bit is set the DMA channel goes into active state. The EN bit is reset after the channel completes its transfer (when it is not in auto-reload mode). 2) If a zero is written to the EN bit after it has been enabled, the DMA stops after completing the current burst transfer. The status bit (bit 14 of DMACHmTCR2 register) is updated from the EN bit. If the DMA channel has been stopped during the last burst of the transfer length, the DMA channel completes the transfer as mentioned above but does NOT generate an interrupt (even though the full transfer is essentially completed). The DMA should be reconfigured and re-enabled only after the DMA has completely stopped. Thus, it is necessary to wait for a certain number of clocks according to the configured burst length as mentioned in the C5504/05/14/15 DMA PRG. 3) Ping/Pong Mode Requirements: the user should a. Define a single buffer of size = Transfer Length; the Pong buffer now starts halfway through the buffer. b. Use Ping-Pong mode with interrupts exclusively (polling is not supported) 4) Changing the Enable Ping Pong Mode bit (bit 0 of DMACHmTCR2 register) when the DMA is active is not allowed. 5) If the DMA is enabled with the “Ping Pong Mode Enable” bit set, and: The DMA starts transferring to the Ping buffer. After completion of the transfer, it continues with transferring to the Pong buffer contiguous to the first buffer. a. If Auto Reload bit is set: 25 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide After completing this transfer, the DMA sets Status = 1 and starts transfer from the top of the Ping Buffer again. The DMA resets this bit after it completes the Ping set again. The enable bit remains set throughout the transfers and auto reloads. Interrupts are generated at the end of both the Ping and Pong buffer. b. If Auto Reload bit is NOT set: Stops after Pong set and resets EN bit. 6) Status bit is set when DMA is enabled (DMA should be enabled with valid transfer configuration in all its other registers). The bit stays set through the ping/pong transfer and is reset after the end of the pong transfer. The bit is set again at the start of the next ping transfer/receipt of the first h/w event of the ping transfer if auto reloading. 7) If a DMA channel is enabled in auto-reload mode, writing a zero to the Auto reload bit (bit 12 of DMACHmTCR2 register) during a transfer or even before a transfer begins: a. stops the DMA after the channel has completed transferring the entire frame or transfer length (not just the burst as in 2) above) and generates interrupt when interrupt generation is enabled. b. with Ping/Pong enabled, the channel stops after the pong frame is transferred; interrupts are generated as normal at the end of both ping and pong buffers. c. resets the status bit and EN bit after the DMA is stopped. If this is done in a DMA ISR, the next DMA transfer will already have begun and consequently the DMA will stop after the active transfer. 8) When writing to the enable or auto reload bit during a transfer, the rest of the bits should not be changed. 12.4 EMIF 12.4.1 Endianness Change On VC5505, the EMIF is little endian but the CPU is big endian. This mismatch may create overhead for the software to deal with. Therefore, on C5505/15, the EMIF has been changed to big endian to match the CPU. This is reflected in the EMIF Revision Code and Status Register be value as shown below: Figure 12-4: EMIF Revision Code and Status Register MSW [0x1001] 15 14 13 0 be fr module_id R, +1 R, +1 R, 0x0000 Table 12-13: EMIF Revision Code and Status Register Bit Field Description Field Description be Big endian value, defining endian mode (data R/W order) 0 EMIF is in little endian mode 1 EMIF is in big endian mode 26 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 12.4.2 SDRAM and mSDRAM Support Added The VC5505 does not support mSDRAM or SDRAM. The C5505/15 has added mSDRAM1 and SDRAM1, 2 support. Refer to SPRUGU6 TMSC5504/05/14/15 External Memory Interface (EMIF) User Guide for the details on using SDRAM with the C5505/15 including the configuration registers and refer to the data sheet for the additional pins to support SDRAM. Notes: To save power, the default setting for SDCLK is off. The programmer must enable it by writing a 1 to SDCLK_EN bit in the in the Clock Configuration register 1 (CCR1) 0x1C1E before programming the SDRAM. See Figure 12-5. 1 2 C5505/15 can support non-mobile SDRAM under certain circumstances. C5505/15 always uses mobile SDRAM initialization but it is able to support SDRAM memories that ignore the BA0 and BA1 pins for the 'load mode register' command. During the mobile SDRAM initialization, the device issues the 'load mode register' initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The Extended mode register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and BA1, the second loaded register value overwrites the first; leaving the desired value in the Mode register and the non-mobile SDRAM will work with the C5505/15 device. Figure 12-5: Clock Configuration Register 1 (CCR1) [0x1C1Eh]. 15 0 Reserved SDCLK_EN R, +0 R/W, +0 Table 12-14: EMIF Revision Code and Status Register Bit Field Description Field Description SDCLK_EN SDRAM clock control 0 –SDCLK off 1 – SDCLK on 12.5 I2S Corrections The below table lists the VC5505 Silicon Errata Issues that have been corrected in C5505/15. The workaround can be removed. 27 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Table 12-15 Interrupt Aggregation Changes VC5505 Errata info C5505/15 SPRZ281B Advisory 1.4.3 Corrected Issue Invalid I2S OUERRFL Error Report at First Frame I2S Internal Data Delay SPRZ281B Advisory 1.4.4 invalid data is transmitted during the delay until the true data is sent Zeros are now transmitted during the delay until true data is sent. The delay itself remains the same. 12.6 MMC/SD Default Endianness Change On VC5505, the MMC/SD default setting is little endian mode. In contrast, the C5505/15 MMC/SD default setting is big endian to match the endianness of the CPU. Note that the MMC/SD endianness is software configurable. If TI’s bootloader reaches the MMC/SD boot, it will change the endianness back to little endian. This change in MMC/SD default endianness change is reflected in the MMC Control Register reset value: 15 11 Reserved R, 00000 10 9 8 7 6 PERMDX PERMDR RSV DATEG1 DATEG0 R/W, 1 R/W, 1 R, 0 RW, 0 RW, 0 5 3 2 1 0 Reserved WIDTH0 CMDRST DATRST R, 0 RW, 0 RW+0 RW+0 Figure 12-6: MMCCTL Offset: [0x3A00 and 0x3B00] Field PERMDX PERMDR Table 12-16: MMCCTL Bit Field Description Description Endian select enable when writing 0: Little Endian is selected. 1: Big Endian is selected. Endian select Enable when reading 0: Little Endian is selected. 1: Big Endian is selected. 12.7 USB Endian Changes The VC5505 USB module is little endian. The C5505/15 USB CDMA endianness is changed to big endian to match the CPU endianness but the Core remains as little endian. The USB module’s endianness is hardcoded and cannot be changed through software. Care must be taken that the different endiannesses of the USB modules do not result in an intra-word byte swap. 28 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide Care also needs to be taken when data is transferred in and out of the C5505/15 as other devices may differ in endianness, and thus, the proper data swapping should be handled in software. The change in endianness on C5505/15 resulted in a change in the address of the USB registers in the Core registers (the address is offset by 1) as shown in Table 12-17. Note that these registers can only be written/read via XPORT (refer to Section 10 to for more details on the endian change): VC5505 Address 0x8400 0x8401 0x8404 0x8405 0x8408 0x8409 0x840C 0x840D 0x8410 0x8411 0x8414 0x8415 0x8418 0x841D 0x8420 0x8421 0x8424 0x8425 0x8428 0x8429 0x842C 0x842D 0x8430 0x8431 0x8461 0x8464 Table 12-17: USB Registers Address Changes C5505/15 Address Register Name 0x8401 Function Address Register, Power Management Register 0x8402 Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4 0x8405 Interrupt Register for Receive Endpoints 1 to 4 0x8406 Interrupt enable register for INTRTX 0x8409 Interrupt Enable Register for INTRRX 0x840A Interrupt Register for Common USB Interrupts, Interrupt Enable Register 0x840D Frame Number Register 0x840E Index Register for Selecting the Endpoint Status and Control Registers, Register to Enable the USB 2.0 Test Modes 0x8411 Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to select Endpoints 1-4) 0x8412 Control Status Register for Peripheral Endpoint 0. (Index register set to select Endpoint 0) or Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4) 0x8415 Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to select Endpoints 1-4) 0x8416 Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4) 0x8419 Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) or Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 1- 4) 0x841E Returns details of core configuration. (index register set to select Endpoint 0) 0x8421 Transmit and Receive FIFO Register 1 for Endpoint 0 0x8422 Transmit and Receive FIFO Register 2 for Endpoint 0 0x8425 Transmit and Receive FIFO Register 1 for Endpoint 1 0x8426 Transmit and Receive FIFO Register 2 for Endpoint 1 0x8429 Transmit and Receive FIFO Register 1 for Endpoint 2 0x842A Transmit and Receive FIFO Register 2 for Endpoint 2 0x842D Transmit and Receive FIFO Register 1 for Endpoint 3 0x842E Transmit and Receive FIFO Register 2 for Endpoint 3 0x8431 Transmit and Receive FIFO Register 1 for Endpoint 4 0x8432 Transmit and Receive FIFO Register 2 for Endpoint 4 0x8462 Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4) 0x8465 Transmit Endpoint FIFO Address (Index register set to 29 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide 0x8465 0x8466 0x846C 0x8501 0x8508 0x850D 0x8510 0x846D 0x8502 0x8509 0x850E 0x8511 0x8511 0x8512 0x8514 0x8515 0x8515 0x8516 0x8518 0x8520 0x8519 0x8521 0x8521 0x8522 0x8524 0x8525 0x8525 0x8526 0x8528 0x8530 0x8529 0x8531 0x8531 0x8532 0x8534 0x8535 0x8535 0x8536 0x8538 0x8540 0x8539 0x8541 0x8541 0x8542 0x8544 0x8545 0x8545 0x8546 0x8548 0x8549 select Endpoints 1-4) Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4) Hardware Version Register Control Status Register for Peripheral Endpoint 0 Number of Received Bytes in Endpoint 0 FIFO Returns details of core configuration. Maximum Packet Size for Peripheral/Host Transmit Endpoint 1 Control Status Register for Peripheral Transmit Endpoint 1 (peripheral Mode) Maximum Packet Size for Peripheral/Host Receive Endpoint 1 Control Status Register for Peripheral Receive Endpoint 1 (peripheral mode) Number of Bytes in Host Receive endpoint 1 FIFO Maximum Packet Size for Peripheral/Host Transmit Endpoint 2 Control Status Register for Peripheral Transmit Endpoint 2 (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint 2 Control Status Register for Peripheral Receive Endpoint 2 (peripheral mode) Number of Bytes in Host Receive endpoint 2 FIFO Maximum Packet Size for Peripheral/Host Transmit Endpoint 3 Control Status Register for Peripheral Transmit Endpoint 3 (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint 3 Control Status Register for Peripheral Receive Endpoint 3 (peripheral mode) Number of Bytes in Host Receive endpoint 3 FIFO Maximum Packet Size for Peripheral/Host Transmit Endpoint 4 Control Status Register for Peripheral Transmit Endpoint 4 (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint 4 Control Status Register for Peripheral Receive Endpoint 4 (peripheral mode) Number of Bytes in Host Receive endpoint 4 FIFO 13 References VC5504 technical documents page VC5505 technical documents page 1. 2. 3. TMS320VC5505/VC5504Fixed-Point Digital Signal Processor Silicon Errata (SPRZ281B) VC5504 data sheet (SPRS609B) VC5505 data sheet (SPRS503B) 30 TMS320VC5504/05 to TMS320C5504/05/14/15 Device Migration Guide C5504 technical documents page C5505 technical documents page C5514 technical documents page C5515 technical documents page 4. TMS320C5505/C5504Fixed-Point Digital Signal Processor Silicon Errata (SPRZ310) 5. TMS320C5515/C5514Fixed-Point Digital Signal Processor Silicon Errata (SPRZ308) 6. C5504 data sheet (SPRS659) 7. C5505 data sheet (SPRS660) 8. C5514 data sheet (SPRS646) 9. C5515 data sheet (SPRS645) 10. TMSC5504/05/14/15 External Memory Interface (EMIF) User’s Guide (SPRUGU6C5504/05/14/15) 11. TMSC5504/05/14/15 USB User’s Guide (to be released soon) 12. TMSC5504/05/14/15 DMA User’s Guide (to be released soon) 13. TMS320VC5504/05 to TMS320C5504/05/14/15 Application Migration Guide 14. C55XCSL-LOWPWR 1.0 to 2.x Migration Guide 31