CD22M3494 Data Sheet May 29, 2014 16 x 8 x 1 BiMOS-E Crosspoint Switch Features The Intersil CD22M3494 is an array of 128 analog switches capable of handling signals from DC to video. Because of the switch structure, input signals may swing through the total supply voltage range, VDD to VEE. Each of the 128 switches may be addressed via the ADDRESS input to the 7 to 128 line decoder. The state of the addressed switch is established by the signal to the DATA input. A low or zero input will open the switch, while a high logic level or a one will result in closure of the addressed switch when the STROBE input goes high from its normally low state. Any number or combination of connections may be active at one time. Each connection, however, must be made or broken individually in the manner previously described. All switches may be reset by taking the RESET input from a zero state to a one state and then returning it to its normal low state. • 128 Analog Switches CS allows crosspoint array to be cascaded for matrix expansion. Applications FN2793.8 • Low rON • Guaranteed rON Matching • Analog Signal Input Voltage Equal to the Supply Voltage • Wide Operating Voltage . . . . . . . . . . . . . . . . . . 4V to 15V • Parallel Input Addressing • High Latch-Up Current . . . . . . . . . . . . . . . . . . 50mA (Min) • Very Low Crosstalk • Pin and Functionally Compatible with the Following Types: SGS M3494 and Mitel MT8816 • Pb-Free (RoHS Compliant) • PBX Systems • Instrumentation • Analog and Digital Multiplexers • Video Switching Networks Block Diagram CS STROBE DATA RESET VDD 1 AX0 AX1 AX2 AX3 AY0 AY1 AY2 7 TO 128 DECODER 1 1 LEVEL SHIFTERS LATCHES 128 128 VSS 1 128 VEE 16 X 8 SWITCH ARRAY X0 - X15 Y0 - Y7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2000, 2005, 2006, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. CD22M3494 Ordering Information PART NUMBER (Note 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # CD22M3494EZ CD22M3494EZ -40 to 85 40 Ld PDIP (Note 2) E40.6 CD22M3494MQZ (Note 1) CD22M3494MQZ -40 to 85 44 Ld PLCC (Mitel Ld Compatible) N44.65 CD22M3494MQAZ (Note 1) CD22M3494MQAZ -40 to 85 44 Ld PLCC (Mitel Ld Compatible) N44.65 CD22M3494SQZ (Note 1) CD22M3494SQZ -40 to 85 44 Ld PLCC (SGS Ld Compatible) N44.65 NOTES: 1. Add “96” suffix for tape and reel. At one time the "QZ" and "QAZ" were different products, but since 1994 these parts have been exactly the same. 2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts Y0 1 44 43 42 41 40 DATA 2 Y1 3 Y2 Y3 AX3 4 V DD AX0 5 RESET NC 6 AY2 CS 1 44 43 42 41 40 DATA 2 Y1 3 Y2 4 Y3 5 V DD 6 RESET AX3 38 DATA CD22M3494SQ (PLCC) (SGS LEAD COMPATIBLE) TOP VIEW AY2 40 VDD 39 Y2 AX0 Y3 1 AY2 2 RESET 3 CD22M3494MQ (PLCC) (MITEL LEAD COMPATIBLE) TOP VIEW NC CD22M3494E (PDIP) TOP VIEW AX3 4 AX0 5 X14 6 37 Y1 36 CS 35 Y0 X14 7 39 Y0 X14 7 X15 8 38 NC X15 8 38 NC X15 7 X6 8 34 NC 33 X0 32 X1 X6 9 37 X0 X6 9 37 X0 X7 10 36 X1 X7 10 36 X1 X8 11 35 X2 X8 11 35 X2 31 X2 X9 12 34 X3 X9 12 34 X3 30 X3 X10 13 33 X4 X10 13 33 X4 X10 12 29 X4 X11 14 32 X5 X11 14 32 X5 X11 13 NC 14 28 X5 27 X12 NC 15 31 X12 NC 15 31 X12 NC 16 30 X13 NC 16 30 X13 Y7 15 VSS 16 26 X13 Y7 17 29 NC Y6 17 24 AY0 23 AX2 Submit Document Feedback 29 NC 2 NC AY1 AY0 AX2 Y4 AX1 Y5 Y6 Y7 NC AY1 AY0 AX2 Y4 AX1 V EE Y5 V EE 22 AX1 21 Y4 18 19 20 21 22 23 24 25 26 27 28 STROBE VEE 20 18 19 20 21 22 23 24 25 26 27 28 STROBE STROBE 18 Y5 19 V SS 17 25 AY1 Y6 X9 11 V SS X7 9 X8 10 39 CS FN2793.8 May 29, 2014 CD22M3494 Pin Descriptions 44 LD PLCC PIN NO. 40 LD PDIP PIN NO. SYMBOL MQ SQ DESCRIPTION POWER SUPPLIES VDD 40 44 44 Positive Supply. VSS 16 18 17 Negative Supply (Digital). VEE 20 22 22 Negative Supply (Analog). ADDRESS AX0 - AX3 5, 22, 23 and 4 5, 24, 25 and 4 X Address Lines. These pins select one of the 16 rows of switches. See the Truth Table on page 7 for the valid addresses. AY0 - AY2 24, 25 and 2 26, 27 and 2 Y Address Lines. These pins select one of the 8 columns of switches. See the Truth Table on page 7 for the valid addresses. DATA 38 42 DATA Input determines the state of the addressed switch. A high or one will close the switch. A low or zero will open the switch. STROBE 18 20 STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or zero results in no action. The ADDRESS Input must be stable before the STROBE Input goes to the active high level. The DATA Input must be stable on the failing edge of the STROBE. RESET 3 3 MASTER RESET. A high or one on this line opens all switches. CS 36 CONTROL 40 39 CHIP SELECT. Device is selected when CS is at a high level, allows the crosspoint array to be cascaded for matrix expansion. INPUTS/OUTPUTS X0 - X5 X6 - X11 X12 - X15 Y0 - Y7 I/O 33-28, 8-13, 27, 26, 6, 7 37-32, 9-14, 31, 30, 7, 8 Analog or Digital Inputs/Outputs. These pins are the rows X0 - X15. 35, 37, 39, 1, 21, 39, 41, 43, 1, 23, 40, 41, 43, 1, 23, Analog or Digital Inputs/Outputs. These pins are the columns Y0 - Y7. 19, 17, 15 21, 19, 17 21, 19, 18 Submit Document Feedback 3 FN2793.8 May 29, 2014 CD22M3494 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VDD) Voltages Referenced to VEE . . . . . . . . . . . . . . . . . . . -0.5V to 16V DC Supply Voltage (VDD) Voltages Referenced to VSS . . . . . . . . . . . . . . . . . . . -0.5V to 16V DC Input Diode Current, IIN For VI, Digital < VSS -0.5V or VI, Analog < VEE -0.5V or VI > VDD 0.5V . . . . . . . . . . . . . . . . . ±20mA DC Output Diode Current, IOK For VO, Digital < VSS -0.5V or VO, Analog < VEE -0.5V or VO > VDD 0.5V. . . . . . . . . . . . . . . . . ±20mA DC Transmission Gate Current . . . . . . . . . . . . . . . . . . . . . . . ±25mA Power Dissipation Per Package (Po) For TA = -40°C to +85°C (PDIP). . . . . . . . . . . . . . . . . . . . .500mW For TA = -40°C to +85°C (PLCC) . . . . . . . . . . . . . . . . . . . .600mW Thermal Resistance (Typical, Note 4) JA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Maximum Junction Temperature Plastic Package . . . . . . . . . +150°C Maximum Storage Temperature Range (TSTG). . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Operating Conditions Operating Temperature Range (TA) Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range For TA = Full Package Temperature Range VSS = 0V, VEE = 0V, VDD . . . . . . . . . . . . . . . . . . . . . . . 4V to 15V DC Input or Output Voltage VI or VO . . . . . . . . . . . . . . . VEE to VDD Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = -40°C to +85°C, VDD = 5V, VSS = 0V, VEE = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDD = 5V, Logic Inputs = VDD - - 2 mA VDD = 15V, Logic Inputs = VDD - - 5 mA 2.4 (Note 5) - - V - - 0.8 (Note 5) V - - ±10 (Note 7) µA STATIC CONTROLS Supply Current IDD High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Leakage Current, Digital IIN Electrical Specifications VDD = 5V Reset = Low (Note 6) TA = -40°C to +85°C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDD = 10V - 40 75 VDD = 12V - 36 65 TA = -40°C to +85°C, VDD = 10V VIN = VDD/2, VX -VY = 0.2V, VDD = 12V VSS = VEE = 0V - 50 75 - 45 65 TA = +25°C, VIN = VDD/2, VX - VY = 0.2V, VSS = VEE = 0V, VDD = 12V - 6 10 STATIC CROSSPOINTS ON Resistance rON ON Resistance rON Difference in ON Resistance Between Any Two Switches Submit Document Feedback rON 4 VSS = VEE = 0V, TA = +25°C, VIN = VDD/2, VX - VY = 0.2V FN2793.8 May 29, 2014 CD22M3494 Electrical Specifications TA = -40°C to +85°C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL Difference in ON Resistance Between Any Two Switches rON OFF-State Leakage Current IL Electrical Specifications TEST CONDITIONS MIN TYP MAX UNITS TA = -40°C to +85°C, VIN = VDD/2, VX - VY = 0.2V, VDD = 12V VSS = VEE = 0V, VDD = 12V - - 10 |VX - VY| = 12V - - ±10 (Note 7) µA TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, CL = 50pF, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DYNAMIC CROSSPOINTS Switch I/O Capacitance VIN = VDD/2, f = 1MHz - - 20 pF Switch Feedthrough Capacitance VIN = VDD/2, f = 1MHz - 0.3 - pF - 5 30 ns Propagation Delay Time (Switch ON) Signal Input to Output, tPHL or tPLH Frequency Response Channel ON f = 20log (VX/VY) = -3dB CL = 3pF, RL = 75, VIN = 2VP-P - 50 - MHz Total Harmonic, THD VIN = 2VP-P, f = 1kHz - 0.01 - % Feedthrough Channel OFF Feedthrough = 20log (VX/VY) = FDT VIN = 2VP-P, f = 1kHz - -95 - dB 40dB VIN = 2VP-P, RL = 75 - 10 - MHz 110dB VIN = 2VP-P, RL = 1k || 10pF - 5 - kHz Control Input = 3VP-P Square Wave, tR = tF = 10ns RIN = 1K, ROUT = 10k || 10pF - 75 - mVPEAK Frequency for Signal Crosstalk, fCT Attenuation of: Control Crosstalk DATA-Input, ADDRESS, or STROBE to Output Electrical Specifications TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 5 - pF DYNAMIC CONTROLS Digital Input Capacitance CIN VIN = 5V, f = 1MHz Propagation Delay Time STROBE to Output Switch Turn-ON tPSN - 50 100 ns Switch Turn-OFF tPSF - 50 100 ns Turn-ON to High Level tPZH - 60 100 ns Turn-ON to Low Level tPZL - 70 100 ns Turn-ON to High Level tPAN - 70 - ns Turn-OFF to Low Level tPAF - 70 - ns DATA-IN to Output ADDRESS to Output Submit Document Feedback 5 FN2793.8 May 29, 2014 CD22M3494 Electrical Specifications TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Setup Time CS to STROBE tCS 10 - - ns DATA-IN to STROBE tDS 10 - - ns ADDRESS to STROBE tAS 10 - - ns tCH 10 - - ns 10 - - ns Hold Time STROBE to CS ADDRESS to CS STROBE to DATA-IN tDH 20 - - ns STROBE to ADDRESS tAH 10 - - ns 20 - - ns DATA-IN to CS Pulse Width STROBE tSPW 20 - - ns RESET tRPW 20 - - ns tPHZ - 70 100 ns RESET Turn-OFF to Output Delay NOTES: 5. Operation of VIH at 2.4V or VIL at 0.8V will result in much higher supply current (IDD) than for logic inputs equal to VDD or VSS respectively. 6. Reset IIH < 20µA, Reset = VIH. 7. At +25°C Limit is 100nA. Submit Document Feedback 6 FN2793.8 May 29, 2014 CD22M3494 Timing Diagram tCS CS tCH 50% 50% ADDRESS 50% 50% tAS tSPW STROBE tAH tPSN tPSF 50% tDH tDS DATA 50% 50% tRPW RESET 50% 50% tPAF tPHZ tPZL SWITCH OUTPUT 90% 90% 10% 10% tPZH tPAN TRUTH TABLE X AXIS TRUTH TABLE Y AXIS X ADDRESS AX3 AX2 AX1 Y ADDRESS AX0 X SWITCH AY2 AY1 AY0 Y SWITCH 0 0 0 Y0 0 0 1 Y1 0 1 0 Y2 0 1 1 Y3 1 0 0 Y4 0 0 0 0 X0 0 0 0 1 X1 0 0 1 0 X2 0 0 1 1 X3 0 1 0 0 X4 1 0 1 Y5 0 1 0 1 X5 1 1 0 Y6 0 1 1 0 X12 1 1 1 Y7 0 1 1 1 X13 1 0 0 0 X6 1 0 0 1 X7 1 0 1 0 X8 1 0 1 1 X9 1 1 0 0 X10 1 1 0 1 X11 1 1 1 0 X14 1 1 1 1 X15 Submit Document Feedback 7 FN2793.8 May 29, 2014 CD22M3494 To make a connection (close switch) between any two points, specify an “X” address, a “Y” address, set “DATA” high, and switch “STROBE” from low to high. To break a connection, follow this same procedure with “DATA” low. Example: X ADDRESS Y ADDRESS DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0 To connect switch X3 to switch Y4: 1 0 0 1 1 1 0 0 To connect switch X6 to switch Y7: 1 1 0 0 0 1 1 1 To break connection from X3 to Y4: 0 0 0 1 1 1 0 0 Typical Performance Curve 70 rON vs VIN AT -55°C, +25°C AND +85°C ON RESISTANCE () 60 VEE = -6V, VSS = 0V, VDD = 6V 50 +85°C 40 +25°C 30 -40°C 20 10 0 -8 -6 -4 -2 0 2 4 6 8 VIN (V) For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 8 FN2793.8 May 29, 2014 CD22M3494 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N44.65 (JEDEC MS-018AC ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N 44 44 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. Submit Document Feedback 9 FN2793.8 May 29, 2014 CD22M3494 Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE N E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- A2 SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). Submit Document Feedback 10 FN2793.8 May 29, 2014