ISL22323 Dual Digitally Controlled Potentiometer (XDCP™) Data Sheet August 17, 2015 Low Noise, Low Power, I2C® Bus, 256 Taps FN6422.2 Features • Two potentiometers in one package The ISL22323 integrates two digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the corresponding wiper. At power up the device recalls the contents of the DCP’s IVRi to the correspondent WRi. The ISL22323 also has 13 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22323 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. • 256 resistor taps • I2C serial interface - Three address pins, up to eight devices per bus • Non-volatile EEPROM storage of wiper position • 13 General Purpose non-volatile registers • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T +55°C • Wiper resistance: 70 typical @ 1mA • Standby current <4µA max • Shut-down current <4µA max • Dual power supply - VCC = 2.25V to 5.5V - V- = -2.25V to -5.5V • 10k 50kor 100k total resistance • Extended industrial temperature range: -40 to +125°C • 14 Ld TSSOP or 16 Ld QFN • Pb-free (RoHS compliant) Block Diagram VCC SCL SDA A2 A1 POWER UP INTERFACE, CONTROL AND STATUS LOGIC I2C INTERFACE A0 RH0 V- WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RH1 WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY NON-VOLATILE REGISTERS GND 1 RW0 RL0 RW1 RL1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2008, 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL22323 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING RESISTANCE OPTION (k) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL22323TFV14Z 22323 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL22323TFR16Z 223 23TFRZ 100 -40 to +125 16 Ld QFN L16.4x4A 22323 UFVZ ISL22323UFV14Z (No longer available, recommended replacement: ISL22323TFV14Z-TK) 50 -40 to +125 14 Ld TSSOP M14.173 223 23UFRZ ISL22323UFR16Z (No longer available, recommended replacement: ISL22323TFV14Z-TK) 50 -40 to +125 16 Ld QFN L16.4x4A 22323 WFVZ ISL22323WFV14Z (No longer available, recommended replacement: ISL22323TFV14Z-TK) 10 -40 to +125 14 Ld TSSOP M14.173 223 23WFRZ ISL22323WFR16Z (No longer available, recommended replacement: ISL22323TFV14Z-TK) 10 -40 to +125 16 Ld QFN L16.4x4A NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. Pinouts ISL22323 (16 LD QFN) TOP VIEW RH1 RW0 2 13 A0 16 15 14 13 RW0 3 12 A1 A2 1 12 RL0 RH1 4 11 GND NC 2 11 RH0 RL1 5 10 SCL NC 3 10 VCC RW1 6 9 SDA V- 4 9 A0 A2 7 8 V- 2 5 6 7 8 A1 RL1 RL0 GND 14 VCC SCL 1 SDA RH0 RW1 ISL22323 (14 LD TSSOP) TOP VIEW FN6422.2 August 17, 2015 ISL22323 Pin Descriptions TSSOP PIN QFN PIN SYMBOL 1 11 RH0 “High” terminal of DCP0 2 12 RL0 “Low” terminal of DCP0 3 13 RW0 “Wiper” terminal of DCP0 4 14 RH1 “High” terminal of DCP1 5 15 RL1 “Low” terminal of DCP1 6 16 RW1 “Wiper” terminal of DCP1 7 1 A2 Device address input for the I2C interface 8 4 V- Negative power supply pin 9 5 SDA Open drain Serial data I/O for the I2C interface 10 6 SCL I2C interface clock input 11 7 GND Device ground pin 12 8 A1 Device address input for the I2C interface 13 9 A0 Device address input for the I2C interface 14 10 VCC 2, 3 NC EPAD* DESCRIPTION Positive power supply pin No connection Exposed Die Pad internally connected to V- NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 FN6422.2 August 17, 2015 ISL22323 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP Pin with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V Thermal Resistance (Typical, Note 3) JA (°C/W) JC (°C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . 105 N/A 16 Lead QFN (Note 4) . . . . . . . . . . . . . 39 3.0 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER RHi to RLi Resistance TEST CONDITIONS VRHi, VRLi RW CH/CL/CW (Note 19) ILkgDCP TYP (Note 5) MAX (Note 21) UNIT W option 10 k U option 50 k T option 100 k RHi to RLi Resistance Tolerance End-to-End Temperature Coefficient MIN (Note 21) -20 +20 % W option ±85 ppm/°C U, T option ±45 ppm/°C DCP Terminal Voltage VRH and VRL to GND Wiper Resistance RH - floating, VRL = V-, force Iw current to the wiper, IW = (VCC - VRL)/RTOTAL Potentiometer Capacitance See Macro Model below. Leakage on DCP Pins Voltage at pin from V- to VCC V70 VCC V 250 10/10/25 pF 0.1 1 µA VOLTAGE DIVIDER MODE (V- @ RLi; VCC @ RHi; measured at RWi, unloaded) INL (Note 10) DNL (Note 9) Integral Non-linearity Monotonic Over All Tap Positions Differential Non-linearity Monotonic Over All Tap Positions ZSerror (Note 7) Zero-scale Error FSerror (Note 8) Full-scale Error VMATCH (Note 11, 19) DCP-to-DCP Matching 4 W option -1.5 ±0.5 1.5 LSB (Note 6) U, T option -1.0 ±0.2 1.0 LSB (Note 6) W option -1.0 ±0.4 1.0 LSB (Note 6) U, T option -0.5 ±0.15 0.5 LSB (Note 6) W option 0 1 5 U, T option 0 0.5 2 LSB (Note 6) W option -5 -1 0 U, T option -2 -1 0 Wipers at the same tap position, the same voltage at all RH terminals and the same voltage at all RL terminals -2 2 LSB (Note 6) LSB (Note 6) FN6422.2 August 17, 2015 ISL22323 Analog Specifications SYMBOL Over recommended operating conditions unless otherwise stated. (Continued) PARAMETER TCV (Note 12, Ratiometric Temperature Coefficient 19) fcutoff (Note 19) -3dB Cut Off Frequency TEST CONDITIONS MIN (Note 21) DCP register set to 80 hex TYP (Note 5) MAX (Note 21) UNIT ±4 ppm/°C Wiper at midpoint (80hex) W option (10k) 1000 kHz Wiper at midpoint (80hex) U option (50k) 250 kHz Wiper at midpoint (80hex) T option (100k) 120 kHz RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected) RINL (Note 16) RDNL (Note 15) Roffset (Note 14) RMATCH (Note 17) Integral Non-linearity Differential Non-linearity Offset DCP-to-DCP Matching TCR Resistance Temperature Coefficient (Notes 18, 19) W option -3 ±1.5 3 MI (Note 13) U, T option -1 ±0.4 1 MI (Note 13) W option -1.5 ±0.5 1.5 MI (Note 13) U, T option -0.5 ±0.15 0.5 MI (Note 13) W option 0 1 5 MI (Note 13) U, T option 0 0.5 2 MI (Note 13) Wipers at the same tap position with the same terminal voltages -2 2 MI (Note 13) DCP register set between 32hex and FF hex ±40 ppm/°C Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 IV-1 ICC2 IV-2 PARAMETER VCC Supply Current (Volatile Write/Read) V- Supply Current (Volatile Write/Read) VCC Supply Current (Non-volatile Write/Read) TYP (Note 5) MAX (Note 21) UNIT VCC = 5.5V, fSCL = 400kHz; (for I2C Active, 0.01 0.2 mA VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) 0.005 0.1 mA TEST CONDITIONS MIN (Note 21) Read and Volatile Write states only) V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) -0.2 -0.05 mA V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) -0.1 -0.02 mA VCC = 5.5V, V- = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) 1.0 2.0 mA VCC = 2.25V, V- = -2.25V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) 0.3 1.0 mA V- Supply Current (Non-volatile Write/Read) V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) -2.0 -1.2 mA V- Supply Current (Non-volatile Write/Read) V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) -1.0 -0.4 mA 5 FN6422.2 August 17, 2015 ISL22323 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL ISB IV-SB ISD IV-SB PARAMETER VCC Current (Standby) V- Current (Standby) VCC Current (Shut-down) V- Current (Standby) TYP (Note 5) MAX (Note 21) UNIT VCC = +5.5V, V- = -5.5V @ +85°C, I2C 0.5 2.0 µA VCC = +5.5V, V- = -5.5V @ +125°C, I2C interface in standby state 1.0 4.0 µA VCC = +2.25V, V- = -2.25V @ +85°C, I2C interface in standby state 0.2 1.0 µA VCC = +2.25V, V- = -2.25V @ +125°C, I2C interface in standby state 0.5 2.0 µA TEST CONDITIONS MIN (Note 21) interface in standby state V- = -5.5V, VCC = +5.5V @ +85°C, I2C interface in standby state -3.0 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, I2C interface in standby state -5.0 -1.5 µA V- = -2.25V, VCC = +2.25V @ +85°C, I2C interface in standby state -2.0 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, I2C interface in standby state -3.0 -0.4 µA VCC = +5.5V, V- = -5.5V @ +85°C, I2C interface in standby state 0.5 2.0 µA VCC = +5.5V, V- = -5.5V @ +125°C, I2C interface in standby state 1.0 4.0 µA VCC = +2.25V, V- = -2.25V @ +85°C, I2C interface in standby state 0.2 1.0 µA VCC = +2.25V, V- = -2.25V @ +125°C, I2C interface in standby state 0.5 2.0 µA V- = -5.5V, VCC = +5.5V @ +85°C, I2C interface in standby state -3.0 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, I2C interface in standby state -5.0 -1.5 µA V- = -2.25V, VCC = +2.25V @ +85°C, I2C interface in standby state -2.0 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, I2C interface in standby state -3.0 -0.4 µA Leakage Current, at Pins A0, A1, A2, SDA, and SCL Voltage at pin from GND to VCC tWRT (Note 19) DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to wiper new position 1.5 µs tShdnRec (Note 19) DCP Recall Time from Shut-down Mode SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs Power-on Recall Voltage Minimum VCC at which memory recall occurs ILkgDig Vpor VCCRamp VCC Ramp Rate tD Power-up Delay -1 1.9 1 2.1 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 6 µA V V/ms 5 ms FN6422.2 August 17, 2015 ISL22323 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 21) TYP (Note 5) MAX (Note 21) UNIT EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 20) Temperature T +55°C 1,000,000 Cycles 50 Years Non-volatile Write Cycle Time 12 20 ms 0.3*VCC V SERIAL INTERFACE SPECS VIL A0, A1, A2, SDA, and SCL Input Buffer LOW Voltage VIH A0, A1, A2, SDA, and SCL Input Buffer HIGH Voltage 0.7*VCC V Hysteresis (Note 19) SDA and SCL Input Buffer Hysteresis 0.05*VCC V VOL (Note 19) SDA Output Buffer LOW Voltage, Sinking 4mA Cpin (Note 19) 0.4 V A0, A1, A2, SDA, and SCL Pin Capacitance 10 pF SCL Frequency 400 kHz Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is and SCL Inputs suppressed 50 ns tAA (Note 19) SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window Valid 900 ns tBUF (Note 19) Time the Bus Must be Free Before The SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns tDH (Note 19) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0 ns tR (Note 19) SDA and SCL Rise Time From 30% to 70% of VCC 20 + 0.1*Cb 250 ns tF (Note 19) SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1*Cb 250 ns fSCL tsp 7 0 FN6422.2 August 17, 2015 ISL22323 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 21) TYP (Note 5) MAX (Note 21) UNIT 400 pF Cb (Note 19) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 Rpu (Note 19) SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k~ 2.5k For Cb = 40pF, max is about 15k~ 20k 1 k tSU:A A0, A1, and A2 Setup Time Before START condition 600 ns tHD:A A0, A1, and A2 Hold Time After STOP condition 600 ns NOTES: 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)255 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255 11. VMATCH= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1. Max V RW i – Min V RW i 10 6 12. TC = --------------------------------------------------------------------------------------------- ----------------- for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V Max V RW i + Min V RW i 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 14. ROFFSET = RW0/MI, when measuring between RW and RL. ROFFSET = RW255/MI, when measuring between RW and RH. 15. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255. 16. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255. 17. RMATCH= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1. 6 for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is Max Ri – Min Ri 10 TC R = ---------------------------------------------------------------- ----------------- the minimum value of the resistance over the temperature range. Max Ri + Min Ri 2 +165°C 19. This parameter is not 100% tested. 18. 20. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 8 FN6422.2 August 17, 2015 ISL22323 DCP Macro Model RTOTAL RH RL CL CH CW 10pF 10pF 25pF RW SDA vs SCL Timing tF tHIGH SCL tLOW tsp tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1 and A2 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1, A2 Typical Performance Curves 80 2.0 T = +125°C 1.5 60 STANDBY CURRENT (µA) WIPER RESISTANCE () 70 T = +25°C 50 40 30 T = -40°C 20 10 1.0 ICC 0.5 0 -0.5 IV- -1.0 -1.5 0 0 50 100 150 200 TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W) 9 250 -2.0 -40 0 40 80 120 TEMPERATURE (°C) FIGURE 2. STANDBY ICC and IV- vs TEMPERATURE FN6422.2 August 17, 2015 ISL22323 Typical Performance Curves (Continued) 0.50 0.50 VCC = 5.5V T = +25°C T = +25°C VCC = 2.25V 0.25 INL (LSB) DNL (LSB) 0.25 0 0 -0.25 -0.25 VCC = 5.5V VCC = 2.25V -0.50 -0.50 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 2.0 0 10k -1 1.2 0.8 50k VCC = 2.25V VCC = 5.5V FS ERROR (LSB) ZS ERROR (LSB) 1.6 0.4 VCC = 2.25V 50k VCC = 5.5V -2 -3 10k -4 0 -40 0 40 80 -5 120 -40 0 TEMPERATURE (ºC) 40 80 120 TEMPERATURE (ºC) FIGURE 6. FS ERROR vs TEMPERATURE FIGURE 5. ZS ERROR vs TEMPERATURE 2.0 0.5 T = +25°C T = +25°C VCC = 2.25V 1.0 RINL (MI) RDNL (MI) 1.5 VCC = 5.5V 0.25 0 -0.25 0.5 0 VCC = 2.25V -0.50 0 50 100 VCC = 5.5V 150 200 250 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 10 -0.5 0 50 100 150 200 250 TAP POSITION (DECIMAL) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) FN6422.2 August 17, 2015 ISL22323 Typical Performance Curves (Continued) 200 1.60 10k 160 10k 0.80 TCv (ppm/ºC) RTOTAL CHANGE (%) 1.20 5.5V 0.40 120 80 50k 40 0.00 50k 2.25V 0 -0.40 -40 0 40 80 120 16 66 116 166 216 266 TAP POSITION (DECIMAL) TEMPERATURE (ºC) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE 500 INPUT 400 TCr (ppm/ºC) OUTPUT 10k 300 200 50k 100 0 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10k 16 66 116 166 216 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (1MHz) CS SCL WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h 11 FIGURE 14. LARGE SIGNAL SETTLING TIME FN6422.2 August 17, 2015 ISL22323 loaded into the corresponding WRi to set the wipers to their initial positions. Pin Description Potentiometers Pins DCP Description RHI AND RLi The high (RHi) and low (RLi) terminals of the ISL22323 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWi RWi is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. SERIAL CLOCK (SCL) While the ISL22323 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WRi will be reloaded with the value stored in corresponding non-volatile Initial Value Register (IVRi). This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor. The WRi and IVRi can be read or written to directly using the I2C serial interface as described in the following sections. DEVICE ADDRESS (A2, A1, A0) Memory Description The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22323. A maximum of eight ISL22323 devices may occupy the I2C serial bus (See Table 3). The ISL22323 contains two non-volatile 8-bit Initial Value Register (IVRi), thirteen General Purpose non-volatile 8-bit registers and three volatile 8-bit registers: two Wiper Registers (WRi) and Access Control Register (ACR). Memory map of ISL22323 is in Table 1. The non-volatile registers (IVRi) at address 0 and 1, contain initial wiper position and volatile registers (WRi) contain current wiper position. SDA requires an external pull-up resistor, since it is an open drain input/output. Principles of Operation The ISL22323 is an integrated circuit incorporating two DCPs with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor arrays are comprised of individual resistors connected in a series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and 12 TABLE 1. MEMORY MAP ADDRESS (hex) NON-VOLATILE VOLATILE 10 N/A ACR F Reserved E General Purpose N/A D General Purpose N/A C General Purpose N/A B General Purpose N/A A General Purpose N/A 9 General Purpose N/A 8 General Purpose N/A FN6422.2 August 17, 2015 ISL22323 transmit and receive operations. Therefore, the ISL22323 operates as a slave device in all applications. TABLE 1. MEMORY MAP (Continued) ADDRESS (hex) NON-VOLATILE VOLATILE 7 General Purpose N/A All communication over the I2C interface is conducted by sending the MSB of each byte of data first. 6 General Purpose N/A Protocol Conventions 5 General Purpose N/A 4 General Purpose N/A 3 General Purpose N/A 2 General Purpose N/A Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22323, the SDA pin is in the input mode. 1 IVR1 WR1 0 IVR0 WR0 The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WRi or initial value registers IVRi. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note: value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shut-down mode. When this bit is 0, DCPs are in Shut-down mode. Default value of the SHDN bit is 1. RHi RWi RLi FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22323 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22323 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22323 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (See Table 3). TABLE 3. IDENTIFICATION BYTE FORMAT The WIP bit (ACR[5]) is a read-only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WRi or ACR while WIP bit is 1. I2C Serial Interface LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY 1 The ISL22323 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both 13 (MSB) 0 1 0 A2 A1 A0 R/W (LSB) FN6422.2 August 17, 2015 ISL22323 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 18. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 A C K S A T C O K P A C K 1 0 1 0 A2 A1 A0 1 0 0 0 0 A C K SIGNALS FROM THE SLAVE S T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 19. READ SEQUENCE 14 FN6422.2 August 17, 2015 ISL22323 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22323 responds with an ACK. At this time, the device enters its standby state (See Figure 18). DCP1 programs the gain of the EL8173 from 90 to 110 with 5V output for 10A current through current sense resistor. More application examples can be found at: http://www.intersil.com/data/an/AN1145.pdf The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL22323 responds with an ACK. Then the ISL22323 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The Data Bytes are from the registers indicated by an internal pointer. This pointers initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0Fh, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received.The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (See Figure 19). Applications Information Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients (or overshoot/undershoot) resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note that all switching transients will settle well within the settling time as stated on the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus this may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. Application Example Figure 20 shows an example of using ISL22323 for gain setting and offset correction in high side current measurement application. DCP0 applies a programmable offset voltage of ±25mV to the FB+ pin of the Instrumentation Amplifier EL8173 to adjust output offset to zero voltages. 15 FN6422.2 August 17, 2015 ISL22323 1.2V DC/DC CONVERTER OUTPUT PROCESSOR LOAD 10A, MAX 0.005 10k +5V 10k 0.1µF 8 VS+ 3 IN+ EL8173IS EN 1 VOUT 6 2 INVOUT = 0V TO +5V to ADC 7 FB+ +5V 4 RH1 RH0 RW1 R2 1k, 1% RW0 RL0 50k R4 150k, 1% 5 FB- V S R1 50k, 1% R5 309, 1% RL1 50k DCP1 (1/2 ISL22323U) DCP0 (1/2 ISL22323U) PROGRAMMABLE OFFSET ±25mV PROGRAMMABLE GAIN 90 TO 110 R3 R6 50k, 1% 1.37k, 1% -5V ISL22323UFV14Z +5V I2C BUS 14 10 9 7 12 13 11 -5V 8 VCC SCL SDA A2 A1 A0 RH0 RL0 RW0 RH1 RL1 RW1 1 2 3 DCP0 4 5 6 DCP1 GND V- FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL 16 FN6422.2 August 17, 2015 ISL22323 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 17, 2015 FN6422.2 - Ordering Information Table on page 2. - Added Revision History - Added About Intersil Verbiage. - Updated POD L16.4X4A to latest revision changes are as follow: Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing. Added Typical Recommended Land Pattern. Removed package option. - Updated POD M14.173 to most current version changes are as follow: Updated drawing to remove table and added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. 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No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6422.2 August 17, 2015 ISL22323 Package Outline Drawing L16.4x4A 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 03/15 2.40 4.00 A 4X 1.50 B 6 13 PIN #1 INDEX AREA 16 6 PIN 1 INDEX AREA 12 1 4.00 12X 0.50 2.40 4 9 0.15 (4X) 5 8 TOP VIEW 0.10 M C A B 4 0.25 +0.05 -0.07 16x 0.40±0.01 BOTTOM VIEW SEE DETAIL "X" 0.90±0.10 0.10 C SEATING PLANE C 0.08 C SIDE VIEW (3.8 TYP) ( 2.40) (12x 0.50) C (16x 0.25) (16x 0.60) 0.20 REF 5 +0.03/-0.02 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 18 FN6422.2 August 17, 2015 ISL22323 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN 19 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. FN6422.2 August 17, 2015