ISL22444 ® Quad Digitally Controlled Potentiometer (XDCP™) Data Sheet May 24, 2007 FN6426.0 Low Noise, Low Power, SPI® Bus, 256 Taps Features The ISL22444 integrates four digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. • Four potentiometers in one package The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The wipers position is controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the wiper. At power-up the device recalls the contents of the DCP’s IVRi to the corresponding WRi. • SPI serial interface with write/read capability The ISL22444 also has 11 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22444 features a dual supply that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • 256 resistor taps • Daisy Chain Configuration • Shutdown mode • Non-volatile EEPROM storage of wiper position • 11 General Purpose non-volatile registers • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T ≤ +55°C • Wiper resistance: 70Ω typical @ 1mA • Standby current <4µA max • Shutdown current <4µA max • Dual power supply - VCC = 2.25V to 5.5V - V- = -2.25V to -5.5V • 10kΩ, 50kΩ or 100kΩ total resistance • Extended industrial temperature range: -40 to +125°C • 20 Ld TSSOP or 20 Ld QFN • Pb-free plus anneal product (RoHS compliant) Ordering Information PART NUMBER (Notes 1, 2) PART MARKING RESISTANCE OPTION (kΩ) TEMPERATURE RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22444TFV20Z 22444 TFVZ 100 -40 to +125 20 Ld TSSOP M20.173 ISL22444TFR20Z 22444 TFRZ 100 -40 to +125 20 Ld QFN L20.5x5 ISL22444UFV20Z 22444 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL22444UFR20Z 22444 UFRZ 50 -40 to +125 20 Ld QFN L20.5x5 ISL22444WFV20Z 22444 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL22444WFR20Z 22444 WFRZ 10 -40 to +125 20 Ld QFN L20.5x5 NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “-TK” suffix for 1,000 Tape and Reel option 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22444 Block Diagram VCC VRH3 RW3 WR3 SCK SDI SPI INTERFACE SDO CS POWER-UP, CONTROL AND STATUS LOGIC RL3 RH2 RW2 WR2 RL2 RH1 RW1 WR1 RL1 RH0 NON-VOLATILE REGISTERS RW0 WR0 RL0 GND Pinouts ISL22444 (20 LEAD QFN) TOP VIEW RH3 1 20 RW0 RL3 RH3 RW0 RL0 RH0 ISL22444 (20 LEAD TSSOP) TOP VIEW RL3 2 19 RL0 20 19 18 17 16 RW3 3 18 RH0 NC 4 17 V- RW3 1 15 V- NC 2 14 VCC SCK 3 13 SDI SCK 5 16 VCC SDO 6 15 SDI GND 7 14 CS RW2 8 13 RH1 SDO 4 12 CS RL2 9 12 RL1 GND 5 11 RH1 RH2 10 2 6 7 8 9 10 RW2 RL2 RH2 RW1 RL1 11 RW1 FN6426.0 May 24, 2007 ISL22444 Pin Descriptions TSSOP PIN QFN PIN SYMBOL 1 19 RH3 “High” terminal of DCP3 2 20 RL3 “Low” terminal of DCP3 3 1 RW3 “Wiper” terminal of DCP3 4 2 NC 5 3 SCK SPI interface clock input 6 4 SDO Data Output of the SPI serial interface 7 5 GND Device ground pin 8 6 RW2 “Wiper” terminal of DCP2 9 7 RL2 “Low” terminal of DCP2 10 8 RH2 “High” terminal of DCP2 11 9 RW1 “Wiper” terminal of DCP1 12 10 RL1 “Low” terminal of DCP1 13 11 RH1 “High” terminal of DCP1 14 12 CS Chip Select active low input 15 13 SDI Data Input of the SPI serial interface 16 14 VCC Positive power supply pin 17 15 V- Negative power supply pin 18 16 RH0 “High” terminal of DCP0 19 17 RL0 “Low” terminal of DCP0 20 18 RW0 “Wiper” terminal of DCP0 EPAD* DESCRIPTION No connection Exposed Die Pad internally connected to V- * Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 FN6426.0 May 24, 2007 ISL22444 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V Thermal Resistance (Typical, Note 3) θJA (°C/W) 20 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER RHi to RLi resistance TEST CONDITIONS MIN RW CH/CL/CW (Note 20) ILkgDCP UNIT 10 kΩ U option 50 kΩ T option VRH, VRL MAX W option RHi to RLi resistance tolerance End-to-End Temperature Coefficient TYP (NOTE 4) 100 -20 kΩ +20 % W option ±85 ppm/°C U, T option ±45 ppm/°C DCP terminal voltage VRHi and VRLi to GND Wiper resistance RH - floating, VRL = V-, force Iw current to the wiper, IW = (VCC - VRL)/RTOTAL Potentiometer capacitance See “DCP Macro Model” on page 8. Leakage on DCP pins Voltage at pin from V- to VCC V70 VCC V 250 Ω 10/10/25 pF 0.1 1 µA VOLTAGE DIVIDER MODE (V- @ RLi; VCC @ RHi; measured at RWi, unloaded) INL (Note 9) DNL (Note 8) Integral non-linearity Differential non-linearity W option -1.5 ±0.5 1.5 LSB (Note 5) U, T option -1.0 ±0.2 1.0 LSB (Note 5) Monotonic over all tap positions, W option -1.0 ±0.4 1.0 LSB (Note 5) U, T option -0.5 ±0.15 0.5 LSB (Note 5) 0 1 5 LSB (Note 5) ZSerror (Note 6) Zero-scale error W option U, T option 0 0.5 2 FSerror (Note 7) Full-scale error W option -5 -1 0 U, T option -2 -1 0 VMATCH (Note 10) DCP to DCP matching Wipers at the same tap position, the same voltage at all RH terminals and the same voltage at all RL terminals -2 TCV Ratiometric temperature coefficient (Note 11, 20) 4 DCP register set to 80 hex 2 ±4 LSB (Note 5) LSB (Note 5) ppm/°C FN6426.0 May 24, 2007 ISL22444 Analog Specifications SYMBOL fcutoff (Note 20) Over recommended operating conditions unless otherwise stated. (Continued) PARAMETER TEST CONDITIONS -3dB cut off frequency MIN Wiper at midpoint (80hex) W option (10k) TYP (NOTE 4) MAX 1000 UNIT kHz Wiper at midpoint (80hex) U option (50k) 250 kHz Wiper at midpoint (80hex) T option (100k) 120 kHz RESISTOR MODE (Measurements between RWi and RL i with RHi not connected, or between RWi and RHi with RLi not connected) RINL (Note 15) RDNL (Note 14) Roffset (Note 13) RMATCH (Note 16) Integral non-linearity Differential non-linearity Offset DCP to DCP matching TCR Resistance temperature coefficient (Note 17, 20) W option -3 ±1.5 3 MI (Note 12) U, T option -1 ±0.4 1 MI (Note 12) W option -1.5 ±0.5 1.5 MI (Note 12) U, T option -0.5 ±0.15 0.5 MI (Note 12) W option 0 1 5 MI (Note 12) U, T option 0 0.5 2 MI (Note 12) Wipers at the same tap position with the same terminal voltages -3 3 MI (Note 12) DCP register set between 32 hex and FFhex ±40 ppm/°C Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 IV-1 ICC2 IV-2 ISB PARAMETER VCC Supply Current (volatile write/read) V- Supply Current (volatile write/read) VCC Supply Current (non-volatile write/read) TYP (NOTE 4) MAX UNIT VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.6 1.0 mA VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.25 0.5 mA TEST CONDITIONS MIN V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) -1.0 -0.3 mA V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) -0.5 -0.1 mA VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 1.0 2.0 mA VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 0.3 1.0 mA V- Supply Current (non-volatile write/read) V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) -2.0 -1.2 mA V- Supply Current (non-volatile write/read) V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) -1.0 -0.4 mA VCC Current (standby) VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface in standby state 0.5 2.0 µA VCC = +5.5V, V- = -5.5V @ +125°C, SPI interface in standby state 1.0 4.0 µA VCC = +2.25V, V- = -2.25V @ +85°C, SPI interface in standby state 0.2 1.0 µA VCC = +2.25V, V- = -2.25V @ +125°C, SPI interface in standby state 0.5 2.0 µA 5 FN6426.0 May 24, 2007 ISL22444 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL IV-SB ISD IV-SD ILkgDig PARAMETER V- Current (standby) VCC Current (shutdown) V- Current (shutdown) TEST CONDITIONS MIN TYP (NOTE 4) V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface in standby state -4.0 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, SPI interface in standby state -5.0 -1.5 µA V- = -2.25V, VCC = +2.25V @ +85°C, SPI interface in standby state -2.0 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, SPI interface in standby state -3.0 -0.4 µA MAX UNIT VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface in standby state 0.5 2.0 µA VCC = +5.5V, V- = -5.5V @ +125°C, SPI interface in standby state 1.0 4.0 µA VCC = +2.25V, V- = -2.25V @ +85°C, SPI interface in standby state 0.2 1.0 µA VCC = +2.25V, V- = -2.25V @ +125°C, SPI interface in standby state 0.5 2.0 µA V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface in standby state -4.0 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, SPI interface in standby state -5.0 -1.5 µA V- = -2.25V, VCC = +2.25V @ +85°C, SPI interface in standby state -2.0 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, SPI interface in standby state -3.0 -0.4 µA Leakage current, at pins SCK, SDI, Voltage at pin from GND to VCC SDO and CS -1 1 µA tWRT (Note 20) DCP wiper response time CS rising edge to wiper new position 1.5 µs tShdnRec (Note 20) DCP recall time from shutdown mode CS rising edge to wiper stored position and RH connection 1.5 µs Power-on recall voltage Minimum VCC at which memory recall occurs Vpor VCCRamp VCC ramp rate tD 1.9 2.1 0.2 Power-up delay V V/ms 5 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance Temperature T ≤ +55ºC EEPROM Retention tWC (Note 18) 1,000,000 Cycles 50 Non-volatile Write Cycle time Years 12 20 ms 0.3*VCC V SERIAL INTERFACE SPECIFICATIONS VIL SCK, SDI, and CS input buffer LOW voltage VIH SCK, SDI, and CS input buffer HIGH voltage 0.7*VCC V Hysteresis SCK, SDI, and CS input buffer hysteresis 0.05*VCC V VOL SDO output buffer LOW voltage IOL = 4mA for Open Drain output, pull-up voltage Vpu = VCC SDO pull-up resistor off-chip Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz Rpu (Note 19) 6 0 0.4 V 2 kΩ FN6426.0 May 24, 2007 ISL22444 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL Cpin (Note 20) PARAMETER TEST CONDITIONS MIN SCK, SDI, SDO and CS pin capacitance TYP (NOTE 4) MAX UNIT 10 pF fSCK SPI frequency tCYC SPI clock cycle time 200 ns tWH SPI clock high time 100 ns tWL 5 MHz SPI clock low time 100 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SDI, SCK and CS input setup time 50 ns tH SDI, SCK and CS input hold time 50 ns tRI SDI, SCK and CS input rise time 10 ns tFI SDI, SCK and CS input fall time 10 20 ns tDIS SDO output Disable time 0 100 ns tSO SDO output setup time 50 ns tV SDO output valid time 150 ns tHO SDO output hold time tRO SDO output rise time Rpu = 2k, Cbus = 30pF tFO SDO output fall time Rpu = 2k, Cbus = 30pF tCS CS deselect time 0 ns 60 ns 60 ns 2 µs NOTES: 4. Typical values are for TA = +25°C and 3.3V supply voltage. 5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 – VCC]/LSB. 8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 9. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 255 10. VMATCH= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3, y = 0 to 3. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 11. TC = --------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 255 decimal, T = -40°C to +125°C. Max ( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 14. RDNL = (RWi – RWi-1)/MI -1, for i = 1 to 255. 15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 255. 16. RMATCH= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 3, y = 0 to 3. 6 [ Max ( Ri ) – Min ( Ri ) ] 10 17. for i = 16 to 255, T = -40°C to +125°C. Max ( ) is the maximum value of the resistance and Min ( ) TC R = ---------------------------------------------------------------- × ----------------[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 +165°C is the minimum value of the resistance over the temperature range. 18. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 19. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 20. This parameter is not 100% tested. 7 FN6426.0 May 24, 2007 ISL22444 DCP Macro Model RTOTAL RH CL CH CW 10pF RL 10pF 25pF RW Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tSU tH ... tWH tWL tRI tFI ... MSB SDI tLAG LSB HIGH IMPEDANCE SDO Output Timing CS SCK ... tSO tHO tDIS ... MSB SDO LSB tV SDI ADDR XDCP Timing (for All Load Instructions) CS tWRT SCK SDI ... MSB ... LSB VW SDO HIGH IMPEDANCE 8 FN6426.0 May 24, 2007 ISL22444 Typical Performance Curves 80 2.0 T = +125ºC 1.5 60 STANDBY CURRENT (µA) WIPER RESISTANCE (Ω) 70 T = +25ºC 50 40 30 T = -40ºC 20 10 1.0 ICC 0.5 0 -0.5 IV-1.0 -1.5 0 0 50 100 150 200 -2.0 -40 250 0 TAP POSITION (DECIMAL) 40 80 120 TEMPERATURE (°C) FIGURE 2. STANDBY ICC and IV- vs TEMPERATURE FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) 0.50 0.50 VCC = 5.5V T = +25ºC T = +25ºC VCC = 2.25V 0.25 INL (LSB) DNL (LSB) 0.25 0 0 -0.25 -0.25 VCC = 5.5V VCC = 2.25V -0.50 -0.50 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 2.0 0 10k -1 1.2 0.8 50k VCC = 2.25V VCC = 5.5V 0.4 0 -40 FS ERROR (LSB) ZS ERROR (LSB) 1.6 VCC = 2.25V 50k VCC = 5.5V -2 -3 10k -4 0 40 80 TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE 9 120 -5 -40 0 40 80 120 TEMPERATURE (ºC) FIGURE 6. FS ERROR vs TEMPERATURE FN6426.0 May 24, 2007 ISL22444 Typical Performance Curves (Continued) 0.5 2.0 T = +25ºC T = +25ºC VCC = 5.5V 1.5 VCC = 2.25V 1.0 RINL (MI) RDNL (MI) 0.25 0 0.5 -0.25 0 VCC = 2.25V VCC = 5.5V -0.50 0 50 100 150 200 -0.5 250 0 50 TAP POSITION (DECIMAL) 100 150 200 250 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 200 1.60 10k 160 10k 0.80 TCv (ppm/ºC) RTOTAL CHANGE (%) 1.20 5.5V 0.40 120 80 50k 40 0.00 50k 2.25V 0 -0.40 -40 0 40 80 120 16 66 116 166 216 266 TAP POSITION (DECIMAL) TEMPERATURE (ºC) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE 500 INPUT TCr (ppm/ºC) OUTPUT 10k 400 300 200 50k 100 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10kΩ 0 16 66 116 166 216 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 10 FIGURE 12. FREQUENCY RESPONSE (1MHz) FN6426.0 May 24, 2007 ISL22444 Typical Performance Curves (Continued) CS SCL WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h Pin Description FIGURE 14. LARGE SIGNAL SETTLING TIME shifted in at the rising edge of the serial clock SCK, while the CS input is low. Potentiometer Pins CHIP SELECT (CS) RHI AND RLI The high (RHi) and low (RLi) terminals of the ISL22444 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for PushPull or Open Drain operation. Default setting for this pin is Push-Pull. An external pull up resistor is required for Open Drain output operation. Note: the external pull up voltage not allowed beyond VCC. SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI remote host device. The data bits are 11 CS LOW enables the ISL22444, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22444 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. Principles of Operation The ISL22444 is an integrated circuit incorporating four DCPs with their associated registers, non-volatile memory and the SPI serial interface providing direct communication between host, potentiometers and memory. The resistor arrays are comprised of individual resistors connected in a series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the content of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial position. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP FN6426.0 May 24, 2007 ISL22444 contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0]= FFh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. The non-volatile registers (IVRi) at address 0, 1, 2 and 3 contain initial wiper position and volatile registers (WRi) contain current wiper position. While the ISL22444 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WRi will be reloaded with the value stored in a non-volatile Initial Value Register (IVRi). All the IVRs are factory programmed with 80h. The VOL bit (ACR[7]) determines whether the access to wiper registers WRi or initial value registers IVRi. The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections. If VOL bit is 0, the non-volatile IVRi and General Purpose registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note: value that is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. Memory Description The ISL22444 contains four non-volatile 8-bit Initial Value Registers (IVRi), eleven non-volatile 8-bit General Purpose (GP) registers, four volatile 8-bit Wiper Registers (WRi), and volatile 8-bit Access Control Register (ACR). The memory map of ISL22444 is in Table 1. TABLE 1. MEMORY MAP ADDRESS (hex) NON-VOLATILE VOLATILE 10 N/A ACR F The register at address 0Fh is a read-only reserved register. Information read from this register should be ignored. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # BIT NAME 7 6 5 VOL SHDN WIP 4 3 2 1 0 0 0 0 SDO 0 The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, DCP is in Shutdown mode, i.e. each DCP is forced to end-to-end open circuit and RWi is shorted to RLi as shown on Figure 15. Default value of SHDN bit is 1. RHi Reserved E General Purpose N/A D General Purpose N/A C General Purpose N/A RWi RLi FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE B General Purpose N/A A General Purpose N/A 9 General Purpose N/A 8 General Purpose N/A 7 General Purpose N/A 6 General Purpose N/A 5 General Purpose N/A 4 General Purpose N/A 3 IVR3 WR3 2 IVR2 WR2 1 IVR1 WR1 The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push - Pull output. SDO pin can be configured as Open Drain output for some application. In this case, an external pull up resistor is required. See “Applications Information” on page 14. 0 IVR0 WR0 SPI Serial Interface Setting SHDN bit to 1 is returned wipers to prior to Shutdown Mode position. The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write or read to the WRi or ACR while WIP bit is 1. The ISL22444 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out 12 FN6426.0 May 24, 2007 ISL22444 Write Operation on the falling edge of SCK. CS must be LOW during communication with the ISL22444. SCK and CS lines are controlled by the host or master. The ISL22444 operates only as a slave device. A Write operation to the ISL22444 is a two or more bytes operation. First, It requires, the CS transition from HIGH to LOW. Then host must send a valid Instruction Byte followed by one or more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. Instruction is executed on rising edge of CS. For a write-to address 00h, 01h, 02h or 03h, the MSB of the byte at address 10h (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to “Memory Description” and Figure 16. Note: the internal non-volatile write cycle starts with the rising edge of CS and requires up to 20ms. During non-volatile write cycle the read operation to ACR register is allowed to check WIP bit. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. Protocol Conventions The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL22444 is the Data Byte. TABLE 3. INSTRUCTION BYTE FORMAT Read Operation BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 A Read operation to the ISL22444 is a four byte operation. It requires first, the CS transition from HIGH to LOW. Then the host must send a valid Instruction Byte followed by “dummy” Data Byte, a NOP Instruction Byte and another “dummy” Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on rising edge of SCK during third and fourth bytes respectively. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). Reading from the IVRi will not change the WRi, if its contents are different. Table 4 contains a valid instruction set for ISL22444. There are only sixteen register addresses possible for this DCP. If the [R4:R0] bits are 00000, 00001, 00010 or 00011 then the read or write is to either the IVRi or the WRi registers (depends of VOL bit at ACR). If the [R4:R0] are 10000, then the operation is on the ACR. TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRITE 1 0 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR READ 1 1 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR WRITE where X means “do not care”. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 16. TWO BYTE WRITE SEQUENCE 13 FN6426.0 May 24, 2007 ISL22444 CS 1 8 16 24 32 SCK SDI RD NOP ADDR RD SDO ADDR READ DATA FIGURE 17. FOUR BYTE READ SEQUENCE Applications Information Communicating with ISL22444 Communication with ISL22444 proceeds using SPI interface through the ACR (address 10000b), IVRi (address 00000b, 00001b, 00010b or 00011b), WRi (addresses 00000b, 00001b, 00010b or 00011b) and General Purpose registers (addresses from 00100b to 01110b). The wiper position of each potentiometer is controlled by the corresponding WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 10000b to 1 (ACR[7] = 1). The non-volatile IVRi stores the power up position of the wiper. IVRi is accessible when MSB bit at address 10000b is set to 0 (ACR[7] = 0). Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different. Daisy Chain Configuration When application needs more then one ISL22444, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown on Figure 18. In Daisy Chain configuration the SDO pin of previous chip is connected to SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of SCK and CS pins of microcontroller; for larger number of SPI devices buffering of SCK and CS lines is required. Daisy Chain Write Operation The write operation starts by HIGH to LOW transition on CS line, followed by N two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown on Figure 19. The serial data is going through DCPs from DCP0 14 to DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. Daisy Chain Read Operation The read operation consists of two parts: first, send read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown on Figure 20 and Figure 21. The first part starts by HIGH to LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW to HIGH transition on CS line. The read instructions are executed during second part of read sequence. It also starts by HIGH to LOW transition on CS line, followed by N two bytes NOP instructions on SDI line and LOW to HIGH transition of CS. The data is read on every even byte during second part of read sequence while every odd byte contains instruction code + address from which the data is being read. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note, that all switching transients will settle well within the settling time as stated on the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN6426.0 May 24, 2007 ISL22444 N DCP IN A CHAIN CS SCK DCP0 MOSI MISO µC DCP1 DCP2 CS CS CS SCK SCK SCK SDI SDO SDI SDO SDI DCP(N-1) CS SCK SDO SDI SDO FIGURE 18. DAISY CHAIN CONFIGURATION CS SCK 16 CLKLS WR SDI 16 CLKS 16 CLKS D C P2 SDO 0 WR D C P1 WR D C P0 WR D C P2 WR D C P1 WR D C P2 SDO 1 SDO 2 FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR SDO DATA IN DATA OUT FIGURE 20. TWO BYTE OPERATION 15 FN6426.0 May 24, 2007 ISL22444 CS SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS 16 CLKS 16 CLKS 16 CLKS RD DCP0 NOP NOP NOP DCP2 OUT DCP1 OUT DCP0 OUT SDO FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP Application Example Figure 22 shows an example of using ISL22444 for gain setting and offset correction in a high side current measurement application. DCP0 applies a programmable offset voltage of ±25mV to the FB+ pin of the Instrumentation Amplifier ISL28272 to adjust output offset to zero voltages. DCP1 programs the gain of the ISL28272 from 90 to 110 with 5V output for 10A current through current sense resistor. DCP2 and DCP3 are used for another channel of dual ISL28272 correspondently (not shown in Figure 22). More application examples can be found at http://www.intersil.com/data/an/AN1145.pdf 16 FN6426.0 May 24, 2007 ISL22444 1.2V DC/DC CONVERTER OUTPUT PROCESSOR LOAD 10A, MAX 0.005Ω 10k +5V 10k 0.1µF 16 V+ 6 IN+ 1/2 ISL28272 EN 7 VOUT 2 5 INVOUT = 0V to + 5V to ADC 3 FB+ +5V 8 RH1 RH0 RL0 R5 309, 1% RW1 R2 1k, 1% RW0 50k R4 150k, 1% 4 FB- V- R1 50k, 1% 50k RL1 DCP1 (1/4 ISL22444U) DCP0 (1/4 ISL22444U) PROGRAMMABLE OFFSET ±25mV PROGRAMMABLE GAIN 90 TO 110 R3 R6 50k, 1% 1.37k, 1% -5V ISL22444UFV20Z +5V SPI BUS 16 5 6 15 14 4 7 -5V 17 Vcc SCK SDO SDI CS NC GND V- RH0 RL0 RW0 RH1 RL1 RW1 RH2 RL2 RW2 RH3 RL3 RW3 18 19 20 DCP0 13 12 11 DCP1 10 9 8 DCP2 1 2 3 DCP3 FIGURE 22. CURRENT SENSING WITH GAIN AND OFFSET CONTROL 17 FN6426.0 May 24, 2007 ISL22444 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.5x5 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - 0.02 0.05 - A2 - 0.65 1.00 9 0.38 5, 8 A3 b 0.20 REF 0.23 0.30 9 D 5.00 BSC - D1 4.75 BSC 9 D2 2.95 E E1 E2 3.10 3.25 7, 8 5.00 BSC - 4.75 BSC 2.95 e 3.10 9 3.25 7, 8 0.65 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 9 θ - - 12 9 Rev. 4 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the "b" dimension. 18 FN6426.0 May 24, 2007 ISL22444 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M E1 2 INCHES SYMBOL 3 0.05(0.002) -A- 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE GAUGE PLANE -B1 M20.173 B M 0.25 0.010 SEATING PLANE L A D -C- α e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N α 20 0o 20 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 1 6/98 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN6426.0 May 24, 2007