ISL21009MEP ® Data Sheet December 15, 2008 FN6744.0 High Voltage Input Precision, Low Noise FGA™ Voltage References Features The ISL21009MEP FGA™ voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil’s proprietary Floating Gate Analog technology. The ISL21009MEP features very low noise (4.5µVP-P for 0.1Hz to 10Hz), low operating current (180µA, Max), and 3ppm/°C of temperature drift. In addition, the ISL21009 family features guaranteed initial accuracy as low as ±0.5mV. • Full Mil-Temp Electrical Performance from -55°C to +125°C This combination of high initial accuracy, low power and low output noise performance of the ISL21009MEP enables versatile high performance control and data acquisition applications with low power consumption. • Enhanced Process Change Notification • Specifications per DSCC VID V62/08629 • Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site • Full Homogeneous Lot Processing in Wafer Fab • No Combination of Wafer Fabrication Lots in Assembly • Full Traceability Through Assembly and Test by Date/Trace Code Assignment • Enhanced Obsolescence Management • Eliminates Need for Up-Screening a COTS Component • Output Voltages . . . . . . . . . . . . . . 2.500V, 4.096V, 5.000V Device Information The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Supply Center in Columbus (DSCC). “Hot-links” to the applicable VID and other supporting application information are provided on our website. • Initial Accuracy . . . . . . . . . . . . . . . . . . . . .±0.5mV, ±1.0mV • Input Voltage Range. . . . . . . . . . . . . . . . . . . 3.5V to 16.5V • Output Voltage Noise . . . . . . . . .4.5µVP-P (0.1Hz to 10Hz) • Supply Current . . . . . . . . . . . . . . . . . . . . . . . .180µA (Max) • Temperature Coefficient . . . . . . . . . . . . 3ppm/°C, 5ppm/°C Available Options • Output Current Capability. . . . . . . . . . . . . . . Up to ±7.0mA • Operating Temperature Range. . . . . . . . . -55°C to +125°C VOUT OPTION (V) INITIAL ACCURACY (mV) TEMPCO. (ppm/°C) ISL21009BMB825EP 2.500 ±0.5 3 Applications ISL21009CMB825EP 2.500 ±1.0 5 • Defense/Commercial Avionics ISL21009BMB841EP 4.096 ±0.5 3 ISL21009BMB850EP 5.000 ±0.5 3 ISL21009CMB850EP 5.000 ±1.0 5 PART NUMBER • Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC • Radar/Sonar Systems • Signal Processing Applications Pinout ISL21009MEP (8 LD SOIC) TOP VIEW 1 GND or NC 1 8 DNC VIN 2 7 DNC DNC 3 6 VOUT GND 4 5 TRIM or NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL21009MEP Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 GND or NC 2 VIN 4 GND Ground connection 5 TRIM Allows user trim typically ±2.5%. Leave unconnected when unused. 6 VOUT Voltage reference output connection 3, 7, 8 DNC Do Not Connect; Internal connection – must be left floating Can be either Ground or No Connect Power supply input connection Ordering Information PART NUMBER (Note 1) PART MARKING VOUT OPTION (V) GRADE TEMP. RANGE (°C) PKG. DWG. # PACKAGE ISL21009BMB825EP 21009BM 25EP 2.500 ±0.5mV, 3ppm/°C -55 to +125 8 Ld SOIC M8.15 ISL21009CMB825EP 21009CM 25EP 2.500 ±1.0mV, 5ppm/°C -55 to +125 8 Ld SOIC M8.15 ISL21009BMB841EP 21009BM 41EP 4.096 ±0.5mV, 3ppm/°C -55 to +125 8 Ld SOIC M8.15 ISL21009BMB850EP 21009BM 50EP 5.000 ±0.5mV, 3ppm/°C -55 to +125 8 Ld SOIC M8.15 ISL21009CMB850EP 21009CM 50EP 5.000 ±1.0mV, 5ppm/°C -55 to +125 8 Ld SOIC M8.15 NOTE: 1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 1 +5V 2 C1 10µF 3 4 GND NC VIN NC NC VOUT GND NC 8 7 6 5 ISL21009-25EP SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK CS A0 CLR A1 VCC A2 VH SI VL SO RDY VREF VSS UP VOUT DOWN VBUF OE VFB 20 19 18 17 16 C1 0.001µF 15 14 13 12 LOW NOISE DAC OUTPUT 11 FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUB-RANGING DAC 2 FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100kΩ) 140 120 UNIT 1 UNIT 2 120 IIN (µA) 100 IIN (µA) +125°C +25°C 110 80 UNIT 3 60 100 -40°C 40 90 20 0 3.5 5.5 7.5 9.5 11.5 13.5 80 3.5 15.5 5.5 7.5 VIN (V) 15.5 100 UNIT 2 ΔVOUT (mV) NORMALIZED TO VIN = 5.5V VOUT (V) (NORMALIZED TO 2.50V AT VIN = 5V) 13.5 FIGURE 3. IIN vs VIN, 3 TEMPERATURES 2.50010 2.50005 2.50000 UNIT 3 UNIT 1 2.49995 2.49990 2.49985 2.49980 3.50 5.50 7.50 9.50 11.5 VIN (V) 13.5 0.1 -55°C 50 0 +25°C -50 +125°C -100 -150 -200 3.5 15.5 5.5 7.5 9.5 11.5 13.5 15.5 VIN (V) FIGURE 5. LINE REGULATION OVER-TEMPERATURE FIGURE 4. LINE REGULATION 2.5002 +125°C UNIT 3 2.5001 0.05 2.5000 2.4999 +25°C VOUT (V) ΔVOUT (mV) NORMALIZED TO VIN = 5.5V 11.5 VIN (V) FIGURE 2. IIN vs VIN, 3 UNITS 0 9.5 -0.05 2.4998 UNIT 2 2.4997 2.4996 -0.1 UNIT 1 2.4995 -55°C 2.4994 -0.15 -7 -5 SINKING -3 -1 1 3 OUTPUT CURRENT (mA) FIGURE 6. LOAD REGULATION 3 5 SOURCING 7 2.4993 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 7. VOUT vs TEMPERATURE FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100kΩ) (Continued) 0 500kHz PEAK VIN (DC) = 10V -10 -20 NO LOAD PSRR (dB) -30 -40 -50 -60 10nF -70 1nF 100nF -80 -90 -100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD VIN AND VOUT (V) FIGURE 8. PSRR AT DIFFERENT CAPACITIVE LOADS 5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 VIN HIGH IIN MEDIUM IIN LOW IIN 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 TIME (ms) FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE FIGURE 11. TURN-ON TIME GAIN IS x1000, NOISE IS 4.5µVP-P 160 140 10nF 2mV/DIV ZOUT (Ω) 120 1nF 100 NO LOAD 80 60 100nF 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) FIGURE 12. ZOUT vs FREQUENCY 4 100k 1M FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100kΩ) (Continued) NO OUTPUT CAPACITANCE NO OUTPUT CAPACITANCE 7mA +50µA -50µA -7mA FIGURE 14. LOAD TRANSIENT RESPONSE FIGURE 15. LOAD TRANSIENT RESPONSE Typical Performance Curves (ISL21009-41EP) (REXT = 100kΩ) 110 100 105 95 +25°C UNIT 3 IIN (µA) IIN (µA) 100 95 UNIT 2 -40°C 90 +125°C 90 85 UNIT 1 85 80 5 7 9 11 13 15 80 17 5 7 9 13 15 17 VIN (V) VIN (V) FIGURE 16. IIN vs VIN, 3 UNITS FIGURE 17. IIN vs VIN, 3 TEMPERATURES 200 4.0963 ΔVOUT (mV) NORMALIZED TO VIN = 5.5V VOUT (V) NORMALIZED TO 4.096V AT VIN = 5.0V 11 4.0962 4.0962 4.0961 UNIT 1 4.0961 UNIT 2 UNIT 3 4.0960 4.0960 4.0959 4.0959 4.0958 4.50 6.50 8.50 10.5 VIN (V) 12.5 14.5 FIGURE 18. LINE REGULATION, 3 UNITS 5 16.5 150 100 +25°C -55°C 50 0 -50 -100 4.5 +125°C 6.5 8.5 10.5 12.5 14.5 16.5 VIN (V) FIGURE 19. LINE REGULATION OVER-TEMPERATURE FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-41EP) (REXT = 100kΩ) VOUT (V) NORMALIZED TO 4.096V ΔVOUT (mV) NORMALIZED TO VIN = 5.5V 0.6 0.5 0.4 0.3 0.2 +25°C 0.1 0.0 -0.1 -0.2 -7 -55°C +125°C -6 -5 -4 SINKING -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4 5 6 7 (Continued) 4.0970 4.0965 4.0960 UNIT 2 4.0955 UNIT 3 4.0950 4.0945 -40 UNIT 1 -25 -10 SOURCING 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) FIGURE 21. VOUT vs TEMPERATURE FIGURE 20. LOAD REGULATION 0 VIN (DC) = 5V -10 -20 PSRR (dB) NO LOAD VIN (AC) RIPPLE = 50mVP-P 100nF LOAD -30 -40 10nF LOAD -50 -60 -70 1nF LOAD X = 10µs/DIV Y = 200mV/DIV -80 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 22. PSRR AT DIFFERENT CAPACITIVE LOADS FIGURE 23. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD VIN VREF X = 50µs/DIV Y = 2V/DIV X = 10µs/DIV Y = 200mV/DIV FIGURE 24. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE 6 FIGURE 25. TURN-ON TIME FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-41EP) (REXT = 100kΩ) (Continued) GAIN IS x10,000 NOISE IS 4.5µVP-P 200 180 160 ZOUT ( Ω) 20mV/DIV 1nF LOAD 140 120 NO LOAD 100 80 60 10nF LOAD 40 20 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 1s/DIV FIGURE 26. ZOUT vs FREQUENCY FIGURE 27. VOUT NOISE, 0.1Hz TO 10Hz 7mA +50µA -50µA -7mA NO OUTPUT CAPACITANCE X = 5µs/DIV Y = 50mV/DIV FIGURE 28. LOAD TRANSIENT RESPONSE 7 NO OUTPUT CAPACITANCE X = 5µs/DIV Y = 500mA/DIV FIGURE 29. LOAD TRANSIENT RESPONSE FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100kΩ) 140 110 UNIT3 UNIT2 120 100 80 IIN (µA) IIN (µA) 100 +25°C UNIT1 60 +125°C 90 40 -40°C 20 80 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 0 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) VIN (V) FIGURE 31. IIN vs VIN, 3 TEMPERATURES 5.0001 ΔVOUT (mV) NORMALIZED TO VIN = 5.5V 100 5.0000 4.9999 4.9998 UNIT2 4.9997 4.9996 UNIT1 4.9995 UNIT3 4.9994 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) 50 0 -50 -100 +25°C -55°C +125°C -150 -200 -250 -300 -350 -400 5.5 FIGURE 32. LINE REGULATION 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) FIGURE 33. LINE REGULATION OVER-TEMPERATURE 0.10 ΔVOUT (mV) NORMALIZED TO VIN = 5.5V VOUT (V) (NORMALIZED TO 5.0V AT VIN = 10V) FIGURE 30. IIN vs VIN, 3 UNITS 0.05 0 +25°C -55°C -0.05 -0.10 +125°C -0.15 -0.20 -7 -6 -5 -4 SINKING -3 -2 -1 0 1 2 OUTPUT CURRENT (mA) 3 4 5 6 7 SOURCING FIGURE 34. LOAD REGULATION 8 FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100kΩ) 5.001 0 NORMALIZED TO +25°C 5.001 5.000 NO LOAD -10 VIN (DC) = 10V -20 VIN (AC) RIPPLE = 50mVP-P -30 UNIT 1 UNIT 2 PSRR (dB) VOUT (V) (Continued) 5.000 4.999 -40 -50 -60 10nF -70 100nF -80 4.999 UNIT 3 4.998 -40 -20 1nF -90 0 20 40 60 80 100 120 -100 1 140 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) TEMPERATURE (°C) FIGURE 35. VOUT vs TEMPERATURE FIGURE 36. PSRR AT DIFFERENT CAPACITIVE LOADS VIN = 10V VIN = 10V DVIN = 1V DVIN = 1V FIGURE 37. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD FIGURE 38. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE 12 120 10 100 VIN 8 6 ZOUT (W) VIN (V) AND VOUT (V) 1nF 450nA 4 60 NO LOAD 40 2 0 80 270nA 0 50 100 150 200 TIME (µs) FIGURE 39. TURN-ON TIME 9 10nF 20 340nA 250 300 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 40. ZOUT vs FREQUENCY FN6744.0 December 15, 2008 ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100kΩ) (Continued) GAIN IS x1000 NOISE IS 4.5µVP-P 2mV/DIV 50µA -50µA FIGURE 41. VOUT NOISE, 0.1Hz TO 10Hz FIGURE 42. LOAD TRANSIENT RESPONSE 7mA -7mA FIGURE 43. LOAD TRANSIENT RESPONSE Applications Information FGA Technology The ISL21009MEP voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics, which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections. Micropower Operation The ISL21009MEP consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 95µA and noise is 4.5µVP-P benefitting precision, low noise portable applications such as handheld meters and instruments. Data Converters in particular can utilize the ISL21009MEP as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise. The process used for these reference devices is a floating gate CMOS process and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While 10 FN6744.0 December 15, 2008 ISL21009MEP Board Mounting Considerations Turn-On Time For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package, which will subject the die to mild stresses when the PC board is heated and cooled, slightly changing the shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. The ISL21009MEP devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 100µs. This is shown in Figure 11. Circuit design must take this into account when looking at power-up delays or sequencing. Noise Performance and Reduction The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4.5µVP-P. The noise measurement is made with a bandpass filter made of a 1-pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40µVP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1-pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10x the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21009MEP is not designed to drive heavily capactive loads, so for load capacitances above 0.001µF, the noise reduction network shown in Figure 44 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to 1MHz using this network with a 0.01µF capacitor and a 2kΩ resistor in series with a 10µF capacitor. Also, transient response is improved with higher value output capacitor. The 0.01µF value can be increased for better load transient response with little sacrifice in output stability. Temperature Coefficient The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH – VLOW), and divide by the temperature extremes of measurement (THIGH – TLOW). The result is divided by the nominal reference voltage (at T = +25°C) and multiplied by 106 to yield ppm/°C. This is the “Box” method for specifying temperature coefficient. Output Voltage Adjustment The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from VOUT to GND and connecting the wiper to the TRIM pin. The TRIM input is high impedance so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/°C) and the resulting voltage divider should have very low tempco <5ppm/°C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications. . VIN = 5.0V 10µF 0.1µF VIN VO ISL21009-25EP GND 2kΩ 0.01µF 10µF FIGURE 44. HANDLING HIGH LOAD CAPACITANCE 11 FN6744.0 December 15, 2008 ISL21009MEP Typical Application Circuits VIN = +5.0V R = 200Ω 2N2905 VIN VOUT ISL21009MEP VOUT = 2.50V GND 2.5V/50mA 0.001µF FIGURE 45. PRECISION 2.5V, 50mA REFERENCE +3.5V TO 16.5V 0.1µF 10µF VIN VOUT ISL21009-25EP VOUT = 2.50V GND 0.001µF VCC RH VOUT X9119 (UNBUFFERED) + SDA 2-WIRE BUS EL8178 SCL VSS – VOUT (BUFFERED) RL FIGURE 46. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE 12 FN6744.0 December 15, 2008 ISL21009MEP Typical Application Circuits (Continued) +3.5V TO 16.5V 0.1µF 10µF VIN EL8178 + VOUT VOUT SENSE – ISL21009-25EP LOAD GND FIGURE 47. KELVIN SENSED LOAD 10µF +3.5V TO 16.5V 0.1µF VIN 2.5V ±2.5% VOUT ISL21009-25EP TRIM GND VCC I2C BUS RH SDA SCL ISL95810 VSS RL FIGURE 48. OUTPUT ADJUSTMENT USING THE TRIM PIN 13 FN6744.0 December 15, 2008 ISL21009MEP Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N a NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6744.0 December 15, 2008