ISL21009 ® Data Sheet September 16, 2009 High Voltage Input Precision, Low Noise FGA™ Voltage References The ISL21009 FGA™ voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil’s proprietary Floating Gate Analog technology. The ISL21009 features very low noise (4.5µVP-P for 0.1Hz to 10Hz), low operating current (180µA, Max), and 3ppm/°C of temperature drift. In addition, the ISL21009 family features guaranteed initial accuracy as low as ±0.5mV. This combination of high initial accuracy, low power and low output noise performance of the ISL21009 enables versatile high performance control and data acquisition applications with low power consumption. Available Options FN6327.7 Features • Output Voltages . . . . . . . .1.250V, 2.500V, 4.096V, 5.000V • Initial Accuracy . . . . . . . . . . . . . .±0.5mV, ±1.0mV, ±2.0mV • Input Voltage Range. . . . . . . . . . . . . . . . . . . 3.5V to 16.5V • Output Voltage Noise . . . . . . . . .4.5µVP-P (0.1Hz to 10Hz) • Supply Current . . . . . . . . . . . . . . . . . . . . . . . .180µA (Max) • Temperature Coefficient . . . 3ppm/°C, 5ppm/°C, 10ppm/°C • Output Current Capability. . . . . . . . . . . . . . . Up to ±7.0mA • Operating Temperature Range. . . . . . . . . -40°C to +125°C • Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC • Pb-Free (RoHS Compliant) Applications • High Resolution A/Ds and D/As VOUT OPTION (V) INITIAL ACCURACY (mV) TEMPCO. (ppm/°C) ISL21009BFB812Z 1.250 ±0.5 3 ISL21009CFB812Z 1.250 ±1.0 5 ISL21009DFB812Z 1.250 ±2.0 10 • Battery Management/Monitoring ISL21009BFB825Z 2.500 ±0.5 3 • Industrial/Instrumentation Equipment ISL21009CFB825Z 2.500 ±1.0 5 Pinout ISL21009DFB825Z 2.500 ±2.0 10 ISL21009BFB841Z 4.096 ±0.5 3 ISL21009CFB841Z 4.096 ±1.0 5 ISL21009DFB841Z 4.096 ±2.0 10 GND OR NC 1 8 DNC ISL21009BFB850Z 5.000 ±0.5 3 VIN 2 7 DNC ISL21009CFB850Z 5.000 ±1.0 5 DNC 3 6 VOUT ISL21009DFB850Z 5.000 ±2.0 10 GND 4 5 TRIM OR NC PART NUMBER 1 • Digital Meters • Bar Code Scanners • Basestations ISL21009 (8 LD SOIC) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL21009 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 GND or NC 2 VIN Power Supply Input Connection 4 GND Ground Connection 5 TRIM or NC 6 VOUT 3, 7, 8 DNC Can be either Ground or No Connect Allows user trim typically ±2.5%. Leave Unconnected when unused. Voltage Reference Output Connection Do Not Connect; Internal Connection – Must Be Left Floating Ordering Information PART NUMBER (Notes 1, 2) PART MARKING VOUT OPTION (V) GRADE TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL21009BFB812Z 21009BF Z12 1.250 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009CFB812Z 21009CF Z12 1.250 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009DFB812Z 21009DF Z12 1.250 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009BFB825Z 21009BF Z25 2.500 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009CFB825Z 21009CF Z25 2.500 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009DFB825Z 21009DF Z25 2.500 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009BFB841Z 21009BF Z41 4.096 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009CFB841Z 21009CF Z41 4.096 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009DFB841Z 21009DF Z41 4.096 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009BFB850Z 21009BF Z50 5.000 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009CFB850Z 21009CF Z50 5.000 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15 ISL21009DFB850Z 21009DF Z50 5.000 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2 FN6327.7 September 16, 2009 ISL21009 1 +5V 2 C1 10µF 3 4 GND NC VIN NC NC VOUT NC GND 8 7 6 5 ISL21009-25 SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK CS A0 CLR A1 VCC A2 VH SI VL SO RDY VREF VSS UP VOUT DOWN VBUF OE VFB 20 19 18 17 16 C1 0.001µF 15 14 13 12 LOW NOISE DAC OUTPUT 11 FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUB-RANGING DAC 3 FN6327.7 September 16, 2009 ISL21009 Absolute Voltage Ratings Thermal Information Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . -0.5V to VOUT +1V Voltage on “DNC” pins . . . . No connections permitted to these pins. ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-free Reflow Profile (Note 4). . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . -40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. Post-reflow drift for the ISL21009 devices will range from 100µV to 1.0mV based on experimental results with devices tested in sockets and also on FR4 multi-layer PC boards. The design engineer must take this into account when considering the reference voltage after assembly. Common Electrical Specifications (ISL21009-12, -25, -41, -50) TA = -40°C to +125°C, IOUT = 0, unless otherwise specified. PARAMETER VOA TC VOUT DESCRIPTION VOUT Accuracy @ TA = +25°C Output Voltage Temperature Coefficient (Note 5) IIN Supply Current ΔVOUT / VOUT Trim Range ISC Short Circuit Current tR CONDITIONS MIN TYP MAX UNIT ISL21009B -0.5 +0.5 mV ISL21009C -1.0 +1.0 mV ISL21009D -2.0 +2.0 mV ISL21009B 3 ppm/°C ISL21009C 5 ppm/°C ISL21009D 10 ppm/°C 180 µA 95 ±2.0 ±2.5 % TA = +25°C, VOUT tied to GND 10 mA Turn-on Settling Time VOUT = ±0.1% 100 µs Ripple Rejection f = 10kHz 60 dB eN Output Voltage Noise 0.1Hz ≤ f ≤ 10Hz 4.5 µVP-P VN Broadband Voltage Noise 10Hz ≤ f ≤ 1kHz 2.2 µVRMS Electrical Specifications (ISL21009-12, VOUT = 1.250V) VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0, unless otherwise specified. PARAMETER DESCRIPTION VOUT Output Voltage VIN Input Voltage Range ΔVOUT/ΔVIN Line Regulation ΔVOUT/ΔIOUT CONDITIONS MIN TYP MAX 1.250 Load Regulation 3.5 UNIT V 16.5 V 3.5V < VIN < 5.5V 50 150 µV/V 5.5V < VIN < 16.5V 10 50 µV/V Sourcing: 0mA ≤ IOUT ≤ 7mA 10 50 µV/mA Sinking: -7mA ≤ IOUT ≤ 0mA 20 100 µV/mA ΔVOUT/ΔTA Thermal Hysteresis (Note 6) ΔTA = +165°C 50 ppm ΔVOUT/Δt Long Term Stability (Note 7) TA = +25°C 50 ppm 4 FN6327.7 September 16, 2009 ISL21009 Electrical Specifications (ISL21009-25, VOUT = 2.50V) PARAMETER DESCRIPTION VOUT Output Voltage VIN Input Voltage Range ΔVOUT/ΔVIN Line Regulation ΔVOUT/ΔIOUT VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0, unless otherwise specified. CONDITIONS MIN TYP MAX 2.500 Load Regulation 3.5 UNIT V 16.5 V 3.5V < VIN < 5.5V 50 150 µV/V 5.5V < VIN < 16.5V 10 50 µV/V Sourcing: 0mA ≤ IOUT ≤ 7mA 10 50 µV/mA Sinking: -7mA ≤ IOUT ≤ 0mA 20 100 µV/mA ΔVOUT/ΔTA Thermal Hysteresis (Note 6) ΔTA = +165°C 50 ppm ΔVOUT/Δt Long Term Stability (Note 7) TA = +25°C 50 ppm Electrical Specifications (ISL21009-41, VOUT = 4.096V) PARAMETER DESCRIPTION VIN = 5.0V, TA = -40°C to +125°C, IOUT = 0 unless otherwise specified. CONDITIONS VOUT Output Voltage VIN Input Voltage Range ΔVOUT/ΔVIN Line Regulation 4.5V < VIN < 16.5V ΔVOUT/ΔIOUT Load Regulation MIN TYP MAX 4.096 4.5 UNIT V 16.5 V 50 200 µV/V Sourcing: 0mA ≤ IOUT ≤ 5mA 20 100 µV/mA Sinking: -5mA ≤ IOUT ≤ 0mA 20 150 µV/mA ΔVOUT/ΔTA Thermal Hysteresis (Note 6) ΔTA = +165°C 50 ppm ΔVOUT/Δt Long Term Stability (Note 7) TA = +25°C 50 ppm Electrical Specifications (ISL21009-50, VOUT = 5.0V) PARAMETER DESCRIPTION VIN = 10.0V, TA = -40°C to +125°C, IOUT = 0 unless otherwise specified. CONDITIONS VOUT Output Voltage VIN Input Voltage Range ΔVOUT/ΔVIN Line Regulation 5.5V < VIN < 16.5V ΔVOUT/ΔIOUT Load Regulation MIN TYP MAX 5.000 5.5 UNIT V 16.5 V 20 90 µV/V Sourcing: 0mA ≤ IOUT ≤ 7mA 10 100 µV/mA Sinking: -7mA ≤ IOUT ≤ 0mA 20 150 µV/mA ΔVOUT/ΔTA Thermal Hysteresis (Note 6) ΔTA = +165°C 50 ppm ΔVOUT/Δt Long Term Stability (Note 7) TA = +25°C 50 ppm NOTES: 5. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40°C to +125°C = +165°C. 6. Thermal Hysteresis is the change of VOUT measured @ TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled from +25°C to +125°C to -40°C to +25°C. 7. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/√(1kHrs). 5 FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-12) (REXT = 100kΩ) 100 110 105 95 +25°C 100 IIN (µA) IIN (µA) UNIT 3 95 UNIT 2 -40°C 90 +125°C 90 85 UNIT 1 85 80 80 5 7 9 11 13 15 17 5 7 9 FIGURE 2. IIN vs VIN, 3 UNITS UNIT 2 20 0 UNIT 3 -20 -40 5.5 7.5 9.5 11.5 13.5 (NORMALIZED TO VIN = 5.0V) 40 ΔVOUT (µV) ΔVOUT (µV) NORMALIZED TO VIN = 5V 15 17 60 UNIT 1 -60 3.5 +25°C 40 20 -40°C 0 -20 +125°C -40 -60 -80 -100 3.5 15.5 5.5 7.5 VIN (V) VOUT (V) NORMALIZED TO 1.250V 0.06 0.04 +25°C -40°C +125°C 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -6 -5 SINKING -4 -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) FIGURE 6. LOAD REGULATION 6 11.5 13.5 15.5 FIGURE 5. LINE REGULATION OVER-TEMPERATURE 0.08 0.02 9.5 VIN (V) FIGURE 4. LINE REGULATION, 3 UNITS ΔVOUT (mV) 13 FIGURE 3. IIN vs VIN, 3 TEMPERATURES 60 -0.12 -7 11 VIN (V) VIN (V) 4 5 6 SOURCING 7 1.25020 1.25015 UNIT 1 UNIT 2 1.25010 1.25005 1.25000 1.24995 UNIT 3 1.24990 1.24985 1.24980 -40 -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 7. VOUT vs TEMPERATURE, 3 UNITS FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-12) (REXT = 100kΩ) (Continued) X = 10µs/DIV Y = 200mV/DIV 0 500kHz PEAK VIN (DC) = 10V -10 -20 NO LOAD PSRR (dB) -30 -40 -50 -60 10nF -70 100nF -80 1nF -90 -100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 8. PSRR AT DIFFERENT CAPACITIVE LOADS FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD X = 5µs/DIV Y = 20mV/DIV VIN VREF X = 100µs/DIV Y = 1V/DIV FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE FIGURE 11. TURN-ON TIME GAIN IS x1000, NOISE IS 4.5µVP-P 200 180 160 1nF LOAD 120 2mV/DIV ZOUT ( Ω) 140 NO LOAD 100 80 60 10nF LOAD 40 20 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 12. ZOUT vs FREQUENCY 7 FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-12) (REXT = 100kΩ) X = 5µs/DIV Y = 50mV/DIV (Continued) X = 10µs/DIV Y = 500mV/DIV +7mA +50µA -50µA -7mA FIGURE 14. LOAD TRANSIENT RESPONSE FIGURE 15. LOAD TRANSIENT RESPONSE Typical Performance Curves (ISL21009-25) (REXT = 100kΩ) 140 120 UNIT 1 UNIT 2 120 IIN (µA) 100 IIN (µA) +125°C +25°C 110 80 UNIT 3 60 100 -40°C 40 90 20 0 3.5 5.5 7.5 9.5 11.5 13.5 80 3.5 15.5 5.5 7.5 VIN (V) 13.5 15.5 FIGURE 17. IIN vs VIN, 3 TEMPERATURES 2.50010 60 UNIT 2 2.50005 2.50000 ΔVOUT (µV) UNIT 3 UNIT 1 2.49995 2.49990 2.49985 5.50 7.50 9.50 11.5 VIN (V) FIGURE 18. LINE REGULATION 8 13.5 15.5 (NORMALIZED TO VIN = 5.0V) VOUT (V) (NORMALIZED TO 2.50V AT VIN = 5V) 11.5 VIN (V) FIGURE 16. IIN vs VIN, 3 UNITS 2.49980 3.50 9.5 40 +25°C 20 -40°C 0 -20 +125°C -40 -60 -80 -100 3.5 5.5 7.5 9.5 11.5 VIN (V) 13.5 15.5 FIGURE 19. LINE REGULATION OVER-TEMPERATURE FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-25) (REXT = 100kΩ) 0.10 2.5002 0.08 2.5001 0.06 2.5000 0.04 UNIT 3 2.4999 +125°C 0.02 VOUT (V) ΔVOUT (mV) (Continued) -40°C 0.00 -0.02 2.4998 UNIT 2 2.4997 2.4996 -0.04 +25°C -0.06 UNIT 1 2.4995 2.4994 -0.08 -0.10 -7 -6 -5 -4 -3 SINKING -2 -1 0 1 2 3 4 OUTPUT CURRENT (mA) 5 6 7 2.4993 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) SOURCING FIGURE 20. LOAD REGULATION FIGURE 21. VOUT vs TEMPERATURE 0 -10 -20 500kHz PEAK VIN (DC) = 10V NO LOAD PSRR (dB) -30 -40 -50 -60 10nF -70 100nF -80 1nF -90 -100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 23. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD VIN AND VOUT (V) FIGURE 22. PSRR AT DIFFERENT CAPACITIVE LOADS 5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 VIN HIGH IIN MEDIUM IIN LOW IIN 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 TIME (ms) FIGURE 24. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE 9 FIGURE 25. TURN-ON TIME FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-25) (REXT = 100kΩ) (Continued) GAIN IS x1000, NOISE IS 4.5µVP-P 160 140 10nF 2mV/DIV ZOUT (Ω) 120 1nF 100 NO LOAD 80 60 100nF 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 26. ZOUT vs FREQUENCY FIGURE 27. VOUT NOISE, 0.1Hz TO 10Hz NO OUTPUT CAPACITANCE NO OUTPUT CAPACITANCE 7mA +50µA -50µA -7mA FIGURE 28. LOAD TRANSIENT RESPONSE FIGURE 29. LOAD TRANSIENT RESPONSE Typical Performance Curves (ISL21009-41) (REXT = 100kΩ) 100 110 105 95 +25°C UNIT 3 IIN (µA) IIN (µA) 100 95 UNIT 2 -40°C 90 +125°C 90 85 UNIT 1 85 80 5 7 9 11 13 VIN (V) FIGURE 30. IIN vs VIN, 3 UNITS 10 15 17 80 5 7 9 11 13 15 17 VIN (V) FIGURE 31. IIN vs VIN, 3 TEMPERATURES FN6327.7 September 16, 2009 ISL21009 300 4.0962 250 4.0962 4.0961 UNIT 2 UNIT 1 4.0961 UNIT 3 4.0960 4.0960 4.0959 200 150 100 +125°C +25°C -40°C 50 0 -50 -100 4.0959 -150 4.0958 4.5 6.5 8.5 10.5 VIN (V) 12.5 14.5 -200 4.5 16.5 FIGURE 32. LINE REGULATION, 3 UNITS VOUT (V) NORMALIZED TO 4.096V 0.05 0.00 -0.05 +25°C -40°C +125°C -0.10 -0.15 -0.20 -7 -6 -5 -4 -3 SINKING -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4 6.5 8.5 10.5 VIN (V) 12.5 14.5 16.5 FIGURE 33. LINE REGULATION OVER-TEMPERATURE 0.10 ΔVOUT (mV) (Continued) 4.0963 ΔVOUT (µV) NORMALIZED TO VIN = 5.0V VOUT (V) NORMALIZED TO 4.096V AT VIN = 5.0V Typical Performance Curves (ISL21009-41) (REXT = 100kΩ) 5 6 7 SOURCING FIGURE 34. LOAD REGULATION 4.0970 4.0965 4.0960 UNIT 2 4.0955 UNIT 3 4.0950 4.0945 -40 UNIT 1 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) FIGURE 35. VOUT vs TEMPERATURE 0 VIN (DC) = 5V -10 -20 PSRR (dB) NO LOAD VIN (AC) RIPPLE = 50mVP-P 100nF LOAD -30 -40 10nF LOAD -50 -60 -70 1nF LOAD -80 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 36. PSRR AT DIFFERENT CAPACITIVE LOADS 11 X = 10µs/DIV Y = 200mV/DIV FIGURE 37. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-41) (REXT = 100kΩ) (Continued) VIN VREF X = 50µs/DIV X = 10µs/DIV Y = 200mV/DIV Y = 2V/DIV FIGURE 39. TURN-ON TIME FIGURE 38. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE GAIN IS x10,000 NOISE IS 4.5µVP-P 200 180 160 ZOUT ( Ω) 20mV/DIV 1nF LOAD 140 120 NO LOAD 100 80 60 10nF LOAD 40 20 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 1s/DIV FIGURE 40. ZOUT vs FREQUENCY FIGURE 41. VOUT NOISE, 0.1Hz TO 10Hz 7mA +50µA -50µA -7mA NO OUTPUT CAPACITANCE X = 5µs/DIV Y = 50mV/DIV FIGURE 42. LOAD TRANSIENT RESPONSE 12 NO OUTPUT CAPACITANCE X = 5µs/DIV Y = 500mA/DIV FIGURE 43. LOAD TRANSIENT RESPONSE FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100kΩ) 140 110 112µA 104µA 120 100 80 IIN (µA) IIN (µA) 100 +25°C 95µA 60 +125°C 90 40 -40°C 20 0 5.5 6.5 7.5 8.5 80 5.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 6.5 7.5 8.5 FIGURE 45. IIN vs VIN, 3 TEMPERATURES 5.0001 ΔVOUT (µV) (NORMALIZED TO VIN = 10.0V) 100 5.0000 4.9999 4.9998 104µA 4.9997 4.9996 95µA 4.9995 112µA 6.5 7.5 8.5 9.5 0 +125°C -100 +25°C -200 -40°C -300 -400 -500 -600 -700 5.50 6.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) VIN (V) FIGURE 46. LINE REGULATION FIGURE 47. LINE REGULATION OVER-TEMPERATURE 0.10 -40°C 0.05 0.00 ΔVOUT (mV) VOUT (V) (NORMALIZED TO 5.0V AT VIN = 10V) FIGURE 44. IIN vs VIN, 3 UNITS 4.9994 5.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) VIN (V) -0.05 +25°C -0.10 +125°C -0.15 -0.20 -0.25 -7 -6 -5 SINKING -4 -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4 5 6 7 SOURCING FIGURE 48. LOAD REGULATION 13 FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100kΩ) 0 5.001 NORMALIZED TO +25°C 5.001 5.000 UNIT 1 UNIT 2 NO LOAD -10 VIN (DC) = 10V -20 VIN (AC) RIPPLE = 50mVP-P -30 PSRR (dB) VOUT (V) (Continued) 5.000 4.999 -40 -50 -60 10nF -70 100nF -80 4.999 UNIT 3 4.998 -40 -20 1nF -90 0 20 40 60 80 100 120 -100 1 140 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) TEMPERATURE (°C) FIGURE 50. PSRR AT DIFFERENT CAPACITIVE LOADS FIGURE 49. VOUT vs TEMPERATURE VIN = 10V VIN = 10V DVIN = 1V DVIN = 1V FIGURE 51. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD FIGURE 52. LINE TRANSIENT RESPONSE, 0.001µF LOAD CAPACITANCE 12 120 10 100 VIN 8 6 ZOUT (W) VIN (V) AND VOUT (V) 1nF 450nA 4 60 NO LOAD 40 2 0 80 270nA 0 50 100 150 200 TIME (µs) FIGURE 53. TURN-ON TIME 14 10nF 20 340nA 250 300 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 54. ZOUT vs FREQUENCY FN6327.7 September 16, 2009 ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100kΩ) (Continued) GAIN IS x1000 NOISE IS 4.5µVP-P 2mV/DIV 50µA -50µA FIGURE 55. VOUT NOISE, 0.1Hz TO 10Hz FIGURE 56. LOAD TRANSIENT RESPONSE 7mA -7mA FIGURE 57. LOAD TRANSIENT RESPONSE Applications Information FGA Technology The ISL21009 voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics, which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). 15 The process used for these reference devices is a floating gate CMOS process and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections. Micropower Operation The ISL21009 consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 95µA and noise is 4.5µVP-P benefitting precision, low noise portable applications such as handheld meters and instruments. FN6327.7 September 16, 2009 ISL21009 Data Converters in particular can utilize the ISL21009 as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise. Board Mounting Considerations For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package, which will subject the die to mild stresses when the Printed Circuit (PC) board is heated and cooled, slightly changing the shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. Board Assembly Considerations FGA references provide high accuracy and low temperature drift but some PC board assembly precautions are necessary. Normal Output voltage shifts of 100µV to 1mV can be expected with Pb-free reflow profiles or wave solder on multi-layer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures, this may reduce device initial accuracy. Post-assembly x-ray inspection may also lead to permanent changes in device output voltage and should be minimized or avoided. If x-ray inspection is required, it is advisable to monitor the reference output voltage to verify excessive shift has not occurred. If large amounts of shift are observed, it is best to add an X-ray shield consisting of thin zinc (300µm) sheeting to allow clear imaging, yet block x-ray energy that affects the FGA reference. Special Applications Considerations In addition to post-assembly examination, there are also other X-ray sources that may affect the FGA reference long term accuracy. Airport screening machines contain X-rays and will have a cumulative effect on the voltage reference output accuracy. Carry-on luggage screening uses low level X-rays and is not a major source of output voltage shift, although if a product is expected to pass through that type of screening over 100 times it may need to consider shielding with copper or aluminum. Checked luggage X-rays are higher intensity and can cause output voltage shift in much fewer passes, so devices expected to go through those machines should definitely consider shielding. Note that just two layers of 1/2 ounce copper planes will reduce the received dose by over 90%. The leadframe for the device which is on the bottom also provides similar shielding. If a device is expected to pass through luggage X-ray machines numerous times, it is advised to mount a 2-layer (minimum) PC board on the top, and along with a ground 16 plane underneath will effectively shield it from from 50 to 100 passes through the machine. Since these machines vary in X-ray dose delivered, it is difficult to produce an accurate maximum pass recommendation. Noise Performance and Reduction The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4.5µVP-P. The noise measurement is made with a bandpass filter made of a 1-pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency (3dB) at 8.2Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10Hz to 1kHz bandwidth is approximately 2.2µVP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1-pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10x the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21009 does not drive heavily capacitive loads well, so for load capacitances above 0.001µF, the noise reduction network shown in Figure 58 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 15µVP-P from 1Hz to 1kHz using this network with a 0.01µF capacitor and a 2kΩ resistor in series with a 10µF capacitor. Also, transient response is improved. The 0.01µF value can be increased for better load transient response with little sacrifice in output stability. Higher output capacitor values can be used without the RC network to address transient loads without stability problems, although there will be more overshoot an longer settling times with values up to 1.0µF. Output capacitor values greater than 1.0µF are not recommended for the ISL21009. . VIN = 5.0V 10µF 0.1µF VIN VO ISL21009-25 GND 2kΩ 0.01µF 10µF FIGURE 58. HANDLING HIGH LOAD CAPACITANCE Turn-On Time The ISL21009 devices have low supply current and thus, the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 100µs, as shown in Figure 25. Circuit design must take this into account when looking at power-up delays or sequencing. FN6327.7 September 16, 2009 ISL21009 Temperature Coefficient Output Voltage Adjustment The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH – VLOW), and divide by the temperature extremes of measurement (THIGH – TLOW). The result is divided by the nominal reference voltage (at T = +25°C) and multiplied by 106 to yield ppm/°C. This is the “Box” method for specifying temperature coefficient. The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from VOUT to GND and connecting the wiper to the TRIM pin. The TRIM input is high impedance so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/°C) and the resulting voltage divider should have very low tempco <5ppm/°C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications. Typical Application Circuits VIN = +5.0V R = 200Ω 2N2905 VIN VOUT ISL21009 VOUT = 2.50V GND 2.5V/50mA 0.001µF FIGURE 59. PRECISION 2.5V, 50mA REFERENCE +3.5V TO 16.5V 0.1µF 10µF VIN VOUT ISL21009-25 VOUT = 2.50V GND 0.001µF VCC RH VOUT X9119 (UNBUFFERED) + SDA 2-WIRE BUS EL8178 SCL VSS – VOUT (BUFFERED) RL FIGURE 60. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE 17 FN6327.7 September 16, 2009 ISL21009 Typical Application Circuits (Continued) +3.5V TO 16.5V 0.1µF 10µF VIN EL8178 + VOUT VOUT SENSE – ISL21009-25 LOAD GND FIGURE 61. KELVIN SENSED LOAD 10µF +3.5V TO 16.5V 0.1µF VIN 2.5V ±2.5% VOUT ISL21009-25 TRIM GND VCC I2C BUS RH SDA SCL ISL95810 VSS RL FIGURE 62. OUTPUT ADJUSTMENT USING THE TRIM PIN 18 FN6327.7 September 16, 2009 ISL21009 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N a NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN6327.7 September 16, 2009