isl78420eval1z user guide

User Guide 006
ISL78420EVAL1Z Evaluation Board User Guide
Description
Key Features
The ISL78420EVAL1Z evaluation board is designed for a user to
evaluate the ISL78420 100V 2A half-bridge driver with tri-level
PWM input for driving the gates of two NMOS FETs in a
half-bridge configuration. These NFET MOSFETs are included on
the evaluation board to evaluate a half-bridge driven load such
as a DC motor or a synchronous switching regulator.
• 2A source and sink NMOS gate drivers
The ISL78420 is offered in a 14 Ld HTSSOP package
enhanced with a thermal EPAD. It operates from a supply
voltage of 8V to 14V DC with the capability of driving a highside NMOS FET in a 100V half-bridge configuration. A unique
tri-level PWM input allows control of both the high and low-side
gate driver with a single input. When the PWM pin is left in a
floating high impedance state both gate drivers are turned off,
which is beneficial for multiphase DC/DC switching that
requires phase shedding.
• Single PWM input for high-side and low-side gate driver with
tri-level for turning off both drivers
Specifications
This board is optimized for the following operating conditions:
• VDD supply: 8V to 14V
• Internal level shifter and bootstrap diode for gate driver on
high-side FET
• Up to 100V high-side gate drive reference
• 8V to 14V bias supply operation
• Single resistor adjustable dead time from 35ns to 220ns
Reference Documents
• ISL78420 datasheet
• ISL78225 datasheet
• AN1727, “ISL78225EVAL1Z: 4-Phase Interleaved
Synchronous Boost Converter”
Ordering Information
PART NUMBER
• PWM switching frequency: 10kHz to 1MHz
ISL78420EVAL1Z
• Preset half-bridge dead time: 35ns
DESCRIPTION
Evaluation Board, 100V 2A Half-Bridge
Driver with Tri-Level Input
• Peak gate drive current: 2A source and sink
• Half-bridge voltage: Up to 100V
FIGURE 1. ISL78420EVAL1Z EVALUATION BOARD
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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User Guide 006
Recommended Equipment
Tri-Level Input
The following equipment is recommended to operate this board:
The ISL78420 has a single input pin (PWM) for controlling the
HO/LO high-side and low-side gate drivers. See Table 1 below for
logic table of PWM to HO and LO. When the PWM pin is left
floating or driven to a valid tri-level voltage, both HO and LO
outputs are driven low.
• 8V to 14V power supply with at least 2A source current
capability
• 0V to 100V power supply for biasing the half bridge
• Digital multimeters (DMMs)
• Up to 1MHz square wave generator
• Load such as a DC motor or buck regulator output stage
(optional)
Quick Setup Guide
1. The dead time of the HO and LO signal is set to 35ns with an
80kΩ resistor from the RDT pin to GND. To change the dead
time, replace the resistor at R20 with the value corresponding
to the desired dead time. See Figure 9.
2. Apply 10V to 14V to VDD and GND.
3. Connect EN BNC to a function generator to control the enable
of the ISL78420 or connect to VDD to always enable.
4. If evaluating the bridge circuit, connect a bridge supply <100V
to the banana jack connectors J5 and J8. Connect load at
R24.
5. Connect a 0V to 5V <1MHz PWM signal to J7.
6. Verify HO and LO outputs are switching. LO switches between
GND and VDD phase inverted from PWM. HO switches
between GND and VHB + VBRIDGE in phase with PWM.
Bootstrap Capacitor
The ISL78420 requires an external bootstrap capacitor between
the HB and HS pins to provide the high-side supply biasing to
generate the level shifted gate voltage on the HO pin and more
importantly, deliver the gate drive current to switch the high-side
NMOS FET.
The ISL78420EVAL1Z is populated with a 0.47µF capacitor at C2
for the bootstrap function. This value will provide optimal bias for
switching frequencies ≥10kHz and is capable of delivering the
dynamic current for 100nC total gate charge while maintaining
<5% ripple voltage. See page 10 of the ISL78420 datasheet for
optimizing the bootstrap capacitance at different operating
conditions.
Dead Time Control
The ISL78420 features a dead time control circuit for
programming the delay between the falling edge of HO to rising
edge of LO and between the falling edge of LO to rising edge of
HO. A single resistor from the RDT pin to GND adjusts the dead
time from 35ns (80kΩ) to 220ns (8kΩ). The ISL78420EVAL1Z
contains a 80kΩ resistor at R20 which sets the dead time to
35ns. Refer to Figure 9 for selecting a resistor value for the
desired dead time.
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Because some function generators do not have a high
impedance disable function (when disabled, the generator
output pulls to GND), the ISL78420EVAL1Z has a switch SW1 on
board to isolate the function generator signal to the PWM input.
Otherwise, the PWM signal is taken to ground which keeps the
LO output at VDD voltage and the HO ouput at HS voltage.
TABLE 1. TRI-LEVEL PWM LOGIC INPUT
PWM
GATE
DRIVE
HIGH
HO
Driven to HB+HS
LO
Driven to VSS
HO
Driven to HS
LO
Driven to VSS
HO
Driven to HS
LO
Driven to VDD
MID
LOW
HO/LO OUTPUT VOLTAGE
Half Bridge Configured MOSFETs
The ISL78420EVAL1Z includes a bridge configured high side (Q1)
and low side (Q2) FET. These devices are automotive grade 100V
NMOS FETs. The source of the high-side FET and drain of the
low-side FET are connected together to the HS node of the
ISL78420. The HO pin drives the gate of Q1 and the LO pin drives
the gate of Q2. The 0.47µF boot capacitor is designed to provide
the necessary gate drive to switch Q1 to frequencies down to
10kHz with minimal ripple on the bootstrap bias.
Other Circuits
The ISL78420EVAL1Z also contains an automotive grade LDO
(ISL78307) and SPDT switch (ISL76123) which is used to switch
between the PWM signal external to the ISL78420 or have the
signal path open, allowing the ISL78420 PWM pin to float to a
tri-level state. The ISL78307 LDO accepts the 10V to 14V VDD
input voltage and outputs a constant 5V bias for the ISL76123
analog switch that connects or disconnects the signal at J7 BNC
from the PWM pin of ISL78420. The switch SW1 toggles the logic
state of the ISL76123.
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VDD
VDD
VDD
VDD
VDD
V+
NC
8
15
EP
DNP
DNP
1SW1
2
2
OUT
2
V+
COM
5
3
GND
NC
4
TP14
V+
R27
C13
DNP
R33
0.1UF
C9
1
Q2
DNP
TBD
R24
LOAD
2
10UF
C8
0
R14
2
1
J7
5
2
100
FDD3672
DRAWN BY:
DATE:
ENGINEER:
RELEASED BY:
DATE:
TITLE:
UPDATED BY:
DATE:
RICHARD KOVACS
RICHARD KOVACS
3
R13
100K
C5
TBD
D1
2
DL4001
1
TP5
6
FDD3672
R11
0
NO
TP18
Q1
3
R12
100K
C4
TBD
1
R1
DNP
C3
HS
TBD
TP15
IN
0.1UF
TP4
ISL76123
1
EXT
GEN
1
0
D3
U3
J5
TP7
R32
12
TP13
0
C15
TP19
3
V BRIDGE
User Guide 006
RDT R20
V+
TP3
R10
0.1UF
C14
0
TP11
TP6
10UF
R30
100K
C11
3
4
R26
TP10
ISL78420CZ
ISL78307
TP12
10
DNP
NC
EPAD
R28
7
5
VDD
DNP
9
GND
6
R29
RDT
NC
EN
7
3
4
EN
NC
NC
8
1
HS
6
ADJ/NC
D2
5
OUT
NC
2
HO
TP9
IN
TBD
PWM
11
J4
5
C12
12
4
3
9
100K
13
VSS
2
4
R25
LO
HB
DNP
NC
R18
3
R22
14
80.6K
VDD
0
DNP
R9
2
DNP
R7
DNP
R5
DNP
R3
DNP
NC
EN
1
2
U2
1
R31
TP8
R16
C2
1
J1
0.47UF
C1
TBD
3
3
2
1
0.1UF
C10
C7
R23
U1
10UF
DNP
DNP
R21
DNP
R19
DNP
R17
R15
0.1UF
C6
10UF
R8
DNP
R6
GND
R4
R2
TP17
DNP
VDD IN
DNP
TP16
DNP
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ISL78420EVAL1Z Schematic
J8
GND
05/19/2014
DATE:
TIM LOK
ISL78420_EVAL1Z
10/08/2014
TESTER
MASK#
FILENAME:
HRDWR ID
SHEET
REV.
A
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User Guide 006
BILL OF MATERIALS
PART
NUMBER
REFERENCE
DESIGNATOR
DESCRIPTION
MANUFACTURER
ISL78420AVEZ
U1
100V; 2A BRIDGE DRIVER
INTERSIL
ISL76123AHZ
U3
300mA SPDT SWITCH; SOT26
INTERSIL
ISL78307FBEBZ
U2
40V; 50mA LDO; SOIC
INTERSIL
2.1A 60V SCHOTTKY
IR
50V; 1A DIODE
MCC
NFET 100V, 44A,28mΩ, TO-252
FAIRCHILD
SPDT SWITCH
C&K
10µF CAP; 200V; 20%; RADIAL
NICHICON
10µF CAP; 50V; 10%; 1206
GENERIC
0.1µF CAP; 50V; 5%; 0805
GENERIC
C2
0.47µF CAP; 50V; 10%; 0805
GENERIC
C9
0.1µF CAP; 200V; 10%; 1206
GENERIC
0Ω; 1/16W; 1%; 0603
GENERIC
R27
100Ω; 1/16W; 1%; 0603
GENERIC
R12, R13, R25, R30
100kΩ; 1/16W; 1%; 0603
GENERIC
R20
80.6kΩ; 1/16W; 1%; 0603
GENERIC
R14
OΩ; 1W; 1%; 2512
GENERIC
10MQ060N
D2, D3
DL4001
D1
FDD3672
Q1, Q2
GT11MSCBETR
SW1
UBT2D100MPD1TD
C8
C6, C10, C14
C7, C11, C13, C15
R10, R11, R23, R26, R32
TP3-TP19
PCB SPECIFICATION
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TEST POINT
J5, J8
BANANA JACK
J4, J7
BNC CONNECTOR
2oz Cu; 1.57mm Thickness FR-4
4
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User Guide 006
ISL78420EVAL1Z Board Layout
FIGURE 2. SILK SCREEN TOP
FIGURE 3. SILK SCREEN BOTTOM
FIGURE 4. TOP LAYER PCB
FIGURE 5. BOTTOM LAYER PCB
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User Guide 006
Typical Performance Curves
Unless otherwise specified, operating conditions at: T = 25°C; VDD = EN = 12V;
VSS = HS = 0V; RDT = 10kΩ; CBOOT = 0.47µF; 100kΩ load on LO to VSS and HO to HS.
1000
8V
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
1000
10V
12V
100
10
0pF
470pF
1000pF
100
2000pF
10
CAPACITOR LOAD ONLY
HS = VSS = 0V
DRIVING FDD3672 NFET
VBRIDGE = 60V
1
1
10
100
FREQUENCY (kHz)
1
1
1000
FIGURE 6. POWER DISSIPATION vs FREQUENCY vs VDD with
NFET LOAD
10
100
FREQUENCY (kHz)
1000
FIGURE 7. POWER DISSIPATION vs FREQUENCY vs CAPACITIVE
LOAD
1000
320
240
200
DEAD TIME DELAY (ns)
POWER DISSIPATION (mW)
8V
10V
100
12V
14V
10
T = -40°C
160
140
120
100
T = +125°C
80
T = +85°C
T = +25°C
60
40
TA = -40°C TO +125°C
tDTLH and tDTHL
1000pF CAPACITOR LOAD
HS = VSS = 0V
1
1
10
100
FREQUENCY (kHz)
1000
FIGURE 8. POWER DISSIPATION vs FREQUENCY vs VDD
20
8
16
24
32
40
48 56 64 72 80
RESISTOR ON RDT PIN (kΩ)
FIGURE 9. DEAD TIME DELAY vs RDT RESISTOR
DRIVING FDD3672 NFET
BRIDGE = 60V
0Ω GATE RESISTOR
DRIVING FDD3672 NFET
BRIDGE = 60V
0Ω GATE RESISTOR
HO
LO
HO
LO
PWM
PWM
FIGURE 10. PWM, LO AND HO PULSE WAVEFORM
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FIGURE 11. PWM, LO AND HO PULSE WAVEFORM
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User Guide 006
Typical Performance Curves
Unless otherwise specified, operating conditions at: T = 25°C; VDD = EN = 12V;
VSS = HS = 0V; RDT = 10kΩ; CBOOT = 0.47µF; 100kΩ load on LO to VSS and HO to HS. (Continued)
DRIVING FDD3672 NFET
VBRIDGE = 60V
10Ω GATE RESISTOR
DRIVING FDD3672 NFET
VBRIDGE = 60V
10Ω GATE RESISTOR
HO
HO
LO
LO
PWM
FIGURE 12. PWM, LO AND HO PULSE WAVEFORM
PWM
FIGURE 13. PWM, LO AND HO PULSE WAVEFORM
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cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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