EL1508 ® Data Sheet March 26, 2007 FN7014.5 Differential DSL Line Driver Features The EL1508 is designed for driving full rate ADSL signals in both CO and CPE applications at very low power dissipation. The high drive capability of 450mA makes this driver ideal for both CAP and DMT designs. It contains two wideband, high-voltage, current mode feedback amplifiers with a number of power dissipation reduction features. • 450mA output drive capability • 43.6VP-P differential output drive into 100Ω • 2nd/3rd harmonics of -85dBc/-75dBc • MTPR of -70dB • Operates down to 3mA per amplifier supply current These drivers achieve an MTPR distortion measurement of better than 70dB, while consuming typically 6mA of total supply current. This supply current can be set using a resistor on the IADJ pin. Two other pins (C0 and C1) can also be used to adjust supply current to one of four pre-set modes (full-IS, 2/3-IS, 1/3-IS, and full power-down). The EL1508 operates on ±5V to ±12V supplies and retains its bandwidth and linearity over the complete supply range. • Power control features • Pin-compatible with EL1503 • Pb-free plus anneal available (RoHS compliant) Applications • ADSL line driver • HDSL line driver The device is supplied in a thermally-enhanced 20 Ld SOIC (0.300”), a thermally-enhanced 16 Ld SOIC (0.150”), and the small footprint (4x5mm) 24 Ld QFN packages. The EL1508 is specified for operation over the full -40°C to +85°C temperature range. • Video distribution amplifier • Video twisted-pair line driver Pinouts 18 VS+ VS- 3 - + GND* 4 GND* 5 VS- 3 17 GND* GND* 4 16 GND* GND* 5 GND* 6 15 GND* VIN+A 6 GND* 7 14 GND* C1 7 VIN+A 8 13 VIN+B C0 8 14 VS+ 13 GND* 12 GND* 11 VIN+B POWER CONTROL LOGIC 20 VOUTB 21 VIN-B 22 NC 15 VOUTB 23 VIN-A 16 VIN-B VOUTA 2 B + - A 24 VOUTA 19 VOUTB VOUTA 2 VIN-A 1 - + 20 VIN-B VIN-A 1 EL1508 (24 LD QFN) TOP VIEW EL1508 [16 LD SOIC (0.150”)] TOP VIEW + - EL1508 [20 LD SOIC (0.300”)] TOP VIEW NC 1 19 NC NC 2 18 NC VS- 3 17 VS+ THERMAL PAD NC 4 16 NC NC 5 15 NC NC 6 14 NC 10 IADJ 9 NC 1 VIN+B 12 *GND PINS ARE HEAT SPREADERS IADJ 11 11 NC 13 GND C0 10 12 IADJ C1 9 C0 10 POWER CONTROL LOGIC VIN+A 8 GND 7 C1 9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL1508 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL1508CS EL1508CS - 16 Ld SOIC (0.150”) MDP0027 EL1508CS-T7 EL1508CS 7” 16 Ld SOIC (0.150”) MDP0027 EL1508CS-T13 EL1508CS 13” 16 Ld SOIC (0.150”) MDP0027 EL1508CSZ (See Note) EL1508CSZ - 16 Ld SOIC (0.150”) (Pb-Free) MDP0027 EL1508CSZ-T7 (See Note) EL1508CSZ 7” 16 Ld SOIC (0.150”) (Pb-Free) MDP0027 EL1508CSZ-T13 (See Note) EL1508CSZ 13” 16 Ld SOIC (0.150”) (Pb-Free) MDP0027 EL1508CM EL1508CM - 20 Ld SOIC (0.300”) MDP0027 EL1508CM-T13 EL1508CM 13” 20 Ld SOIC (0.300”) MDP0027 EL1508CMZ (See Note) EL1508CMZ - 20 Ld SOIC (0.300”) (Pb-Free) MDP0027 EL1508CMZ-T13 (See Note) EL1508CMZ 13” 20 Ld SOIC (0.300”) (Pb-Free) MDP0027 EL1508CL 1508CL - 24 Ld QFN MDP0046 EL1508CL-T7 1508CL 7” 24 Ld QFN MDP0046 EL1508CL-T13 1508CL 13” 24 Ld QFN MDP0046 EL1508CLZ (See Note) 1508CLZ - 24 Ld QFN (Pb-Free) MDP0046 EL1508CLZ-T7 (See Note) 1508CLZ 7” 24 Ld QFN (Pb-Free) MDP0046 EL1508CLZ-T13 (See Note) 1508CLZ 13” 24 Ld QFN (Pb-Free) MDP0046 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7014.5 March 26, 2007 EL1508 Absolute Maximum Ratings (TA = 25°C) VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V VS- Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -28V to 0.3V Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V IADJ Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Output Current from Driver (Static) . . . . . . . . . . . . . . . . . . . . 100mA Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS = ±12V, RF = 2.2kΩ, RL= 65Ω, IADJL = C0 = C1 = 0V, TA = 25°C. Amplifiers tested separately. DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY CHARACTERISTICS IS+ (Full IS) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V 10 14.5 18 mA IS- (Full IS) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V -9.5 -13.5 -17.5 mA IS+ (2/3 IS) Positive Supply Current per Amplifier All outputs at 0V, C0 = 5V, C1 = 0V 7 10 12.5 mA IS- (2/3 IS) Negative Supply Current per Amplifier All outputs at 0V, C0 = 5V, C1 = 0V -6 -9 -12 mA IS+ (1/3 IS) Positive Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V 3.75 5.25 7 mA IS- (1/3 IS) Negative Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V -2.75 -4.25 -6 mA IS+ (6.8k) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V, RADJ = 6.8k 3 3.75 4.5 mA IS- (6.8k) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V, RADJ = 6.8k -3.75 -2.9 -2.25 mA IS+ (Power-down) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V 0.75 1.2 2 mA IS- (Power-down) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V 0 -0.25 -2 mA IGND GND Supply Current per Amplifier All outputs at 0V 1 mA INPUT CHARACTERISTICS VOS Input Offset Voltage -10 1 10 mV ΔVOS VOS Mismatch -5 0 5 mV IB+ Non-Inverting Input Bias Current -15 15 µA IB- Inverting Input Bias Current -50 50 µA ΔIB- IB- Mismatch -25 0 25 µA ROL Transimpedance 1.1 2.9 5 MΩ eN Input Noise Voltage 3.5 nV/√ Hz iN -Input Noise Current 13 pA/√ Hz VIH Input High Voltage C0 and C1 inputs VIL Input Low Voltage C0 and C1 inputs IIH1 Input High Current for C1 C1 = 5V 1 IIH0 Input High Current for C0 C0 = 5V 0.5 IIL Input Low Current for C0 or C1 C0 = 0V, C1 = 0V -1 3 2.25 V 0.8 V 2 6 µA 1 3 µA 1 µA FN7014.5 March 26, 2007 EL1508 Electrical Specifications PARAMETER VS = ±12V, RF = 2.2kΩ, RL= 65Ω, IADJL = C0 = C1 = 0V, TA = 25°C. Amplifiers tested separately. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT RL = 100Ω ±10.6 ±10.8 ±11.5 V RL = 25Ω ±9.8 ±10.2 ±10.6 V OUTPUT CHARACTERISTICS VOUT Loaded Output Swing IOL Linear Output Current AV = 5, RL = 10Ω, f = 100kHz, THD = -60dBc 450 mA IOUT Output Current VOUT = 1V, RL = 1Ω 1 A DYNAMIC PERFORMANCE BW -3 dB Bandwidth AV = +5 80 MHz HD2 2nd Harmonic Distortion fC = 1MHz, RL = 100Ω, VOUT = 2VP-P -90 dBc fC = 1MHz, RL = 25Ω, VOUT = 2VP-P -80 dBc fC = 1MHz, RL = 100Ω, VOUT = 2VP-P -90 dBc fC = 1MHz, RL = 25Ω, VOUT = 2VP-P -75 dBc -70 dBc HD3 3rd Harmonic Distortion MTPR Multi-Tone Power Ratio 26kHz to 1.1MHz, RLINE = 100Ω, PLINE = 20.4dBM SR Slewrate VOUT from -8V to +8V measured at ±4V 4 450 600 800 V/µs FN7014.5 March 26, 2007 EL1508 Pin Descriptions 16 Ld SOIC (0.150") 20 Ld SOIC (0.300") 24 Ld QFN PIN NAME 1 1 23 VIN-A FUNCTION CIRCUIT Channel A Inverting Input CIRCUIT 1 2 2 24 VOUTA Channel A Output 3 3 3 VS- Negative Supply 4, 5 4, 5, 6, 7 7 GND Ground Connection 6 8 8 VIN+A (Reference Circuit 1) Channel A Non-inverting Input VS+ VS- CIRCUIT 2 7 9 9 C1 Current Control Bit 1 VS+ 6.7V CIRCUIT 3 8 10 10 C0 Current Control Bit 2 9 11 1, 2, 4, 5, 6, 14, 15, 16, 18, 19, 22 NC Not Connected 10 12 11 IADJ (Reference Circuit 3) Supply Current Control Pin VS+ IADJ GND CIRCUIT 4 11 13 12 VIN+B 12, 13 14, 15, 16, 17 13 GND Ground Connection 14 18 17 VS+ Positive Supply 15 19 20 VOUTB 16 20 21 VIN-B 5 Channel B Non-inverting Input (Reference Circuit 2) Channel B Output (Reference Circuit 1) Channel B Inverting Input (Reference Circuit 1) FN7014.5 March 26, 2007 EL1508 Typical Performance Curves 24 RF=2kΩ RF=1.5kΩ 16 RF=2.5kΩ 20 GAIN (dB) GAIN (dB) 22 18 AV=10 VS=±12V RL=100Ω RADJ=0Ω RF=3kΩ 18 16 AV=5 VS=±12V RL=100Ω RF=2.5kΩ 14 RF=4kΩ 12 RF=3.5kΩ 1M 10M 8 100K 100M FREQUENCY (Hz) 20 RF=3kΩ 18 RF=4kΩ 14 RF=3.5kΩ RF=3kΩ 1M 10M 8 100K 100M FREQUENCY (Hz) RF=4kΩ RF=2kΩ RF=2.5kΩ 14 100K RF=2kΩ RF=3kΩ 12 RF=2.5kΩ 10 10M 100M FREQUENCY (Hz) FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE) 6 14 RF=3.5kΩ RF=3kΩ 1M GAIN (dB) GAIN (dB) 16 16 100M AV=5 VS=±12V RL=100Ω RF=1.5kΩ 20 18 10M FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE (2/3 POWER MODE) 18 AV=10 VS=±12V RL=100Ω RADJ=0Ω 1M FREQUENCY (Hz) FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE) 22 RF=2.5kΩ 10 14 100K 24 RF=2kΩ 12 RF=2.5kΩ 16 100M AV=5 VS=±12V RL=100Ω RF=1.5kΩ GAIN (dB) GAIN (dB) 16 RF=2kΩ 10M FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE (1/3 POWER MODE) 18 AV=10 VS=±12V RL=100Ω RADJ=0Ω 1M FREQUENCY (Hz) FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs RF (1/3 POWER MODE) 22 RF=2kΩ 10 14 100K 24 RF=3kΩ 8 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE) FN7014.5 March 26, 2007 EL1508 Typical Performance Curves MAGNITUDE (dB) 22 26 VS=±12V RFB=3kΩ AV=5 RL=83Ω RSET=0Ω 100pF MAGNITUDE (dB) 26 (Continued) 68pF 18 50pF 14 22pF 10 VS=±12V RFB=3kΩ 22 AV=5 RL=83Ω RSET=0Ω 18 150pF 100pF 62pF 14 39pF 10 0pF 22pF 0pF 6 10K 100K 10M 1M 6 10K 100M 100K FREQUENCY (Hz) VS=±12V RFB=3kΩ AV=10 RL=100Ω 5 150pF PEAKING (dB) MAGNITUDE (dB) 22 FIGURE 8. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL (1/3 POWER MODE) 6 VS=±12V RFB=3kΩ AV=5 RL=83Ω RSET=0Ω 100pF 18 62pF 14 39pF 10 100M FREQUENCY (Hz) FIGURE 7. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL (1/3 POWER MODE) 26 10M 1M 22pF 4 3 2 1 5pF 6 10K 100K 10M 1M 0 100M 5 6 FIGURE 9. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL 6 9 10 VS=±7.5V RFB=3kΩ AV=10 RL=100Ω 6 PEAKING (dB) PEAKING (dB) 7 4 3 2 1 0 8 FIGURE 10. PEAKING vs IS+ VS=±12V RFB=3kΩ AV=10 RL=100Ω 5 7 TOTAL IS (mA) FREQUENCY (Hz) 5 4 3 2 1 0 2 4 6 8 RADJ (kΩ) FIGURE 11. PEAKING vs RADJ 7 10 0 5 7 9 11 13 15 ISUPPLY (mA) FIGURE 12. PEAKING vs IS+ FN7014.5 March 26, 2007 EL1508 Typical Performance Curves (Continued) 0 40 -20 GAIN (dB) ROUT (Ω) 30 20 -40 A to B -60 10 B to A -80 0 10K 100K 10M 1M -100 10K 100M 100K FREQUENCY (Hz) FIGURE 13. OUTPUT IMPEDANCE DIFFERENTIAL GAIN (%), PHASE (°) VOLTAGE NOISE (nV/√Hz), CURRENT NOISE (pA/√Hz) CURRENT NOISE 10 VOLTAGE NOISE 1K 100 100K 10K 1.4 1.2 1.0 0.6 0.4 DIFF GAIN 0.20 0.15 0.10 DIFF PHASE 0.05 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 NUMBER of 150Ω RESISTOR LOADS FIGURE 17. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (2/3 POWER MODE) 8 DIFF PHASE 0.2 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FIGURE 16. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (2/3 POWER MODE) DIFFERENTIAL GAIN (%), PHASE (°) DIFFERENTIAL GAIN (%), PHASE (°) 0.25 DIFF GAIN NUMBER of 150Ω RESISTOR LOADS FIGURE 15. VOLTAGE AND CURRENT NOISE vs FREQUENCY VS=±12V RFB=3kΩ AV=2 RSET=0Ω VS=±12V RFB=3kΩ AV=2 RSET=0Ω 0.8 FREQUENCY (Hz) 0.30 100M FIGURE 14. CHANNEL SEPARATION 100 1 10 10M 1M FREQUENCY (Hz) 0.08 VS=±12V RFB=3kΩ AV=2 RSET=0Ω 0.07 0.06 DIFF PHASE 0.05 0.04 DIFF GAIN 0.03 0.02 0.01 0 1 2 3 4 5 NUMBER of 150Ω RESISTOR LOADS FIGURE 18. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (FULL POWER MODE) FN7014.5 March 26, 2007 EL1508 0 FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 -10 -30 HD3 -50 HD2 -70 -90 HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) Typical Performance Curves - 24 Ld QFN Package 0 1 2 3 4 5 6 7 8 -20 -40 HD3 -60 HD2 -80 -100 9 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 0 5 VOUTP-P (V) -30 HARMONIC DISTORTION (dB) -20 HD (dB) 25 20 25 20 25 0 FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 -10 HD3 -40 -50 -60 HD2 -70 -80 0 1 2 3 4 5 6 7 8 -20 HD3 -40 -60 -80 HD2 -100 9 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 0 5 VOUTp-p (V) 10 15 VOUTP-P (V) FIGURE 21. HARMONIC DISTORTION TEST (2/3 POWER MODE) FIGURE 22. HARMONIC DISTORTION TEST (2/3 POWER MODE) 0 FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 -10 -20 -30 HARMONIC DISTORTION (dB) 0 HARMONIC DISTORTION (dB) 20 FIGURE 20. HARMONIC DISTORTION TEST (1/3 POWER MODE) 0 HD3 -40 -50 -60 -70 -80 HD2 -90 -100 15 VOUTP-P (V) FIGURE 19. HARMONIC DISTORTION TEST (1/3 POWER MODE) -90 10 0 1 2 3 4 5 6 7 VOUTp-p (V) FIGURE 23. HARMONIC DISTORTION TEST (FULL POWER MODE) 9 8 9 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 -20 HD3 -40 -60 -80 HD2 -100 0 5 10 15 VOUTP-P (V) FIGURE 24. HARMONIC DISTORTION TEST (FULL POWER MODE) FN7014.5 March 26, 2007 EL1508 Typical Performance Curves - 20 Ld SOIC (0.300") Package FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 -20 HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) 0 -40 HD2 -60 HD3 -80 -30 -50 1 2 3 4 5 6 7 8 HD 2 -70 HD 3 -90 0 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 -10 9 0 5 FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 -30 -50 HD2 -70 HD3 -90 0 1 3 2 4 5 6 7 8 -30 -50 HD 2 HD 3 0 5 -40 HD2 -80 HD3 2 3 4 5 6 7 8 VOUTP-P (V) FIGURE 29. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) 10 20 25 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 -10 -30 -50 HD 2 -70 HD 3 -90 1 15 FIGURE 28. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (2/3 POWER MODE) HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) FREQ=1MHz VS=±5V RSET=0 RL=100Ω GAIN=10 0 10 VOUTP-P (V) 0 -100 25 -70 -90 9 FIGURE 27. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (2/3 POWER MODE) -60 20 FREQ=1MHz VS=±12V RSET=0 RL=100Ω GAIN=10 -10 VOUTP-P (V) -20 15 FIGURE 26. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/3 POWER MODE) HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) FIGURE 25. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/3 POWER MODE) -10 10 VOUTP-P (V) VOUTP-P (V) 0 5 10 15 20 25 VOUTP-P (V) FIGURE 30. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) FN7014.5 March 26, 2007 EL1508 FREQ=1MHz VS=±5V RSET=6.81kΩ RL=100Ω GAIN=10 -10 HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) Typical Performance Curves -30 HD 3 -50 HD 2 -70 0 1 2 3 5 4 7 6 -30 -70 HD2 0 1 2 VOUTP-P (V) HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) HD 2 -60 HD 3 0 5 7 8 9 0 -40 -80 6 5 FIGURE 32. EL1508CL HARMONIC DISTORTION TEST (FULL POWER MODE) FREQ=1MHz VS=±12V RSET=6.81kΩ RL=100Ω GAIN=10 -20 4 3 VOUTP-P (V) FIGURE 31. EL1508CM HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) 0 HD3 -50 -90 9 8 FREQ=1MHz VS=±5V RSET=6.81kΩ RL=100Ω GAIN=10 -10 10 15 20 25 FREQ=1MHz VS=±12V RSET=6.81kΩ RL=100Ω GAIN=10 -20 HD3 -40 -60 HD2 -80 -100 0 VOUTP-P (V) 5 10 15 20 25 VOUTP-P (V) FIGURE 33. EL1508CM HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE) VOUT FIGURE 34. EL1508CL HARMONIC DISTORTION TEST (FULL POWER MODE) VOUT C0, C1 C0, C1 2V/DIV 2V/DIV 40ns/DIV FIGURE 35. DISABLE TIME 11 40ns/DIV FIGURE 36. ENABLE TIME FN7014.5 March 26, 2007 EL1508 Typical Performance Curves (Continued) 25 21.4 21 21.2 17 IS+ (mA) OUTPUT VOLTAGE P-P (V) 21.6 21.0 FREQ=100kHz VS=±12V RSET=0 AV=10 20.8 20.6 50 70 110 90 130 150 170 VS=±12V RFB=10 AV=10 RL=100Ω 13 9 5 190 0 2 4 8 10 RADJ (kΩ) DIFFERENTIAL LOAD RESISTANCE (Ω) FIGURE 37. LOAD RESISTANCE vs OUTPUT VOLTAGE (ALL POWER MODES) FIGURE 38. IS+ vs RADJ (FULL POWER MODE) 30 4.5 25 FU LL P - 20 2/3 POW 15 10 4.0 + OWE R POWER DISSIPATION (W) SUPPLY CURRENT (mA) 6 + ER - 1/3 POWER + - 5 θJA = 30°C/W 3.5 3.0 2.5 θJA = 43°C/W 2.0 θJA = 53°C/W 1.5 θJA = 80°C/W 1.0 0.5 0 0 2 6 4 8 10 0 -40 12 -20 SUPPLY VOLTAGE (V) FIGURE 39. SUPPLY CURRENT vs SUPPLY VOLTAGE 4 4.0 3.5 USING JEDEC JESD51-3 HIGH EFFECTIVE THERMAL CONDUCTIVITY. (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.5 POWER DISSIPATION (W) POWER DISSIPATION (W) 100 FIGURE 40. POWER DISSIPATION vs AMBIENT TEMPERATURE for VARIOUS MOUNTED θJAs (See Thermal Resistance Curve on page 15) USING ELANTEC EL1503CS DEMO BOARD, 2”X2” (4-LAYER). DEMO BOARD WITH HEATSINK VIA INTERNAL GROUND PLANE 3 θJ 2.5 A =4 2 7° C/ W 1.5 1 0.5 0 -40 20 40 60 80 0 AMBIENT TEMPERATURE (°C) 3.0 3.378W θ JA = 2.5 37 °C /W 2.0 1.5 1.0 0.5 0 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) FIGURE 41. 16 LD SOIC POWER DISSIPATION and THERMAL RESISTANCE 12 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 42. 24 LD QFN POWER DISSIPATION vs AMBIENT TEMPERATURE FN7014.5 March 26, 2007 EL1508 Applications Information The EL1508 consists of two high-power line driver amplifiers that can be connected for full duplex differential line transmission. The amplifiers are designed to be used with signals up to 4MHz and produce low distortion levels. The EL1508 has been optimized as a line driver for ADSL CO application. The driver output stage has been sized to provide full ADSL CO power level of 20dBM onto the telephone lines. Realizing that the actual peak output voltages and currents vary with the line transformer turns ratio, the EL1508 is designed to support 450mA of output current which exceeds the level required for 1:2 transformer ratio. A typical ADSL interface circuit is shown in Figure 43 below. Each amplifier has identical positive gain connections, and optimum common-mode rejection occurs. Further, DC input errors are duplicated and create commonmode rather than differential line errors. DRIVER INPUT+ + - ROUT LINE + RF ZLINE 2RG RF DRIVER INPUT- ROUT + LINE RF + RECEIVE OUT + RECEIVE AMPLIFIERS RECEIVE OUT - + RF R RIN the average output current, IO, or 1/2 IQ, whichever is the lowest. We’ll call this term IX. Therefore, we can determine a quiescent current with the equation: P Dquiescent = V S × ( I S – 21 X ) where: VS is the supply voltage (VS+ to VS-) IS is the operating supply current (IS+ - IS-) / 2 IX is the lesser of IO or 1/2 IQ The dissipation in the output stage has two main contributors. Firstly, we have the average voltage drop across the output transistor and secondly, the average output current. For minimal power dissipation, the user should select the supply voltage and the line transformer ratio accordingly. The supply voltage should be kept as low as possible, while the transformer ratio should be selected so that the peak voltage required from the EL1508 is close to the maximum available output swing. There is a trade off, however, with the selection of transformer ratio. As the ratio is increased, the receive signal available to the receivers is reduced. Once the user has selected the transformer ratio, the dissipation in the output stages can be selected with the following equation: VS P Dtransistors = 2 × I O × ⎛ ------- – V O⎞ ⎝ 2 ⎠ R RIN where: VS is the supply voltage (VS+ to VS-) FIGURE 43. TYPICAL LINE INTERFACE CONNECTION VO is the average output voltage per channel IO is the average output current per channel Input Connections The EL1508 amplifiers are somewhat sensitive to source impedance. In particular, they do not like being driven by inductive sources. More than 100nH of source impedance can cause ringing or even oscillations. This inductance is equivalent to about 4” of unshielded wiring, or 6” of unterminated transmission line. Normal high-frequency construction obviates any such problem. Power Supplies and Dissipation Due to the high power drive capability of the EL1508, much attention needs to be paid to power dissipation. The power that needs to be dissipated in the EL1508 has two main contributors. The first is the quiescent current dissipation. The second is the dissipation of the output stage. The quiescent power in the EL1508 is not constant with varying outputs. In reality, 50% of the total quiescent supply current needed to power each driver is converted in to output current. Therefore, in the equation below we should subtract 13 The overall power dissipation (PDISS) is obtained by adding PDquiescent and PDtransistor. Estimating Line Driver Power Dissipation in ADSL CO Applications Figure 44 on the following page shows a typical ADSL CO line driver implementation. The average line power requirement for the ADSL CO application is 20dBM (100mW) into a 100Ω line. The average line voltage is 3.16VRMS. The ADSL DMT peak to average ratio (crest factor) of 5.3 implies peak voltage of 16.7V into the line. Using a differential drive configuration and transformer coupling with standard back termination, a transformer ratio of 1:1 is selected. With 1:1 transformer ratio, the impedance across the driver side of the transformer is 100Ω, the average voltage is 3.16VRMA and the average current is 31.6mA. The power dissipated in the EL1508 is a FN7014.5 March 26, 2007 EL1508 combination of the quiescent power and the output stage power when driving the line: PCB Layout Considerations for QFN and SOIC Packages Pd = P quiescent + P output-stage The EL1508 die is packaged in three different thermallyefficient packages: a 20 Ld SOIC (0.300”), a 16 Ld SOIC (0.150”), and a 24 Ld QFN. The 16 Ld SOIC has the same external dimensions as a standard 0.150” width SOIC package, but has the center four leads (two per side) internally-fused for heat transfer purposes. Both packages can use PCB surface metal vias areas and internal ground planes, to spread heat away from the package. The larger the PCB area the lower the junction temperature of the device will be. In XDSL applications, multiple layer circuit boards with internal ground plane are generally used. 13 mil vias are recommended to connect the metal area under the device with the internal ground plane. Examples of the PCB layouts are shown in the figures below that result in thermal resistance θJA of 37°C/W for the QFN package and 47°C/W for the SOIC package. The thermal resistance is obtained with the EL1508CL and CS demo boards. The demo board is a 4-layer board built with 2oz. copper and has a dimension of 4in2. Note, the user must follow the thermal layout guideline to achieve these results. In addition to lower thermal resistance, the QFN package exhibits much lower 2nd harmonic distortion. Pd = V S × I Q + ( V S – 2 × V OUT-RMS ) × I OUT-RMS In the full power mode and with 6.8k RADJ registers, the EL1508 consumes typically 7mA quiescent current and still able to maintain very low distortion. The distortion results are shown in typical performance section of the data sheet. When driving a load, a large portion (about 50%) of the quiescent current becomes output load current: Pd = 12 × ( 7mA × 50% ) + ( 12V – 3.16 ) × 31.6mA × 2 where: Pd = 598mW The θJA requirement needs to be calculated. This is done using the equation: T JUNCT – T AMB Θ JA = -------------------------------------------P DISS where: A separate Application Note for the QFN package and layout recommendations is also available. TJUNCT is the maximum die temperature (150°C) TAMB is the maximum ambient temperature (85°C) PDISS is the dissipation calculated above θJA is the junction to ambient thermal resistance for the package when mounted on the PCB 150 – 85 Θ JA = ---------------------- = 108°C/W 598mW TX+ FROM AFE + - VS+ RT VS- 10 0.22µF RF 2RG TXFR 1:1 100 3k TOP (24 LD QFN) 1.5kΩ TX- VS+ RT VSRF 10 + - 0.22µF 3k FIGURE 44. TYPICAL ADSL CO LINE DRIVER IMPLEMENTATION INTERNAL GROUND PLANE (24 LD QFN) 14 FN7014.5 March 26, 2007 EL1508 MOUNTED DEVICE θJA (°C/W) 55 Note: 2OZ COPPER USED TOP FOIL ONLY-WITH SOLDER MASK 50 TOP FOIL-WITH 0.45in2 BOTTOM FOIL WITH MANY FEEDTHROUGHS 45 40 TOP FOIL ONLY-NO SOLDER MASK 35 30 0 2 4 6 8 10 AREA OF CIRCUIT BOARD HEAT SINK (in2) TOP (16 Ld SO) FIGURE 45. THERMAL RESISTANCE of 20 LD SO (0.300") EL1508 vs BOARD COPPER AREA Power Control Function The EL1508 contains two forms of power control operation. Two digital inputs, C0 and C1, can be used to control the supply current of the EL1508 drive amplifiers. As the supply current is reduced, the EL1508 will start to exhibit slightly higher levels of distortion and the frequency response will be limited. The 4 power modes of the EL1508 are set up as shown in the following table: TABLE 1. POWER MODES OF THE EL1508 C1 C0 0 0 IS full power mode 0 1 2/3 IS power mode EL1508CM PCB Layout Considerations 1 0 1/3 IS power mode The 20 Ld SOIC (0.300") Power Package is designed so that heat may be conducted away from the device in an efficient manner. To disperse this heat, the center four leads on either side of the package are internally fused to the mounting platform of the die. Heat flows through the leads into the circuit board copper, then spreads and convects to air. Thus, the ground plane on the component side of the board becomes the heatsink. This has proven to be a very effective technique, but several aspects of board layout should be noted. First, the heat should not be shunted to internal copper layers of the board nor backside foil, since the feedthroughs and fiberglass of the board are not very thermally conductive. To obtain the best thermal resistance of the mounted part, θJA, the topside copper ground plane should have as much area as possible and be as thick as practical. If possible, the solder mask should be cut away from the EL1508 to improve thermal resistance. Finally, metal heatsinks can be placed against the board close to the part to draw heat toward the chassis. The graph below shows various θJAs for the 20 Ld SOIC mounted on different copper foil areas. 1 1 Power-down INTERNAL GROUND PLANE (16 Ld SO) 15 OPERATION Another method for controlling the power consumption of the EL1508 is to connect a resistor from the IADJ pin to ground. When the IADJ pin is grounded (the normal state), the supply current per channel is as per the specifications table on page 2. When a resistor is inserted, the supply current is scaled according to the “RSET vs IS” graphs in the Performance Curves section. Both methods of power control can be used simultaneously. In this case, positive and negative supply currents (per amp) are given by the equations below: 12.4mA I S + = 0.9mA + ------------------------------------------------------ × ( 2/3C 1 + 1/3C 0 ) ( 1 + R SET ÷ 1574Ω ) 12.4mA I S - = ------------------------------------------------------ × ( 2/3C 1 + 1/3C 0 ) ( 1 + R SET ÷ 1574Ω ) Output Loading While the drive amplifiers can output in excess of 500mA transiently, the internal metallization is not designed to carry more than 100mA of steady DC current and there is no FN7014.5 March 26, 2007 EL1508 current-limit mechanism. This allows safely driving rms sinusoidal currents of 2 x 100mA, or 200mA. This current is more than that required to drive line impedances to large output levels, but output short circuits cannot be tolerated. The series output resistor will usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is a serious hazard. The amplifiers are sensitive to capacitive loading. More than 25pF will cause peaking of the frequency response. The same is true of badly terminated lines connected without a series matching resistor. Output AC Coupling When in power-down mode, several volts of differential voltage may appear across the line driver outputs. If DC current path exists between the two outputs, large DC current can flow from the positive supply rail to the negative supply rail through the outputs. To avoid DC current flow, the most effective solution is to place DC blocking capacitors in series at the outputs, as shown by the 0.22µF capacitors in Figure 44. Single Supply Operation The EL1508 can also be powered from a single supply voltage. When operating in this mode, the GND pins can still be connected directly to GND. To calculate power dissipation, the equations in the previous section should be used, with VS equal to half the supply rail. Feedback Resistor Value The bandwidth and peaking of the amplifiers varies with supply voltage somewhat and with gain settings. The feedback resistor values can be adjusted to produce an optimal frequency response. Here is a series of resistor values that produce an optimal driver frequency response (1dB peaking) for different supply voltages and gains: TABLE 2. OPTIMUM DRIVER FEEDBACK RESISTOR FOR VARIOUS GAINS AND SUPPLY VOLTAGES DRIVER VOLTAGE GAIN SUPPLY VOLTAGE 2.5 5 10 ±5V 3.5k 3.25k 3k ±12V 3.5k 3.25k 3k Power Supplies The power supplies should be well bypassed close to the EL1508. A 2.2µF tantalum capacitor and a 0.1µF ceramic capacitor for each supply works well. Since the load currents are differential, they should not travel through the board copper and set up ground loops that can return to amplifier inputs. Due to the class AB output stage design, these currents have heavy harmonic content. If the ground terminal of the positive and negative bypass capacitors are connected to each other directly and then returned to circuit ground, no such ground loops will occur. This scheme is employed in the layout of the EL1508 demonstration board, and documentation can be obtained from the factory. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7014.5 March 26, 2007 EL1508 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 17 FN7014.5 March 26, 2007 EL1508 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN3 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN2 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 18 FN7014.5 March 26, 2007