DATASHEET

EL1503A
®
Data Sheet
March 26, 2007
High Power Differential Line Driver
Features
The EL1503A ADSL Line Driver contains two wideband
high-voltage drivers which are ideally suited for both ADSL
and HDSL2 applications. They can supply a 39.2VP-P signal
into a 22Ω load while exhibiting very low distortion. The
EL1503A also has a number of power saving features. The
IADJ pin can be used to set the maximum supply current and
the C0 and C1 pins can be used to digitally vary the supply
current to one of four modes. These modes include full
power, low power, terminate only and power down.
• High power ADSL driver
The EL1503A uses current-feedback type amplifiers, which
achieve a high slew rate while consuming moderate power.
They retain their frequency response over a wide range of
externally set gains. The EL1503A operates on ±5V to ±12V
supplies and consumes only 12.5mA per amplifier.
The device is supplied in a thermally-enhanced 20 Ld SOIC
(0.300”) and the small footprint (4x5mm) 24 Ld QFN
packages. Center pins on each side of the 20 Ld and 16 Ld
packages are used as ground connections and heat
spreaders. The QFN package has the potential for a low θJA
(<40°C/W) and dissipates heat by means of a thermal pad
that is soldered onto the PCB. All package options are
specified for operation over the full -40°C to +85°C
temperature range.
FN7039.2
• 39.2VP-P differential output drive into 22Ω
• 42.4VP-P differential output drive into 65Ω
• Driver 2nd/3rd harmonics of
-66dBc/-72dBc at 2VP-P into 100Ω differential
• Supply current of 12.5mA per amplifier
• Supply current control
• Power saving modes
• Standard surface-mount packages
• Ultra-small QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• ADSL line drivers
• HDSL2 line drivers
• Video distribution amplifiers
Pinouts
EL1503A
[20 LD SOIC (0.300”)]
TOP VIEW
18 VS+
VS- 3
A
+
20 VOUTB
21 VIN-B
22 NC
19 NC
-
23 VIN-A
19 VOUTB
VOUTA 2
-
NC 1
20 VIN-B
VIN-A 1
B
+
24 VOUTA
EL1503A
(24 LD QFN)
TOP VIEW
17 GND*
NC 2
18 NC
GND* 4
VS- 3
17 VS+
GND* 5
16 GND*
16 NC
GND* 6
15 GND*
NC 5
15 NC
GND* 7
14 GND*
NC 6
14 NC
VIN+A 8
13 VIN+B
THERMAL
PAD
NC 4
13 GND
1
VIN+B 12
IADJ 11
C0 10
C1 9
VIN+A 8
GND 7
C1 9
C0 10
POWER
CONTROL
LOGIC
12 IADJ
11 NC
*GND pins are heat spreaders
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2003, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL1503A
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
EL1503ACM
EL1503ACM
-
20 Ld SOIC (0.300")
MDP0027
EL1503ACM-T13
EL1503ACM
13”
20 Ld SOIC (0.300")
MDP0027
EL1503ACMZ (See Note)
EL1503ACMZ
-
20 Ld SOIC (0.300") (Pb-Free)
MDP0027
EL1503ACMZ-T13 (See Note)
EL1503ACMZ
13”
20 Ld SOIC (0.300") (Pb-Free)
MDP0027
EL1503ACL
1503ACL
-
24 Ld QFN
MDP0046
EL1503ACL-T7
1503ACL
7”
24 Ld QFN
MDP0046
EL1503ACL-T13
1503ACL
13”
24 Ld QFN
MDP0046
EL1503ACLZ (See Note)
1503ACLZ
-
24 Ld QFN (Pb-Free)
MDP0046
EL1503ACLZ-T7 (See Note)
1503ACLZ
7”
24 Ld QFN (Pb-Free)
MDP0046
EL1503ACLZ-T13 (See Note)
1503ACLZ
13”
24 Ld QFN (Pb-Free)
MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7039.2
March 26, 2007
EL1503A
s
Absolute Maximum Ratings (TA = +25°C)
VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28V
VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VS- Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -28V to 0.3V
Input C0/C1 to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Output Current from Driver (static) . . . . . . . . . . . . . . . . . . . . 100mA
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±12V, RF = 1.5kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
IS+(Full Power)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V
10
12.5
16
mA
IS-(Full Power)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V
-15
-11.5
-9
mA
IS+(Low Power)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = 5V, C1 = 0V
7
9
11.5
mA
IS-(Low Power)
Negative Supply Current per Amplifier
All outputs at 0V, C0 =5V, C1 = 0V
-10.5
-8
-6
mA
IS+(Terminate)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = 0V, C1 = 5V
4
5.1
7
mA
IS-(Terminate)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = 0V, C1 = 5V
-6
-4
-3
mA
IS+(Power Down)
Positive Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 5V
0.75
1.05
1.7
mA
IS-(Power Down)
Negative Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 5V
-0.5
-0.25
0.07
mA
IGND
GND Supply Current per Amplifier
All outputs at 0V
-1
mA
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-30
30
mV
ΔVOS
VOS Mismatch
-15
15
mV
IB+
Non-Inverting Input Bias Current
-15
15
µA
IB-
Inverting Input Bias Current
-50
50
µA
ΔIB-
IB- Mismatch
-30
30
µA
ROL
Transimpedance
0.4
eN
0.8
MΩ
Input Noise Voltage
3.5
nV/√ Hz
iN
-Input Noise Current
13
pA/√ Hz
VIH
Input High Voltage
C0 & C1 inputs
VIL
Input Low Voltage
C0 & C1 inputs
IIH1
Input High Current for C1
C1 = 5V
IIH0
Input High Current for C0
C0 = 5V
IIL
Input Low Current for C1or C0
C1 = 0V, C0 = 0V
2.7
V
0.8
V
1.5
8
µA
0.75
4
µA
-1
1
µA
OUTPUT CHARACTERISTICS
VOUT
Loaded Output Swing
RL = 65Ω
±10.3
±10.6
V
RL = 22Ω
±9.3
±9.8
V
450
mA
1
A
IOL
Linear Output Current
AV = 5, RL = 10Ω, f = 100kHz,
THD = --60dBc
IOUT
Output Current
VOUT = 1V, RL = 1Ω
3
FN7039.2
March 26, 2007
EL1503A
Electrical Specifications
PARAMETER
VS = ±12V, RF = 1.5kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
BW
-3dB Bandwidth
AV = +5
80
MHz
HD2
2nd Harmonic Distortion
fC = 1MHz, RL = 100Ω, VOUT = 2VP-P
-76
dBc
fC = 1MHz, RL = 25Ω, VOUT = 2VP-P
-72
dBc
fC = 1MHz, RL = 100Ω, VOUT = 2VP-P
-76
dBc
fC = 1MHz, RL = 25Ω, VOUT = 2VP-P
-72
dBc
1100
V/µs
HD3
3rd Harmonic Distortion
SR
VOUT from -8V to +8V Measured at ±4V
Slewrate
700
Typical Performance Curves
25
VS=±12V
AV=10
RL=100Ω
RF=1.5kΩ
RF=1.3kΩ
RF=1.82kΩ
GAIN (dB)
GAIN (dB)
25
20
RF=2.0kΩ
VS=±5V
AV=10
RL=100Ω
RF=1.5kΩ
RF=1.82kΩ
20
RF=2.0kΩ
RF=2.4kΩ
RF=2.43kΩ
RF=2.74kΩ
RF=2.74kΩ
15
100K
1M
15
100K
100M
10M
FREQUENCY (Hz)
RF=1.3kΩ
RF=1.82kΩ
GAIN (dB)
GAIN (dB)
RF=1.5kΩ
20
RF=2.0kΩ
VS=±5V
AV=10
RL=100Ω
20
RF=2.0kΩ
RF=2.4kΩ
RF=2.74kΩ
RF=2.74kΩ
1M
10M
FREQUENCY (Hz)
FIGURE 3. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (2/3 POWER MODE)
4
RF=1.82kΩ
RF=1.3kΩ
RF=1.5kΩ
RF=2.43kΩ
15
100K
100M
10M
FIGURE 2. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (FULL POWER MODE)
25
VS=±12V
AV=10
RL=100Ω
1M
FREQUENCY (Hz)
FIGURE 1. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (FULL POWER MODE)
25
RF=1.3kΩ
100M
15
100K
1M
100M
10M
FREQUENCY (Hz)
FIGURE 4. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (2/3 POWER MODE)
FN7039.2
March 26, 2007
EL1503A
Typical Performance Curves
25
VS=±12V
AV=10
RL=100Ω
RF=2.0kΩ
RF=1.82kΩ
GAIN (dB)
GAIN (dB)
25
(Continued)
20
RF=2.43kΩ
RF=2.74kΩ
15
100M
1M
10M
VS=±5V
AV=10
RL=100Ω
1M
FIGURE 6. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (TERMINATE MODE)
19
RF=1.3kΩ
RF=1.5kΩ
VS=±5V
AV=5
RL=100Ω
RF=1.5kΩ
RF=1.82kΩ
GAIN (dB)
GAIN (dB)
RF=1.82kΩ
14
14
RF=2.4kΩ
RF=2.0kΩ
RF=2.4k
RF=2.74kΩ
RF=2.74k
RF=2.0kΩ
9
100K
1M
10M
9
100K
100M
FREQUENCY (Hz)
VS=±12V
AV=5
RL=100Ω
100M
10M
FIGURE 8. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (FULL POWER MODE)
19
RF=1.3kΩ
RF=1.5kΩ
VS=±5V
AV=5
RL=100Ω
RF=1.5kΩ
RF=1.82kΩ
RF=2.0kΩ
GAIN (dB)
RF=1.82kΩ
GAIN (dB)
1M
FREQUENCY (Hz)
FIGURE 7. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (FULL POWER MODE)
19
100M
10M
FREQUENCY (Hz)
FIGURE 5. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (TERMINATE MODE)
VS=±12V
AV=5
RL=100Ω
RF=2.43kΩ
20
FREQUENCY (Hz)
19
RF=2.0kΩ
RF=2.74kΩ
15
100K
100K
RF=1.84kΩ
14
RF=2.0kΩ
RF=2.43kΩ
14
RF=2.4kΩ
RF=2.74kΩ
RF=2.74kΩ
9
100K
1M
10M
FREQUENCY (Hz)
FIGURE 9. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (2/3 POWER MODE)
5
100M
9
100K
1M
100M
10M
FREQUENCY (Hz)
FIGURE 10. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (2/3 POWER MODE)
FN7039.2
March 26, 2007
EL1503A
Typical Performance Curves
(Continued)
19
19
RF=2.0kΩ
RF=1.82kΩ
RF=2.43kΩ
RF=2.0kΩ
GAIN (dB)
GAIN (dB)
RF=1.82kΩ
14
RF=2.74kΩ
14
RF=2.4kΩ
RF=2.74kΩ
VS=±12V
AV=5
RL=100Ω
VS=±5V
AV=5
RL=100Ω
9
100K
1M
9
100K
100M
10M
1M
FREQUENCY (Hz)
FIGURE 11. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (TERMINATE MODE)
FIGURE 12. DRIVER DIFFERENTIAL FREQUENCY
RESPONSE vs RF (TERMINATE MODE)
100
100
25
POWER)
IS+ (FULL
R)
IS- (FULL POWE
10
10
IS (mA)
iN
iN (pA/√Hz)
eN (nV/√Hz)
20
ER)
IS+ (2/3 POW
IS- (2/3 POWER)
15
10
IS+
eN
IS- (TERMINATE)
5
1
10
100
1K
10K
1
100K
0
0
2
4
FREQUENCY (Hz)
FIGURE 13. DRIVER INPUT VOLTAGE and FEEDBACK
CURRENT NOISE vs FREQUENCY
8
10
12
0
SUPPLY REJECTION (dB)
SUPPLY REJECTION (dB)
6
VS (V)
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
0
LEFT
DRIVER
-20
-40
RIGHT
DRIVER
-60
-80
-100
10K
100M
10M
FREQUENCY (Hz)
100K
1M
10M
FREQUENCY (Hz)
100M
FIGURE 15. POSITIVE SUPPLY REJECTION vs FREQUENCY
6
-20
LEFT
DRIVER
-40
RIGHT
DRIVER
-60
-80
-100
10K
100K
1M
10M
FREQUENCY (Hz)
100M
FIGURE 16. NEGATIVE SUPPLY REJECTION vs FREQUENCY
FN7039.2
March 26, 2007
EL1503A
Typical Performance Curves
VS=±12V
AV=1
RL=1.5kΩ
100
2/3 POWER
10
1
FULL POWER
0
10K
VS=±5V
AV=1
RL=1.5kΩ
TERMINATE
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
100
(Continued)
100K
1M
10M
TERMINATE
10
2/3 POWER
1
FULL POWER
0
10K
100M
100K
FREQUENCY (Hz)
FIGURE 17. OUTPUT IMPEDANCE vs FREQUENCY
-45
HD (dB)
HD (dB)
VS=±5V
-45 AV=5
R =100Ω
-50 f L=1MHz
C
-55
HD3
-60
-65
HD3
-70
-75
-75
HD2
-80
1
5
9
13
17
-85
21
HD2
1
2
3
VOP-P (V)
6
7
8
-40
VS=±5V
-55 AV=5
RL=100Ω
f =1MHz
-60 C
VS=±5V
AV=5
RL=100Ω
fC=1MHz
-50
HD3
HD (dB)
HD (dB)
5
FIGURE 20. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (FULL POWER)
-50
-70
-75
-60
HD3
-70
HD2
-80
-85
4
VOP-P (V)
FIGURE 19. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (FULL POWER)
-65
100M
-40
-65
-85
10M
FIGURE 18. OUTPUT IMPEDANCE vs FREQUENCY
VS=±12V
AV=5
RL=100Ω
fC=1MHz
-55
1M
FREQUENCY (Hz)
1
5
9
HD2
13
17
21
VOP-P (V)
FIGURE 21. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (2/3 POWER)
7
-80
1
2
3
4
5
6
7
8
VOP-P (V)
FIGURE 22. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE
FN7039.2
March 26, 2007
EL1503A
Typical Performance Curves
(Continued)
-45
-40
VS=±5V
AV=5
RL=100Ω
-50 fC=1MHz
THD (dB)
THD (dB)
VS=±12V
-50 AV=5
RL=100Ω
-55 fC=1MHz
-60
2/3 POWER
-65
-70
-60
FULL POWER
-70
FULL POWER
2/3 POWER
-75
-80
1
5
9
13
17
-80
21
1
2
3
VOP-P (V)
4
5
6
7
8
VOP-P (V)
FIGURE 23. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs OUTPUT AMPLITUDE
FIGURE 24. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs OUTPUT AMPLITUDE
-60
-56
-62
-60
HD2
-64
HD2
-64
HD (dB)
HD (dB)
-66
-68
-70
-72
-68
-72
VS=±12V
AV=5
RL=100Ω
fC=1MHz
-74
HD3
-76
-78
1
3
5
7
9
11
13
15
17
HD3
-76
-80
19
1
2
VOP-P (V)
FIGURE 25. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (FULL POWER)
-54
-58
VS=±5V
AV=5
RL=100Ω
fC=1MHz
-60
-62
-60
HD (dB)
HD (dB)
-58
HD2
-62
-64
-66
6
HD2
-64
-66
HD3
-68
HD3
5
FIGURE 26. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (FULL POWER)
VS=±12V
AV=5
RL=100Ω
fC=1MHz
-56
4
3
VOP-P (V)
VS=±5V
AV=5
RL=100Ω
fC=1MHz
-70
-68
-70
1
3
5
7
9
11
13
15
17
19
VOP-P (V)
FIGURE 27. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (2/3 POWER)
8
-72
1
2
3
4
VOP-P (V)
5
6
FIGURE 28. DIFFERENTIAL HARMONIC DISTORTION vs
OUTPUT AMPLITUDE (2/3 POWER)
FN7039.2
March 26, 2007
EL1503A
Typical Performance Curves
(Continued)
-55
-55
2/3 POWER
-61
-63
FULL POWER
2/3 POWER
-61
-63
FULL POWER
-67
-67
1
3
7
5
15
11 13
9
VOP-P (V)
17
1
19
FIGURE 29. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs OUTPUT AMPLITUDE
2
3
4
VOP-P (V)
25
R MO D E
7
2/3 POWER MODE
20
MODE
TERMINATE
AV=10
RF=1.82kΩ
5
6
7
8
9
10
AV=10
RF=1.82kΩ
3.0
PEAKING (dB)
WE
FULL PO
15
TERMIN
2.5
1.5
2/3 POW
1.0
0.5
11
0
12
A TE M
FULL POWER
5
6
7
8
9
10
VS = ±12V
RSET to GND
IS+ (FULL POWER)
IS- (FULL POWER)
±IS (mA)
IS- 2/3 POWER)
IS+ (TERMINATE)
15
IS- 2/3 POWER)
10
IS+ (TERMINATE)
IS- (TERMINATE)
5
5
0
6
RSET (kΩ)
FIGURE 33. IS vs RSET
9
12
IS+ 2/3 POWER)
IS- (TERMINATE)
4
11
IS- (FULL POWER)
IS+ 2/3 POWER)
2
MODE
VS = ±5V
RSET to GND
IS+ (FULL POWER)
20
20
0
E
FIGURE 32. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE
25
25
10
ER MO
D
±VS (V)
FIGURE 31. DIFFERENTIAL BANDWIDTH vs SUPPLY
VOLTAGE
15
OD E
2.0
±VS (V)
±IS (mA)
6
3.5
30
0
5
FIGURE 30. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs OUTPUT AMPLITUDE
35
BW (MHz)
-59
-65
-65
10
VS=±5V
AV=5
RL=100Ω
fC=1MHz
-57
THD (dBc)
THD (dBc)
VS=±12V
A =5
-57 RV=100Ω
L
fC=1MHz
-59
8
10
0
2
4
6
8
10
RSET (kΩ)
FIGURE 34. IS vs RSET
FN7039.2
March 26, 2007
EL1503A
25
VS = ±12V
O
LP
25
R)
WE
R)
WE
L
PO
R)
( FU
LL
WE
I S+ - (FU /3 PO R)
(2
IS
WE
I S+
PO
( 2 /3
IS
T E)
MINA
T ER
(
+
IS
E)
INAT
E RM
I - (T
20
±IS (mA)
(Continued)
15
10
VS = ±12V
)
ER
OW
P
)
LL
ER
(FU OW
R)
I S+ LL P
WE
(FU 2/3 PO R)
(
E
IS
I S+
POW
2/3
(
IS
E)
INAT
ERM
E)
I S+ (T
T
A
IN
E RM
I S- (T
20
±IS (mA)
Typical Performance Curves
15
10
S
5
0
5
0
100
200
300
400
0
500
0
100
200
ISET (µA)
FIGURE 35. IS vs ISET
2.0
θJA = 53°C/W
1.5
θJA = 80°C/W
1.0
0.5
0
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
FIGURE 37. POWER DISSIPATION vs AMBIENT
TEMPERATURE for VARIOUS MOUNTED θJAs
10
2.5
2.703W
2.0
A
2.5
POWER DISSIPATION & THERMAL RESISTANCE USING
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
θJ
POWER DISSIPATION (W)
3.0
θJA = 43°C/W
500
24
W
F N °C /
Q
7
=3
POWER DISSIPATION (W)
3.0
θJA = 30°C/W
3.5
400
FIGURE 36. IS vs ISET
4.5
4.0
300
ISET (µA)
1.5
1.0
0.5
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 38. POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7039.2
March 26, 2007
EL1503A
Test Circuit
1 VIN-A
VIN-B 20
2 VOUTA
VOUTB 19
3 VS-
VS+ 18
4 GND
GND 17
5 GND
GND 16
6 GND
GND 15
7 GND
GND 14
8 VIN+A
VIN+B 13
9 C1
IADJ 12
10 C0
NC 11
RS
100
1W
R3
R4
56Ω
1/2W
56Ω
1/2W
332Ω
R7
20
2
19
3
0.1µF
5µF
TANTALUM
C2
GND
LEFT
DRIVER
IN
R2
R16
1
A
+
LEFT
DRIVER
OUT
-
1.5kΩ
-
B
+
1.5kΩ
RIGHT
DRIVER
OUT
18
5µF
4
17
5
16
6
15
7
14
8
13
9
12
0.1µF
VS+
TANTALUM
C1
GND
R17
51Ω
RIGHT
DRIVER
IN
51Ω
10
C1
11
11
RSET
C0
FN7039.2
March 26, 2007
EL1503A
Pin Descriptions
20 Ld SOIC
(0.300")
24 Ld QFN
PIN NAME
1
23
VIN-A
FUNCTION
CIRCUIT
Channel A Inverting Input
CIRCUIT 1
2
24
VOUTA
3
3
VS-
Negative Supply
4, 5, 6, 7
7
GND
Ground Connection
8
8
VIN+A
Channel A Output
Channel A Non-Inverting Input
(Reference Circuit 1)
VS+
VS-
CIRCUIT 2
9
9
C1
Current Control Bit 1
VS+
6.7V
CIRCUIT 3
10
10
C0
Current Control Bit 0
11
1, 2, 4, 5, 6, 14,
15, 16, 18, 19,
22
NC
Not Connected
12
11
IADJ
Supply Current Control Pin
(Reference Circuit 3)
VS+
CIRCUIT 4
13
12
VIN+B
14, 15, 16, 17
13
GND
Ground Connection
18
17
VS+
Positive Supply
19
20
VOUTB
20
21
VIN-B
-
7
12
Channel B Non-Inverting Input
(Reference Circuit 2)
Channel B Output
(Reference Circuit 1)
Channel B Inverting Input
(Reference Circuit 1)
Reserve for Future Use
Internally Unconnected
FN7039.2
March 26, 2007
EL1503A
Applications Information
The EL1503A consists of two high-power line driver
amplifiers that can be connected for full duplex differential
line transmission. The amplifiers are designed to be used
with signals up to 4MHz and produce low distortion levels. A
typical interface circuit is shown in Figure 39 below.
DRIVER
INPUT
ROUT
+
-
LINE +
RF
RG
ZLINE
RF
ROUT
+
LINE RF
RECEIVE
OUT +
R
RIN
+
RECEIVE
AMPLIFIERS
Power Supplies & Dissipation
Due to the high power drive capability of the EL1503A, much
attention needs to be paid to power dissipation. The power
that needs to be dissipated in the EL1503A has two main
contributors. The first is the quiescent current dissipation.
The second is the dissipation of the output stage.
The quiescent power in the EL1503A is not constant with
varying outputs. In reality, 7mA of the 12.5mA needed to
power each driver is converted in to output current.
Therefore, in the equation below we should subtract the
average output current, IO, or 7mA, whichever is the lowest.
We’ll call this term IX.
Therefore, we can determine a quiescent current with the
equation:
+
-
R
RF
RECEIVE
OUT -
can cause ringing or even oscillations. This inductance is
equivalent to about 4” of unshielded wiring, or 6” of
unterminated transmission line. Normal high-frequency
construction obviates any such problem.
RIN
P Dquiescent = V S × ( I S – 2I X )
where:
FIGURE 39. TYPICAL LINE INTERFACE CONNECTION
The amplifiers are wired with one in positive gain and the
other in a negative gain configuration to generate a
differential output for a single-ended input. They will exhibit
very similar frequency responses for gains of three or
greater and thus generate very small common-mode outputs
over frequency, but for low gains the two drivers RF's need
to be adjusted to give similar frequency responses. The
positive-gain driver will generally exhibit more bandwidth and
peaking than the negative-gain driver.
If a differential signal is available to the drive amplifiers, they
may be wired so:
+
-
2RG
RF
RF
+
FIGURE 40. DRIVERS WIRED FOR DIFFERENTIAL INPUT
Each amplifier has identical positive gain connections, and
optimum common-mode rejection occurs. Further, DC input
errors are duplicated and create common-mode rather than
differential line errors.
Input Connections
The EL1503A amplifiers are somewhat sensitive to source
impedance. In particular, they do not like being driven by
inductive sources. More than 100nH of source impedance
13
VS is the supply voltage (VS+ to VS-)
IS is the maximum quiescent supply current (IS+ + IS-)
IX is the lesser of IO or 7mA (generally IX = 7mA)
The dissipation in the output stage has two main
contributors. Firstly, we have the average voltage drop
across the output transistor and secondly, the average
output current. For minimal power dissipation, the user
should select the supply voltage and the line transformer
ratio accordingly. The supply voltage should be kept as low
as possible, while the transformer ratio should be selected
so that the peak voltage required from the EL1503A is close
to the maximum available output swing. There is a trade of
however with the selection of transformer ratio. As the ratio
is increased, the receive signal available to the receivers is
reduced.
Once the user has selected the transformer ratio, the
dissipation in the output stages can be selected with the
following equation:
VS
P Dtransistors = 2 × I O × ⎛ ------- – V O ⎞
⎝ 2
⎠
where:
VS is the supply voltage (VS+ to VS-)
VO is the average output voltage per channel
IO is the average output current per channel
The overall power dissipation (PDISS) is obtained by adding
PDquiescent and PDtransistor.
FN7039.2
March 26, 2007
EL1503A
Then, the θJA requirement needs to be calculated. This is
done using the equation:
( T JUNCT – T AMB )
θ JA = ------------------------------------------------P DISS
where:
TJUNCT is the maximum die temperature (150°C)
TAMB is the maximum ambient temperature
PDISS is the dissipation calculated above
θJA is the junction to ambient thermal resistance for the
package when mounted on the PCB
This θJA value is then used to calculate the area of copper
needed on the board to dissipate the power. The graph
below show various θJA for the SO20 mounted on different
copper foil areas.
MOUNTED DEVICE θJA (°C/W)
55
Note: 2oz. COPPER USED
50
TOP FOIL ONLY-WITH SOLDER MASK
TOP FOIL-WITH 0.45IN2 BOTTOM
FOIL WITH MANY FEEDTHROUGHS
45
Output Loading
While the drive amplifiers can output in excess of 500mA
transiently, the internal metallization is not designed to carry
more than 100mA of steady DC current and there is no
current-limit mechanism. This allows safely driving rms
sinusoidal currents of 2 X 100mA, or 200mA. This current is
more than that required to drive line impedances to large
output levels, but output short circuits cannot be tolerated.
The series output resistor will usually limit currents to safe
values in the event of line shorts. Driving lines with no series
resistor is a serious hazard.
The amplifiers are sensitive to capacitive loading. More than
25pF will cause peaking of the frequency response. The
same is true of badly terminated lines connected without a
series matching resistor.
40
TOP FOIL ONLY-NO SOLDER MASK
35
technique, but several aspects of board layout should be
noted. First, the heat should not be shunted to internal
copper layers of the board nor backside foil, since the
feedthroughs and fiberglass of the board are not very
thermally conductive. To obtain the best thermal resistance
of the mounted part, θJA, the topside copper ground plane
should have as much area as possible and be as thick as
practical. If possible, the solder mask should be cut away
from the EL1503A to improve thermal resistance. Finally,
metal heatsinks can be placed against the board close to the
part to draw heat toward the chassis.
Power Supplies
30
0
1
2
3
4
5
6
7
8
9
10
AREA OF CIRCUIT BOARD HEAT SINK (in2)
FIGURE 41. THERMAL RESISTANCE of 20 Ld SOIC (0.300")
EL1503A vs BOARD COPPER AREA
A separate application note details the 24 Ld QFN PCB
design considerations.
Single Supply Operation
The EL1503A can also be powered from a single supply
voltage. When operating in this mode, the GND pins can still
be connected directly to GND. To calculate power
dissipation, the equations in the previous section should be
used, with VS equal to half the supply rail.
EL1503A PCB Design
A separate application note details the 24 Ld QFN PCB
design considerations. The SOIC power packages
(20 leads) are designed so that heat may be conducted
away from the device in an efficient manner. To disperse this
heat, the center leads (4 per side for the 20 lead and 2 per
side for the 16 lead) are internally connected to the mounting
platform of the die. Heat flows through the leads into the
circuit board copper, then spreads and convects to air. Thus,
the ground plane on the component side of the board
becomes the heatsink. This has proven to be a very effective
14
The power supplies should be well bypassed close to the
EL1503A. A 3.3µF tantalum capacitor for each supply works
well. Since the load currents are differential, they should not
travel through the board copper and set up ground loops that
can return to amplifier inputs. Due to the class AB output
stage design, these currents have heavy harmonic content.
If the ground terminal of the positive and negative bypass
capacitors are connected to each other directly and then
returned to circuit ground, no such ground loops will occur.
This scheme is employed in the layout of the EL1503A
demonstration board, and documentation can be obtained
from the factory.
Feedback Resistor Value
The bandwidth and peaking of the amplifiers varies with
supply voltage somewhat and with gain settings. The
feedback resistor values can be adjusted to produce an
optimal frequency response. Here is a series of resistor
values that produce an optimal driver frequency response
(1dB peaking) for different supply voltages and gains:
TABLE 1. OPTIMUM DRIVER FEEDBACK RESISTOR for
VARIOUS GAINS and SUPPLY VOLTAGES
DRIVER VOLTAGE GAIN
SUPPLY
VOLTAGE
2.5
5
10
±5V
±12V
2.7k
2.2k
2.2k
2.0k
2.0k
2.0k
FN7039.2
March 26, 2007
EL1503A
Power Control Function
The EL1503A contains two forms of power control operation.
Two digital inputs, C0 and C1, can be used to control the
supply current of the EL1503A drive amplifiers. As the
supply current is reduced, the EL1503A will start to exhibit
slightly higher levels of distortion and the frequency
response will be limited. The 4 power modes of the EL1503A
are set up as shown in the table 2.
TABLE 2. POWER MODES of the EL1503A
C1
C0
OPERATION
0
0
IS full power mode (CO or CP)
0
1
2/3 IS power mode (CO or CP)
1
0
1/3 IS terminate only mode
1
1
Power down
Another method for controlling the power consumption of the
EL1503A is to connect a resistor from the IADJ pin to ground.
When this pin is grounded (the normal state), the supply
current per channel is as per the specifications table on page
3. When a resistor is inserted, the supply current is scaled
according to the “IS vs RSET” graphs on page 10 in the
Performance Curves section.
Both methods of power control can be used simultaneously.
In this case, positive and negative supply currents (per amp)
are given by the equations below:
12.5mA
I S + = 1mA + ( C 1 × 2 ⁄ 3 ) × ------------------------------------------( 1 + R SET ÷ 1k )
12.5mA
+ ( C 0 × 1 ⁄ 3 ) × ------------------------------------------( 1 + R SET ÷ 1k )
12.5mA
I S - = 0 + ( C 1 × 2 ⁄ 3 ) × ------------------------------------------( 1 + R SET ÷ 1k )
12.5mA
+ ( C 0 × 1 ⁄ 3 ) × ------------------------------------------( 1 + R SET ÷ 1k )
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN7039.2
March 26, 2007
EL1503A
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
16
FN7039.2
March 26, 2007
EL1503A
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
0.10 M C A B
(N-2)
(N-1)
N
b
L
SYMBOL QFN44 QFN3
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
Basic
-
Reference
8
Basic
-
Reference
8
Basic
-
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
1
2
3
6.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
0.50
L
0.55
0.40
0.53
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
MILLIMETERS
PIN #1 I.D.
3
QFN32
SYMBOL QFN28 QFN2
QFN20
QFN16
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SEATING
PLANE
TOLERANCE NOTES
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 11 2/07
0.08 C
N LEADS
& EXPOSED PAD
SEE DETAIL "X"
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
C
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
2
A
(L)
A1
N LEADS
DETAIL X
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
17
FN7039.2
March 26, 2007