Si5513CDC Datasheet

Si5513CDC
Vishay Siliconix
N- and P-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
N-Channel
20
P-Channel
- 20
RDS(on) (Ω)
ID (A)a Qg (Typ.)
0.055 at VGS = 4.5 V
4g
0.085 at VGS = 2.5 V
4g
0.150 at VGS = - 4.5 V
- 3.7
0.255 at VGS = - 2.5 V
- 2.9
2.6 nC
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFETs
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
3.6 nC
APPLICATIONS
• Load Switch for Portable Devices
1206-8 ChipFET®
D1
1
S2
S1
D1
G1
D1
D2
G2
Marking Code
S2
G2
EG
D2
XXX
G1
Lot Traceability
and Date Code
Part # Code
Bottom View
Ordering Information: Si5513CDC-T1-E3 (Lead (Pb)-free)
Si5513CDC-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
D2
N-Channel MOSFET
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
VDS
VGS
Drain-Source Voltage
Gate-Source Voltage
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Source Drain Current Diode Current
Maximum Power Dissipation
ID
IS
PD
4g
4g
- 3.7
- 3.0
4b, c, g
3.5b, c
10
2.6
- 2.4b, c
- 1.9b, c
-8
- 2.6
1.4b, c
3.1
2.0
- 1.7b, c
3.1
2.0
1.7b, c
1.1b, c
1.3b, c
0.8b, c
TJ, Tstg
Operating Junction and Storage Temperature Range
P-Channel
- 20
± 12
IDM
Pulsed Drain Current
Soldering Recommendations (Peak Temperature)
N-Channel
20
- 55 to 150
d, e
Unit
V
A
W
°C
260
THERMAL RESISTANCE RATINGS
N-Channel
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Foot (Drain)
t≤5s
Steady State
Symbol
RthJA
RthJF
P-Channel
Typ.
Max.
Typ.
Max.
Unit
62
32
74
40
77
33
95
40
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequade bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 115 °C/W for N-Channel and 130 °C/W for P-Channel.
g. Package limited.
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
1
Si5513CDC
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate Threshold Voltage
Gate-Body Leakage
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
N-Ch
20
VGS = 0 V, ID = - 250 µA
P-Ch
- 20
ID = 250 µA
N-Ch
23.7
ID = - 250 µA
P-Ch
- 19.5
ID = 250 µA
N-Ch
- 3.5
2.8
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
IDSS
ID(on)
RDS(on)
gfs
mV/°C
ID = - 250 µA
P-Ch
VDS = VGS, ID = 250 µA
N-Ch
0.6
1.5
VDS = VGS, ID = - 250 µA
P-Ch
- 0.6
- 1.5
VDS = 0 V, VGS = ± 12 V
VDS = 20 V, VGS = 0 V
Zero Gate Voltage Drain Current
V
N-Ch
100
P-Ch
- 100
N-Ch
1
VDS = - 20 V, VGS = 0 V
P-Ch
-1
VDS = 20 V, VGS = 0 V, TJ = 55 °C
N-Ch
10
VDS = - 20 V, VGS = 0 V, TJ = 55 °C
P-Ch
- 10
VDS ≥ 5 V, VGS = 4.5 V
N-Ch
10
VDS ≤ - 5 V, VGS = - 4.5 V
P-Ch
-8
VGS = 4.5 V, ID = 4.4 A
N-Ch
0.045
VGS = - 4.5 V, ID = - 2.4 A
P-Ch
0.120
0.150
VGS = 2.5 V, ID = 3.6 A
N-Ch
0.065
0.085
VGS = - 2.5 V, ID = - 1.9 A
P-Ch
0.204
0.255
VDS = 10 V, ID = 4.4 A
N-Ch
12
VDS = - 10 V, ID = - 2.4 A
P-Ch
5
N-Ch
285
P-Ch
252
V
nA
µA
A
0.055
Ω
S
Dynamica
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
N-Channel
VDS = 10 V, VGS = 0 V, f = 1 MHz
Coss
Crss
P-Channel
VDS = - 10 V, VGS = 0 V, f = 1 MHz
VDS = 10 V, VGS = 5 V, ID = 4.4 A
Total Gate Charge
Gate-Source Charge
Qg
VDS = - 10 V, VGS = - 5 V, ID = - 2.4 A
65
P-Ch
62
N-Ch
30
P-Ch
45
N-Ch
2.8
3.9
5.6
2.6
3.9
5.4
P-Ch
3.6
0.7
P-Ch
0.6
N-Ch
0.5
P-Ch
1.2
Gate-Drain Charge
Qgd
Gate Resistance
Rg
f = 1 MHz
4.2
P-Ch
N-Ch
Qgs
pF
N-Ch
N-Channel
VDS = 10 V, VGS = 4.5 V, ID = 4.4 A
P-Channel
VDS = - 10 V, VGS = - 4.5 V, ID = - 2.4 A
www.vishay.com
2
N-Ch
N-Ch
0.6
3
6
P-Ch
1.3
6.5
13
nC
Ω
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
Si5513CDC
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
N-Ch
5
10
P-Ch
4
8
N-Ch
10
20
18
Unit
Dynamica
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(on)
tr
td(off)
tf
td(on)
tr
N-Channel
VDD = 10 V, RL = 2.9 Ω
ID ≅ 3.5 A, VGEN = 10 V, Rg = 1 Ω
P-Channel
VDD = - 10 V, RL = 5.3 Ω
ID ≅ - 1.9 A, VGEN = - 10 V, Rg = 1 Ω
N-Channel
VDD = 10 V, RL = 2.9 Ω
ID ≅ 3.5 A, VGEN = 4.5 V, Rg = 1 Ω
tf
P-Channel
VDD = - 10 V, RL = 5.3 Ω
ID ≅ - 1.9 A, VGEN = - 4.5 V, Rg = 1 Ω
IS
TC = 25 °C
td(off)
P-Ch
12
N-Ch
14
21
P-Ch
15
23
N-Ch
6
12
P-Ch
6
12
N-Ch
8
16
P-Ch
19
29
N-Ch
9
18
P-Ch
40
60
N-Ch
16
24
P-Ch
18
27
N-Ch
8
16
P-Ch
8
16
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Currenta
Body Diode Voltage
Body Diode Reverse Recovery Time
ISM
VSD
N-Ch
2.6
P-Ch
- 2.6
N-Ch
10
P-Ch
-8
IS = 3.5 A, VGS = 0 V
N-Ch
0.8
1.2
IS = - 1.9 A, VGS = 0 V
P-Ch
- 0.8
- 1.2
trr
Body Diode Reverse Recovery Charge
Qrr
N-Channel
IF = 3.5 A, dI/dt = 100 A/µs, TJ = 25 °C
Reverse Recovery Fall Time
ta
P-Channel
IF = - 1.9 A, dI/dt = - 100 A/µs, TJ = 25 °C
Reverse Recovery Rise Time
tb
A
N-Ch
10
15
P-Ch
15
22.5
N-Ch
3
4.5
P-Ch
9
13.5
N-Ch
6
P-Ch
10
N-Ch
4
P-Ch
5
V
ns
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
3
Si5513CDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
5
VGS = 5 V thru 2.5 V
4
I D - Drain Current (A)
I D - Drain Current (A)
8
6
VGS = 2 V
4
2
3
2
TC = 25 °C
1
TC = 125 °C
VGS = 1.5 V
0
0
1
2
3
4
5
0.5
1.0
1.5
2.0
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.10
2.5
400
0.08
320
VGS = 2.5 V
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
TC = - 55 °C
0
0.0
0.06
VGS = 4.5 V
0.04
Ciss
240
160
0.02
80
0.00
0
Coss
Crss
0
2
4
6
8
10
0
4
8
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
20
1.6
10
VGS = 4.5 V; ID = 4.4 A
ID = 4.4 A
1.4
VDS = 10 V
6
VDS = 16 V
4
(Normalized)
8
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
12
1.2
VGS = 2.5 V; ID = 3.6 A
1.0
0.8
2
0
0
www.vishay.com
4
1
2
3
4
5
6
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
150
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
Si5513CDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.10
100
10
TJ = 150 °C
TJ = 25 °C
1
0.1
0.0
0.08
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 4.4 A
TJ = 125 °C
0.06
0.04
TJ = 25 °C
0.02
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
2
4
VSD - Source-to-Drain Voltage (V)
6
8
10
12
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
1.3
30
25
1.1
Power (W)
VGS(th) (V)
20
0.9
ID = 250 µA
15
10
0.7
5
0.5
- 50
- 25
0
25
50
75
100
125
0
10-4
150
10-3
10-2
10-1
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
1
10
100
Limited by RDS(on)*
I D - Drain Current (A)
10
100 µs
1 ms
1
10 ms
100 ms
1 s, 10 s
0.1
TA = 25 °C
Single Pulse
0.01
0.1
DC
BVDSS Limited
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
5
Si5513CDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
8
I D - Drain Current (A)
6
Package Limited
4
2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
4.0
1.5
3.2
1.2
Power (W)
Power (W)
Current Derating*
2.4
1.6
0.8
0.9
0.6
0.3
0.0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Foot
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
6
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
Si5513CDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 95 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10 -4
4. Surface Mounted
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
100
10
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
7
Si5513CDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
8
2.0
I D - Drain Current (A)
I D - Drain Current (A)
VGS = 5 V thru 3 V
6
VGS = 2.5 V
4
VGS = 2 V
2
1.5
1.0
TC = 25 °C
0.5
TC = 125 °C
VGS = 1.5 V
0
0
1
2
3
4
TC = - 55 °C
0.0
0.0
5
0.5
VDS - Drain-to-Source Voltage (V)
1.5
2.0
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.30
450
0.25
360
VGS = 2.5 V
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
1.0
0.20
0.15
VGS = 4.5 V
0.10
Ciss
270
180
Coss
90
0.05
Crss
0.00
0
0
2
4
6
8
0
4
8
12
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
20
1.6
10
1.4
8
VDS = 10 V
6
VDS = 16 V
4
VGS = - 4.5 V; I D = - 2.4 A
(Normalized)
RDS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
ID = 2.4 A
1.2
VGS = - 2.5 V; I D = - 1.9 A
1.0
0.8
2
0
0
2
4
6
Qg - Total Gate Charge (nC)
Gate Charge
www.vishay.com
8
8
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
Si5513CDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.30
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = - 2.4 A
10
TJ = 150 °C
TJ = 25 °C
1
0.1
0.0
0.24
0.18
TJ = 125 °C
0.12
TJ = 25 °C
0.06
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
2
1.1
50
1.0
40
Power (W)
VGS(th) (V)
60
0.9
ID = 250 µA
20
0.7
10
25
50
75
100
10
12
30
0.8
0
8
On-Resistance vs. Gate-to-Source Voltage
1.2
- 25
6
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0.6
- 50
4
125
0
0.0001
150
0.001
0.01
0.1
1
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
10
100
10
Limited by RDS(on)*
I D - Drain Current (A)
100 µs
1
1 ms
10 ms
100 ms
0.1
1 s, 10 s
DC
TA = 25 °C
Single Pulse
0.01
0.1
BVDSS Limited
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Case
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
9
Si5513CDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
5
I D - Drain Current (A)
4
3
2
1
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating*
1.2
4.0
3.2
Power (W)
Power (W)
0.9
2.4
1.6
0.6
0.3
0.8
0.0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
10
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
Si5513CDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 105 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
100
10
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68806.
Document Number: 68806
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
11
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
7
6
5
4
1
S
2
e
3
E1
5
6
7
8
4
3
2
1
E
4
b
x
c
Backside View
2X 0.10/0.13 R
C1
A
DETAIL X
NOTES:
1.
All dimensions are in millimeaters.
2.
Mold gate burrs shall not exceed 0.13 mm per side.
3.
Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4.
Dimensions exclusive of mold gate burrs.
5.
No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
Dim
A
b
c
c1
D
E
E1
e
L
S
INCHES
Min
Nom
Max
Min
Nom
Max
1.00
−
1.10
0.039
−
0.043
0.25
0.30
0.35
0.010
0.012
0.014
0.1
0.15
0.20
0.004
0.006
0.008
0
−
0.038
0
−
0.0015
2.95
3.05
3.10
0.116
0.120
0.122
1.825
1.90
1.975
0.072
0.075
0.078
1.55
1.65
1.70
0.061
0.065
0.067
0.65 BSC
0.28
−
0.0256 BSC
0.42
0.011
−
0.55 BSC
0.022 BSC
5_Nom
5_Nom
0.017
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
www.vishay.com
1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
80 mil
25 mil
43 mil
18 mil
10 mil
26 mil
PIN-OUT
FIGURE 2.
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
Dual 1206-8 ChipFET
S1
G1
S2
Footprint With Copper Spreading
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
G2
D1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D1
D2
D2
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71127
12-Dec-03
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
www.vishay.com
1
AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30_C/W typical, 40_C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the dual-channel 1206-8 ChipFET is
90_C/W steady state, identical to the SO-8. Maximum ratings
are 110_C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
200
Min. Footprint
160
Thermal Resistance (C/W)
THERMAL PERFORMANCE
Dual EVB
120
80
40
1” Square PCB
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the Dual 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
185_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
128_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
90_C/W
www.vishay.com
2
0
10-5 10-4
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126).
Document Number: 71127
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
0.036
(0.914)
0.022
(0.559)
(2.032)
0.080
(2.357)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
www.vishay.com
2
Document Number: 72593
Revision: 21-Jan-08
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000